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s/flag_reg_nr/flag_subreg_nr for an instruction

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s/flagreg/flag_subreg_nr for a condition

They are flag subregister number indeed

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
This commit is contained in:
Xiang, Haihao 2012-07-17 14:18:54 +08:00 committed by Damien Lespiau
parent 968d2d7ef6
commit 2f772dd67b
4 changed files with 18 additions and 18 deletions
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8
assembler/src/brw_structs.h
View File

@ -1134,7 +1134,7 @@ struct brw_instruction
GLuint src0_horiz_stride:2; /* 0x00030000 */ GLuint src0_horiz_stride:2; /* 0x00030000 */
GLuint src0_width:3; /* 0x001c0000 */ GLuint src0_width:3; /* 0x001c0000 */
GLuint src0_vert_stride:4; /* 0x01e00000 */ GLuint src0_vert_stride:4; /* 0x01e00000 */
GLuint flag_reg_nr:1; /* 0x02000000 */ GLuint flag_subreg_nr:1; /* 0x02000000 */
GLuint pad:6; /* 0xfc000000 */ GLuint pad:6; /* 0xfc000000 */
} da1; } da1;
@ -1148,7 +1148,7 @@ struct brw_instruction
GLuint src0_horiz_stride:2; GLuint src0_horiz_stride:2;
GLuint src0_width:3; GLuint src0_width:3;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_reg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad:6; GLuint pad:6;
} ia1; } ia1;
@ -1165,7 +1165,7 @@ struct brw_instruction
GLuint src0_swz_w:2; GLuint src0_swz_w:2;
GLuint pad0:1; GLuint pad0:1;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_reg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad1:6; GLuint pad1:6;
} da16; } da16;
@ -1182,7 +1182,7 @@ struct brw_instruction
GLuint src0_swz_w:2; GLuint src0_swz_w:2;
GLuint pad0:1; GLuint pad0:1;
GLuint src0_vert_stride:4; GLuint src0_vert_stride:4;
GLuint flag_reg_nr:1; GLuint flag_subreg_nr:1;
GLuint pad1:6; GLuint pad1:6;
} ia16; } ia16;

4
assembler/src/disasm.c
View File

@ -780,8 +780,8 @@ int disasm (FILE *file, struct brw_instruction *inst)
string (file, "("); string (file, "(");
err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
string (file, "f0"); string (file, "f0");
if (inst->bits2.da1.flag_reg_nr) if (inst->bits2.da1.flag_subreg_nr)
format (file, ".%d", inst->bits2.da1.flag_reg_nr); format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
if (inst->header.access_mode == BRW_ALIGN_1) if (inst->header.access_mode == BRW_ALIGN_1)
err |= control (file, "predicate control align1", pred_ctrl_align1, err |= control (file, "predicate control align1", pred_ctrl_align1,
inst->header.predicate_control, NULL); inst->header.predicate_control, NULL);

2
assembler/src/gen4asm.h
View File

@ -49,7 +49,7 @@ struct direct_reg {
struct condition { struct condition {
int cond; int cond;
int flagreg; int flag_subreg_nr;
}; };
struct region { struct region {

22
assembler/src/gram.y
View File

@ -389,8 +389,8 @@ unaryinstruction:
if (set_instruction_src0(&$$, &$7) != 0) if (set_instruction_src0(&$$, &$7) != 0)
YYERROR; YYERROR;
if ($3.flagreg != -1) if ($3.flag_subreg_nr != -1)
$$.bits2.da1.flag_reg_nr = $3.flagreg; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -419,8 +419,8 @@ binaryinstruction:
if (set_instruction_src1(&$$, &$8) != 0) if (set_instruction_src1(&$$, &$8) != 0)
YYERROR; YYERROR;
if ($3.flagreg != -1) if ($3.flag_subreg_nr != -1)
$$.bits2.da1.flag_reg_nr = $3.flagreg; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -449,8 +449,8 @@ binaryaccinstruction:
if (set_instruction_src1(&$$, &$8) != 0) if (set_instruction_src1(&$$, &$8) != 0)
YYERROR; YYERROR;
if ($3.flagreg != -1) if ($3.flag_subreg_nr != -1)
$$.bits2.da1.flag_reg_nr = $3.flagreg; $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
if (gen_level < 6 && if (gen_level < 6 &&
get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
@ -2291,7 +2291,7 @@ imm32: exp { $$.r = imm32_d; $$.u.d = $1; }
predicate: /* empty */ predicate: /* empty */
{ {
$$.header.predicate_control = BRW_PREDICATE_NONE; $$.header.predicate_control = BRW_PREDICATE_NONE;
$$.bits2.da1.flag_reg_nr = 0; $$.bits2.da1.flag_subreg_nr = 0;
$$.header.predicate_inverse = 0; $$.header.predicate_inverse = 0;
} }
| LPAREN predstate flagreg predctrl RPAREN | LPAREN predstate flagreg predctrl RPAREN
@ -2301,7 +2301,7 @@ predicate: /* empty */
* set a predicate for one flag register and conditional * set a predicate for one flag register and conditional
* modification on the other flag register. * modification on the other flag register.
*/ */
$$.bits2.da1.flag_reg_nr = $3.subreg_nr; $$.bits2.da1.flag_subreg_nr = $3.subreg_nr;
$$.header.predicate_inverse = $2; $$.header.predicate_inverse = $2;
} }
; ;
@ -2360,12 +2360,12 @@ saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
conditionalmodifier: condition conditionalmodifier: condition
{ {
$$.cond = $1; $$.cond = $1;
$$.flagreg = -1; $$.flag_subreg_nr = -1;
} }
| condition DOT flagreg | condition DOT flagreg
{ {
$$.cond = $1; $$.cond = $1;
$$.flagreg = $3.subreg_nr; $$.flag_subreg_nr = $3.subreg_nr;
} }
condition: /* empty */ { $$ = BRW_CONDITIONAL_NONE; } condition: /* empty */ { $$ = BRW_CONDITIONAL_NONE; }
@ -2848,7 +2848,7 @@ void set_instruction_predicate(struct brw_instruction *instr,
{ {
instr->header.predicate_control = predicate->header.predicate_control; instr->header.predicate_control = predicate->header.predicate_control;
instr->header.predicate_inverse = predicate->header.predicate_inverse; instr->header.predicate_inverse = predicate->header.predicate_inverse;
instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr; instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr;
} }
void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg,