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https://github.com/tiagovignatti/intel-gpu-tools.git
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intel_reg_dumper: handle 3 pipe configs when dumping HDMI config
Could be on pipe A, B, or C. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -3261,6 +3261,7 @@ typedef enum {
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/* CPU: FDI_TX */
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/* CPU: FDI_TX */
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#define FDI_TXA_CTL 0x60100
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#define FDI_TXA_CTL 0x60100
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#define FDI_TXB_CTL 0x61100
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#define FDI_TXB_CTL 0x61100
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#define FDI_TXC_CTL 0x62100
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#define FDI_TX_DISABLE (0<<31)
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#define FDI_TX_DISABLE (0<<31)
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#define FDI_TX_ENABLE (1<<31)
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#define FDI_TX_ENABLE (1<<31)
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#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
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#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
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@ -1319,7 +1319,8 @@ DEBUGSTRING(ironlake_debug_pf_win)
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DEBUGSTRING(ironlake_debug_hdmi)
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DEBUGSTRING(ironlake_debug_hdmi)
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{
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{
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char *enable, pipe, *bpc = NULL, *encoding;
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int pipe;
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char *enable, *bpc = NULL, *encoding;
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char *mode, *audio, *vsync, *hsync, *detect;
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char *mode, *audio, *vsync, *hsync, *detect;
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if (val & PORT_ENABLE)
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if (val & PORT_ENABLE)
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@ -1328,9 +1329,9 @@ DEBUGSTRING(ironlake_debug_hdmi)
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enable = "disabled";
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enable = "disabled";
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if (HAS_CPT)
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if (HAS_CPT)
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pipe = (val & (1<<29)) ? 'B' : 'A';
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pipe = (val & (3<<29)) >> 29;
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else
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else
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pipe = (val & TRANSCODER_B) ? 'B' : 'A';
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pipe = (val & TRANSCODER_B) >> 29;
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switch (val & (7 << 26)) {
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switch (val & (7 << 26)) {
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case COLOR_FORMAT_8bpc:
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case COLOR_FORMAT_8bpc:
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@ -1372,7 +1373,7 @@ DEBUGSTRING(ironlake_debug_hdmi)
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detect = "non-detected";
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detect = "non-detected";
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snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s",
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snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s",
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enable, pipe, bpc, encoding, mode, audio, vsync, hsync, detect);
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enable, pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect);
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}
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}
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DEBUGSTRING(snb_debug_dpll_sel)
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DEBUGSTRING(snb_debug_dpll_sel)
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@ -1627,6 +1628,7 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
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DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
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DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
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DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
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DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl),
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DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
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DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
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DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
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DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
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DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
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DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
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