mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-25 08:46:27 +00:00
Add conditional support to assembler. Add align16 dest support to disasm.
This is working towards round-tripping mesa programs. Still need indirect register addressing and align16 source support.
This commit is contained in:
Keith Packard
Damien Lespiau
parent
d8057c9bcd
commit
2033aea3dd
@ -522,8 +522,9 @@
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#define BRW_CONDITIONAL_L 5
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#define BRW_CONDITIONAL_LE 6
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#define BRW_CONDITIONAL_C 7
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#define BRW_CONDITIONAL_O 8
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#define BRW_CONDITIONAL_U 9
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#define BRW_CONDITIONAL_R 7 /* round increment */
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#define BRW_CONDITIONAL_O 8 /* overflow */
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#define BRW_CONDITIONAL_U 9 /* unordered */
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#define BRW_DEBUG_NONE 0
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#define BRW_DEBUG_BREAKPOINT 1
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@ -1193,7 +1193,7 @@ struct brw_instruction
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GLuint src1_reg_nr:8;
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GLuint src1_abs:1;
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GLuint src1_negate:1;
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GLuint pad:1;
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GLuint src1_address_mode:1;
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GLuint src1_horiz_stride:2;
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GLuint src1_width:3;
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GLuint src1_vert_stride:4;
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@ -1208,7 +1208,7 @@ struct brw_instruction
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GLuint src1_reg_nr:8;
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GLuint src1_abs:1;
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GLuint src1_negate:1;
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GLuint pad0:1;
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GLuint src1_address_mode:1;
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GLuint src1_swz_z:2;
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GLuint src1_swz_w:2;
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GLuint pad1:1;
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@ -1222,7 +1222,7 @@ struct brw_instruction
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GLuint src1_subreg_nr:3;
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GLuint src1_abs:1;
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GLuint src1_negate:1;
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GLuint pad0:1;
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GLuint src1_address_mode:1;
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GLuint src1_horiz_stride:2;
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GLuint src1_width:3;
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GLuint src1_vert_stride:4;
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@ -1238,7 +1238,7 @@ struct brw_instruction
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GLuint src1_subreg_nr:3;
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GLuint src1_abs:1;
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GLuint src1_negate:1;
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GLuint pad0:1;
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GLuint src1_address_mode:1;
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GLuint src1_swz_z:2;
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GLuint src1_swz_w:2;
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GLuint pad1:1;
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@ -88,17 +88,15 @@ struct {
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char *conditional_modifier[16] = {
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[BRW_CONDITIONAL_NONE] = "",
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[BRW_CONDITIONAL_Z] = ".Z",
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[BRW_CONDITIONAL_NZ] = ".NZ",
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[BRW_CONDITIONAL_EQ] = ".EQ",
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[BRW_CONDITIONAL_NEQ] = ".NEQ",
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[BRW_CONDITIONAL_G] = ".G",
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[BRW_CONDITIONAL_GE] = ".GE",
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[BRW_CONDITIONAL_L] = ".L",
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[BRW_CONDITIONAL_LE] = ".LE",
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[BRW_CONDITIONAL_C] = ".C",
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[BRW_CONDITIONAL_O] = ".O",
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[BRW_CONDITIONAL_U] = ".U",
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[BRW_CONDITIONAL_Z] = ".e",
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[BRW_CONDITIONAL_NZ] = ".ne",
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[BRW_CONDITIONAL_G] = ".g",
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[BRW_CONDITIONAL_GE] = ".ge",
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[BRW_CONDITIONAL_L] = ".l",
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[BRW_CONDITIONAL_LE] = ".le",
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[BRW_CONDITIONAL_R] = ".r",
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[BRW_CONDITIONAL_O] = ".o",
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[BRW_CONDITIONAL_U] = ".u",
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};
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char *negate[2] = {
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@ -172,19 +170,17 @@ char *pred_inv[2] = {
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};
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char *pred_ctrl_align16[16] = {
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[0] = "",
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[1] = "sequential",
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[2] = "replication swizzle .x",
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[3] = "replication swizzle .y",
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[4] = "replication swizzle .z",
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[5] = "replication swizzle .w",
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[1] = "",
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[2] = ".x",
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[3] = ".y",
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[4] = ".z",
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[5] = ".w",
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[6] = ".any4h",
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[7] = ".all4h",
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};
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char *pred_ctrl_align1[16] = {
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[0] = "",
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[1] = "sequential",
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[1] = "",
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[2] = ".anyv",
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[3] = ".allv",
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[4] = ".any2h",
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@ -252,6 +248,25 @@ char *reg_file[4] = {
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[3] = "imm",
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};
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char *writemask[16] = {
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[0x0] = ".",
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[0x1] = ".x",
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[0x2] = ".y",
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[0x3] = ".xy",
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[0x4] = ".z",
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[0x5] = ".xz",
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[0x6] = ".yz",
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[0x7] = ".xyz",
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[0x8] = ".w",
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[0x9] = ".xw",
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[0xa] = ".yw",
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[0xb] = ".xyw",
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[0xc] = ".zw",
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[0xd] = ".xzw",
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[0xe] = ".yzw",
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[0xf] = "",
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};
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char *end_of_thread[2] = {
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[0] = "",
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[1] = "EOT"
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@ -361,8 +376,9 @@ static int newline (FILE *f)
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static int pad (FILE *f, int c)
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{
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while (column < c)
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do
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string (f, " ");
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while (column < c);
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return 0;
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}
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@ -394,56 +410,95 @@ static int print_opcode (FILE *file, int id)
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return 0;
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}
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static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
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{
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int err = 0;
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if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
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switch (_reg_nr & 0xf0) {
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case BRW_ARF_NULL:
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string (file, "null");
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return -1;
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case BRW_ARF_ADDRESS:
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format (file, "a%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_ACCUMULATOR:
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format (file, "acc%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK:
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format (file, "mask%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK_STACK:
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format (file, "msd%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_STATE:
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format (file, "sr%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_CONTROL:
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format (file, "cr%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_NOTIFICATION_COUNT:
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format (file, "n%d", _reg_nr & 0x0f);
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break;
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case BRW_ARF_IP:
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string (file, "ip");
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return -1;
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break;
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default:
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format (file, "ARF%d", _reg_nr);
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break;
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}
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} else {
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err |= control (file, "src reg file", reg_file, _reg_file, NULL);
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format (file, "%d", _reg_nr);
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}
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return err;
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}
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static int dest (FILE *file, struct brw_instruction *inst)
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{
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int err = 0;
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if (inst->bits1.da1.dest_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
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switch (inst->bits1.da1.dest_reg_nr & 0xf0) {
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case BRW_ARF_NULL:
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string (file, "null");
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if (inst->header.access_mode == BRW_ALIGN_1)
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{
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if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
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{
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err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
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if (err == -1)
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return 0;
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case BRW_ARF_ADDRESS:
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format (file, "a%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_ACCUMULATOR:
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format (file, "acc%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK:
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format (file, "mask%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_MASK_STACK:
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format (file, "msd%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_STATE:
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format (file, "sr%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_CONTROL:
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format (file, "cr%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_NOTIFICATION_COUNT:
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format (file, "n%d", inst->bits1.da1.dest_reg_nr & 0x0f);
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break;
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case BRW_ARF_IP:
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string (file, "ip");
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break;
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default:
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format (file, "ARF%d", inst->bits1.da1.dest_reg_nr);
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break;
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}
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} else {
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err |= control (file, "dest reg file", reg_file, inst->bits1.da1.dest_reg_file, NULL);
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format (file, "%d", inst->bits1.da1.dest_reg_nr);
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}
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if (inst->bits1.da1.dest_subreg_nr)
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format (file, ".%d", inst->bits1.da1.dest_subreg_nr);
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format (file, "<%d>", inst->bits1.da1.dest_horiz_stride);
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err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
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}
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else
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{
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err = 1;
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string (file, "Indirect align1 address mode not supported");
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}
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}
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else
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{
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if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
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{
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err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
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if (err == -1)
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return 0;
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if (inst->bits1.da16.dest_subreg_nr)
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format (file, ".%d", inst->bits1.da16.dest_subreg_nr);
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err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
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string (file, "<1>");
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}
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else
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{
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err = 1;
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string (file, "Indirect align16 address mode not supported");
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}
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}
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return 0;
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}
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static int src (FILE *file, GLuint type, GLuint _reg_file,
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static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
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GLuint _vert_stride, GLuint _width, GLuint _horiz_stride,
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GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate)
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{
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@ -451,8 +506,9 @@ static int src (FILE *file, GLuint type, GLuint _reg_file,
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err |= control (file, "negate", negate, _negate, NULL);
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err |= control (file, "abs", _abs, __abs, NULL);
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err |= control (file, "src reg file", reg_file, _reg_file, NULL);
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format (file, "%d", reg_num);
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err |= reg (file, _reg_file, reg_num);
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if (err == -1)
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return 0;
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if (sub_reg_num)
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format (file, ".%d", sub_reg_num);
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string (file, "<");
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@ -500,8 +556,11 @@ static int src0 (FILE *file, struct brw_instruction *inst)
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if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
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return imm (file, inst->bits1.da1.src0_reg_type,
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inst);
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else
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return src (file,
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else if (inst->header.access_mode == BRW_ALIGN_1)
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{
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if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
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{
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return src_da1 (file,
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inst->bits1.da1.src0_reg_type,
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inst->bits1.da1.src0_reg_file,
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inst->bits2.da1.src0_vert_stride,
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@ -512,14 +571,37 @@ static int src0 (FILE *file, struct brw_instruction *inst)
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inst->bits2.da1.src0_abs,
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inst->bits2.da1.src0_negate);
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}
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else
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{
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string (file, "Indirect align1 address mode not supported");
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return 1;
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}
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}
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else
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{
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if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
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{
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string (file, "Indirect align16 address mode not supported");
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return 1;
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}
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else
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{
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string (file, "Indirect align16 address mode not supported");
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return 1;
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}
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}
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}
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static int src1 (FILE *file, struct brw_instruction *inst)
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{
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if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
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return imm (file, inst->bits1.da1.src1_reg_type,
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inst);
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else
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return src (file,
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else if (inst->header.access_mode == BRW_ALIGN_1)
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{
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if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
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{
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return src_da1 (file,
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inst->bits1.da1.src1_reg_type,
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inst->bits1.da1.src1_reg_file,
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inst->bits3.da1.src1_vert_stride,
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@ -530,28 +612,55 @@ static int src1 (FILE *file, struct brw_instruction *inst)
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inst->bits3.da1.src1_abs,
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inst->bits3.da1.src1_negate);
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}
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else
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{
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string (file, "Indirect align1 address mode not supported");
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return 1;
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}
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}
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else
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{
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if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
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{
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string (file, "Indirect align16 address mode not supported");
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return 1;
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}
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else
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{
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string (file, "Indirect align16 address mode not supported");
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return 1;
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}
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}
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}
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int disasm (FILE *file, struct brw_instruction *inst)
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{
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int err = 0;
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int space = 0;
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if (inst->header.predicate_control || inst->header.predicate_inverse) {
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if (inst->header.predicate_control) {
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string (file, "(");
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space = 0;
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err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, &space);
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err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
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string (file, "f0");
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if (inst->bits2.da1.flag_reg_nr)
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format (file, ".%d", inst->bits2.da1.flag_reg_nr);
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if (inst->header.access_mode == BRW_ALIGN_1)
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err |= control (file, "predicate control align1", pred_ctrl_align1,
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inst->header.predicate_control, &space);
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inst->header.predicate_control, NULL);
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else
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err |= control (file, "predicate control align16", pred_ctrl_align16,
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inst->header.predicate_control, &space);
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inst->header.predicate_control, NULL);
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string (file, ") ");
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}
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err |= print_opcode (file, inst->header.opcode);
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err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
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err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
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if (inst->header.opcode != BRW_OPCODE_SEND)
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err |= control (file, "conditional modifier", conditional_modifier,
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inst->header.destreg__conditionalmod, NULL);
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if (inst->header.opcode != BRW_OPCODE_NOP) {
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string (file, "(");
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err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
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@ -560,9 +669,6 @@ int disasm (FILE *file, struct brw_instruction *inst)
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if (inst->header.opcode == BRW_OPCODE_SEND)
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format (file, " %d", inst->header.destreg__conditionalmod);
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else
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err |= control (file, "conditional modifier", conditional_modifier,
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inst->header.destreg__conditionalmod, NULL);
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if (opcode[inst->header.opcode].ndst > 0) {
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pad (file, 16);
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@ -86,7 +86,9 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
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%token ALIGN1 ALIGN16 SECHALF COMPR SWITCH ATOMIC NODDCHK NODDCLR
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%token MASK_DISABLE BREAKPOINT EOT
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%token ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
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%token SEQ ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H ANYV ALLV
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%token <integer> ZERO EQUAL NOT_ZERO NOT_EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL
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%token <integer> ROUND_INCREMENT OVERFLOW UNORDERED
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%token <integer> GENREG MSGREG ADDRESSREG ACCREG FLAGREG
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%token <integer> MASKREG AMASK IMASK LMASK CMASK
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%token <integer> MASKSTACKREG LMS IMS MASKSTACKDEPTHREG IMSD LMSD
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@ -1331,11 +1333,13 @@ predstate: /* empty */ { $$ = 0; }
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| MINUS { $$ = 1; }
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;
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||||
|
||||
predctrl: /* empty */ { $$ = BRW_PREDICATE_NONE; }
|
||||
predctrl: /* empty */ { $$ = BRW_PREDICATE_NORMAL; }
|
||||
| DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
|
||||
| DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
|
||||
| DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
|
||||
| DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
|
||||
| ANYV { $$ = BRW_PREDICATE_ALIGN1_ANYV; }
|
||||
| ALLV { $$ = BRW_PREDICATE_ALIGN1_ALLV; }
|
||||
| ANY2H { $$ = BRW_PREDICATE_ALIGN1_ANY2H; }
|
||||
| ALL2H { $$ = BRW_PREDICATE_ALIGN1_ALL2H; }
|
||||
| ANY4H { $$ = BRW_PREDICATE_ALIGN1_ANY4H; }
|
||||
@ -1372,7 +1376,18 @@ saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
|
||||
| DOT SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
|
||||
;
|
||||
|
||||
conditionalmodifier: { $$ = 0; }
|
||||
conditionalmodifier: /* empty */ { $$ = BRW_CONDITIONAL_NONE; }
|
||||
| ZERO
|
||||
| EQUAL
|
||||
| NOT_ZERO
|
||||
| NOT_EQUAL
|
||||
| GREATER
|
||||
| GREATER_EQUAL
|
||||
| LESS
|
||||
| LESS_EQUAL
|
||||
| ROUND_INCREMENT
|
||||
| OVERFLOW
|
||||
| UNORDERED
|
||||
;
|
||||
|
||||
/* 1.4.13: Instruction options */
|
||||
@ -1632,7 +1647,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
|
||||
src->reg_nr = reg->reg_nr;
|
||||
src->vert_stride = 0;
|
||||
src->width = 0;
|
||||
src->horiz_stride = 1;
|
||||
src->horiz_stride = 0;
|
||||
src->negate = 0;
|
||||
src->abs = 0;
|
||||
src->swizzle_set = 0;
|
||||
|
||||
@ -284,14 +284,28 @@ extern char *input_filename;
|
||||
"scalar" { return SCALAR; }
|
||||
|
||||
/* predicate control */
|
||||
"any2h" { return ANY2H; }
|
||||
"all2h" { return ALL2H; }
|
||||
"any4h" { return ANY4H; }
|
||||
"all4h" { return ALL4H; }
|
||||
"any8h" { return ANY8H; }
|
||||
"all8h" { return ALL8H; }
|
||||
"any16h" { return ANY16H; }
|
||||
"all16h" { return ALL16H; }
|
||||
".anyv" { return ANYV; }
|
||||
".allv" { return ALLV; }
|
||||
".any2h" { return ANY2H; }
|
||||
".all2h" { return ALL2H; }
|
||||
".any4h" { return ANY4H; }
|
||||
".all4h" { return ALL4H; }
|
||||
".any8h" { return ANY8H; }
|
||||
".all8h" { return ALL8H; }
|
||||
".any16h" { return ANY16H; }
|
||||
".all16h" { return ALL16H; }
|
||||
|
||||
".z" { yylval.integer = BRW_CONDITIONAL_Z; return ZERO; }
|
||||
".e" { yylval.integer = BRW_CONDITIONAL_Z; return EQUAL; }
|
||||
".nz" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_ZERO; }
|
||||
".ne" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_EQUAL; }
|
||||
".g" { yylval.integer = BRW_CONDITIONAL_G; return GREATER; }
|
||||
".ge" { yylval.integer = BRW_CONDITIONAL_GE; return GREATER_EQUAL; }
|
||||
".l" { yylval.integer = BRW_CONDITIONAL_L; return LESS; }
|
||||
".le" { yylval.integer = BRW_CONDITIONAL_LE; return LESS_EQUAL; }
|
||||
".r" { yylval.integer = BRW_CONDITIONAL_R; return ROUND_INCREMENT; }
|
||||
".o" { yylval.integer = BRW_CONDITIONAL_O; return OVERFLOW; }
|
||||
".u" { yylval.integer = BRW_CONDITIONAL_U; return UNORDERED; }
|
||||
|
||||
/* channel selectors */
|
||||
"x" {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user