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https://github.com/tiagovignatti/intel-gpu-tools.git
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igt/gem_busy: Discard the indirect batchbuffers
The stack of batchbuffers is myth. In general there are only 2 levels of stack for HEAD (ringbuffer, batchbuffer) and chaining up the batch buffer just updates the lowest level of the stack. A BATCH_BUFFER_END at any depth then returns to the ring. So be creative and modify the batch buffer on the fly... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
71f4153287
commit
1e9a3acfd4
152
tests/gem_busy.c
152
tests/gem_busy.c
@ -222,98 +222,49 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
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gem_close(fd, handle[i]);
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}
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static void create_indirect(int fd,
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struct drm_i915_gem_exec_object2 *obj,
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struct drm_i915_gem_exec_object2 *target)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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const int nreloc = 128;
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struct drm_i915_gem_relocation_entry *reloc;
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uint32_t *batch;
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int i, count;
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reloc = calloc(nreloc, sizeof(*reloc));
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obj->handle = gem_create(fd, 4096);
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obj->relocs_ptr = (uintptr_t)reloc;
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obj->relocation_count = nreloc;
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batch = gem_mmap__cpu(fd, obj->handle, 0, 4096, PROT_WRITE);
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gem_set_domain(fd, obj->handle,
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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i = 0;
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for (count = 0; count < nreloc; count++) {
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reloc[count].target_handle = target->handle;
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reloc[count].presumed_offset = target->offset;
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reloc[count].offset = sizeof(uint32_t) * (i + 1);
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reloc[count].delta = 0;
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reloc[count].read_domains = I915_GEM_DOMAIN_COMMAND;
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reloc[count].write_domain = 0;
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batch[i] = MI_BATCH_BUFFER_START;
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if (gen >= 8) {
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batch[i] |= 1 << 8 | 1;
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batch[++i] = target->offset;
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batch[++i] = target->offset >> 32;
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} else if (gen >= 6) {
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batch[i] |= 1 << 8;
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batch[++i] = target->offset;
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} else {
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batch[i] |= 2 << 6;
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batch[++i] = target->offset;
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if (gen < 4) {
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batch[i] |= 1;
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reloc[count].delta = 1;
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}
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}
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i++;
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}
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batch[++i] = MI_BATCH_BUFFER_END;
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igt_assert(i < 4096/sizeof(*batch));
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munmap(batch, 4096);
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}
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static void store(int fd, unsigned ring, uint32_t flags)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_exec_object2 obj[16];
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struct drm_i915_gem_relocation_entry store[1024];
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struct drm_i915_gem_exec_object2 obj[2];
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#define SCRATCH 0
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#define BATCH 1
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struct drm_i915_gem_relocation_entry store[1024+1];
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struct drm_i915_gem_execbuffer2 execbuf;
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unsigned size = ALIGN(ARRAY_SIZE(store)*16 + 4, 4096);
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uint32_t read[2], write[2];
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struct timespec tv;
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uint32_t *batch;
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int i, count, idx;
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uint32_t *batch, *bbe;
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int i, count;
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gem_require_ring(fd, ring | flags);
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igt_skip_on_f(gen == 6 && (ring & ~(3<<13)) == I915_EXEC_BSD,
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"MI_STORE_DATA broken on gen6 bsd\n");
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gem_require_mmap_wc(fd);
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gem_quiescent_gpu(fd);
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)obj;
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execbuf.buffer_count = 2;
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execbuf.flags = ring | flags | LOCAL_EXEC_NO_RELOC;
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execbuf.flags = ring | flags;
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if (gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[0].flags = EXEC_OBJECT_WRITE;
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obj[1].handle = gem_create(fd, size);
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obj[SCRATCH].handle = gem_create(fd, 4096);
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obj[BATCH].handle = gem_create(fd, size);
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obj[BATCH].relocs_ptr = (uintptr_t)store;
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obj[BATCH].relocation_count = ARRAY_SIZE(store);
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memset(store, 0, sizeof(store));
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obj[1].relocs_ptr = (uintptr_t)store;
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obj[1].relocation_count = ARRAY_SIZE(store);
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batch = gem_mmap__cpu(fd, obj[1].handle, 0, size, PROT_WRITE);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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batch = gem_mmap__wc(fd, obj[BATCH].handle, 0, size, PROT_WRITE);
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gem_set_domain(fd, obj[BATCH].handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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i = 0;
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for (count = 0; count < ARRAY_SIZE(store); count++) {
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store[count].target_handle = obj[0].handle;
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for (count = 0; count < 1024; count++) {
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store[count].target_handle = obj[SCRATCH].handle;
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store[count].presumed_offset = -1;
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store[count].offset = sizeof(uint32_t) * (i + 1);
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store[count].delta = sizeof(uint32_t) * count;
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@ -334,50 +285,61 @@ static void store(int fd, unsigned ring, uint32_t flags)
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batch[++i] = count;
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i++;
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}
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batch[++i] = MI_BATCH_BUFFER_END;
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bbe = &batch[i];
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store[count].target_handle = obj[BATCH].handle; /* recurse */
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store[count].presumed_offset = 0;
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store[count].offset = sizeof(uint32_t) * (i + 1);
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store[count].delta = 0;
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store[count].read_domains = I915_GEM_DOMAIN_COMMAND;
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store[count].write_domain = 0;
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batch[i] = MI_BATCH_BUFFER_START;
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if (gen >= 8) {
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batch[i] |= 1 << 8 | 1;
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batch[++i] = 0;
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batch[++i] = 0;
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} else if (gen >= 6) {
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batch[i] |= 1 << 8;
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batch[++i] = 0;
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} else {
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batch[i] |= 2 << 6;
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batch[++i] = 0;
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if (gen < 4) {
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batch[i] |= 1;
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store[count].delta = 1;
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}
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}
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i++;
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igt_assert(i < size/sizeof(*batch));
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munmap(batch, size);
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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do {
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idx = execbuf.buffer_count++;
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igt_require(idx < ARRAY_SIZE(obj));
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create_indirect(fd, &obj[idx], &obj[idx-1]);
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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__gem_busy(fd, obj[SCRATCH].handle, &read[SCRATCH], &write[SCRATCH]);
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__gem_busy(fd, obj[BATCH].handle, &read[BATCH], &write[BATCH]);
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gem_execbuf(fd, &execbuf);
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__gem_busy(fd, obj[0].handle, &read[0], &write[0]);
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__gem_busy(fd, obj[idx].handle, &read[1], &write[1]);
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igt_debug("After %d cycles: read[0]=%x read[1]=%x\n",
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idx-1, read[0], read[1]);
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} while (read[0] == 0 || read[1] == 0);
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*bbe = MI_BATCH_BUFFER_END;
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__sync_synchronize();
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igt_assert_eq(write[0], ring);
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igt_assert_eq_u32(read[0], 1 << ring);
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igt_assert_eq(write[SCRATCH], ring);
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igt_assert_eq_u32(read[SCRATCH], 1 << ring);
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igt_assert_eq(write[1], 0);
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igt_assert_eq_u32(read[1], 1 << ring);
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igt_assert_eq(write[BATCH], 0);
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igt_assert_eq_u32(read[BATCH], 1 << ring);
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/* Calling busy in a loop should be enough to flush the rendering */
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memset(&tv, 0, sizeof(tv));
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while (gem_busy(fd, obj[idx].handle))
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while (gem_busy(fd, obj[BATCH].handle))
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igt_assert(igt_seconds_elapsed(&tv) < 10);
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igt_assert(!gem_busy(fd, obj[0].handle));
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igt_assert(!gem_busy(fd, obj[SCRATCH].handle));
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batch = gem_mmap__gtt(fd, obj[0].handle, 4096, PROT_READ);
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munmap(batch, size);
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batch = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ);
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for (i = 0; i < 1024; i++)
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igt_assert_eq_u32(batch[i], i);
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munmap(batch, 4096);
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for (i = 0; i <= idx; i++) {
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struct drm_i915_gem_relocation_entry *r;
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r = (struct drm_i915_gem_relocation_entry *)
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(uintptr_t)obj[i].relocs_ptr;
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if (r != store)
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free(r);
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gem_close(fd, obj[i].handle);
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}
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gem_close(fd, obj[BATCH].handle);
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gem_close(fd, obj[SCRATCH].handle);
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}
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static bool has_semaphores(int fd)
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