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batch: Specify number of relocations to accommodate

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Since relocations are variable size, depending upon generation, it is
easier to handle the resizing of the batch request inside the
BEGIN_BATCH macro. This still leaves us with having to resize commands
in a few places - which still need adaption for gen8+.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
2014-08-30 11:44:51 +01:00
parent 255bade1ea
commit 10552b5ca6
45 changed files with 152 additions and 180 deletions
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tests/gem_pipe_control_store_loop.c
+8 -8
View File
@@ -77,7 +77,7 @@ store_pipe_control_loop(bool preuse_buffer)
igt_assert(target_bo);
if (preuse_buffer) {
COLOR_BLIT_COPY_BATCH_START(devid, 0);
COLOR_BLIT_COPY_BATCH_START(0);
OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
OUT_BATCH(0);
OUT_BATCH(1 << 16 | 1);
@@ -99,8 +99,8 @@ store_pipe_control_loop(bool preuse_buffer)
/* gem_storedw_batches_loop.c is a bit overenthusiastic with
* creating new batchbuffers - with buffer reuse disabled, the
* support code will do that for us. */
if (intel_gen(devid) >= 8) {
BEGIN_BATCH(5);
if (batch->gen >= 8) {
BEGIN_BATCH(4, 1);
OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
OUT_RELOC_FENCED(target_bo,
@@ -109,10 +109,10 @@ store_pipe_control_loop(bool preuse_buffer)
OUT_BATCH(val); /* write data */
ADVANCE_BATCH();
} else if (intel_gen(devid) >= 6) {
} else if (batch->gen >= 6) {
/* work-around hw issue, see intel_emit_post_sync_nonzero_flush
* in mesa sources. */
BEGIN_BATCH(4);
BEGIN_BATCH(4, 1);
OUT_BATCH(GFX_OP_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
@@ -120,7 +120,7 @@ store_pipe_control_loop(bool preuse_buffer)
OUT_BATCH(0); /* write data */
ADVANCE_BATCH();
BEGIN_BATCH(4);
BEGIN_BATCH(4, 1);
OUT_BATCH(GFX_OP_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
OUT_RELOC(target_bo,
@@ -128,8 +128,8 @@ store_pipe_control_loop(bool preuse_buffer)
PIPE_CONTROL_GLOBAL_GTT);
OUT_BATCH(val); /* write data */
ADVANCE_BATCH();
} else if (intel_gen(devid) >= 4) {
BEGIN_BATCH(4);
} else if (batch->gen >= 4) {
BEGIN_BATCH(4, 1);
OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
PIPE_CONTROL_TC_FLUSH |
PIPE_CONTROL_WRITE_IMMEDIATE | 2);