mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-09 00:46:17 +00:00
assembler: Rename gen5 DP pixel_scoreboard_clear to last_render_target
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
parent
fe0bd3776e
commit
0fde3ddccc
@ -1368,7 +1368,7 @@ struct brw_instruction
|
||||
struct {
|
||||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:3;
|
||||
GLuint pixel_scoreboard_clear:1;
|
||||
GLuint last_render_target:1;
|
||||
GLuint msg_type:3;
|
||||
GLuint send_commit_msg:1;
|
||||
GLuint response_length:4;
|
||||
@ -1489,7 +1489,7 @@ struct brw_instruction
|
||||
struct {
|
||||
GLuint binding_table_index:8;
|
||||
GLuint msg_control:3;
|
||||
GLuint pixel_scoreboard_clear:1;
|
||||
GLuint last_render_target:1;
|
||||
GLuint msg_type:3;
|
||||
GLuint send_commit_msg:1;
|
||||
GLuint pad0:3;
|
||||
|
@ -854,7 +854,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
|
||||
case BRW_MESSAGE_TARGET_DATAPORT_WRITE:
|
||||
format (file, " (%d, %d, %d, %d)",
|
||||
inst->bits3.dp_write.binding_table_index,
|
||||
(inst->bits3.dp_write.pixel_scoreboard_clear << 3) |
|
||||
(inst->bits3.dp_write.last_render_target << 3) |
|
||||
inst->bits3.dp_write.msg_control,
|
||||
inst->bits3.dp_write.msg_type,
|
||||
inst->bits3.dp_write.send_commit_msg);
|
||||
|
@ -1307,7 +1307,7 @@ msgtarget: NULL_TOKEN
|
||||
BRW_MESSAGE_TARGET_DATAPORT_WRITE;
|
||||
$$.bits3.generic_gen5.header_present = 1;
|
||||
$$.bits3.dp_write_gen5.binding_table_index = $3;
|
||||
$$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write_gen5.last_render_target = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write_gen5.msg_control = $5 & 0x7;
|
||||
$$.bits3.dp_write_gen5.msg_type = $7;
|
||||
$$.bits3.dp_write_gen5.send_commit_msg = $9;
|
||||
@ -1316,10 +1316,10 @@ msgtarget: NULL_TOKEN
|
||||
BRW_MESSAGE_TARGET_DATAPORT_WRITE;
|
||||
$$.bits3.dp_write.binding_table_index = $3;
|
||||
/* The msg control field of brw_struct.h is split into
|
||||
* msg control and pixel_scoreboard_clear, even though
|
||||
* pixel_scoreboard_clear isn't common to all write messages.
|
||||
* msg control and last_render_target, even though
|
||||
* last_render_target isn't common to all write messages.
|
||||
*/
|
||||
$$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write.last_render_target = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write.msg_control = $5 & 0x7;
|
||||
$$.bits3.dp_write.msg_type = $7;
|
||||
$$.bits3.dp_write.send_commit_msg = $9;
|
||||
@ -1348,7 +1348,7 @@ msgtarget: NULL_TOKEN
|
||||
BRW_MESSAGE_TARGET_DATAPORT_WRITE;
|
||||
$$.bits3.generic_gen5.header_present = ($11 != 0);
|
||||
$$.bits3.dp_write_gen5.binding_table_index = $3;
|
||||
$$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write_gen5.last_render_target = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write_gen5.msg_control = $5 & 0x7;
|
||||
$$.bits3.dp_write_gen5.msg_type = $7;
|
||||
$$.bits3.dp_write_gen5.send_commit_msg = $9;
|
||||
@ -1357,10 +1357,10 @@ msgtarget: NULL_TOKEN
|
||||
BRW_MESSAGE_TARGET_DATAPORT_WRITE;
|
||||
$$.bits3.dp_write.binding_table_index = $3;
|
||||
/* The msg control field of brw_struct.h is split into
|
||||
* msg control and pixel_scoreboard_clear, even though
|
||||
* pixel_scoreboard_clear isn't common to all write messages.
|
||||
* msg control and last_render_target, even though
|
||||
* last_render_target isn't common to all write messages.
|
||||
*/
|
||||
$$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write.last_render_target = ($5 & 0x8) >> 3;
|
||||
$$.bits3.dp_write.msg_control = $5 & 0x7;
|
||||
$$.bits3.dp_write.msg_type = $7;
|
||||
$$.bits3.dp_write.send_commit_msg = $9;
|
||||
|
Loading…
x
Reference in New Issue
Block a user