From 0f906083f2a2248355f799948188aa8c010585d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 28 May 2014 18:26:39 +0300 Subject: [PATCH] lib/intel_iosf: add second phy support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak --- lib/intel_iosf.c | 10 ++++++++-- lib/intel_reg.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c index ffa2fcaa..ca206389 100644 --- a/lib/intel_iosf.c +++ b/lib/intel_iosf.c @@ -137,7 +137,10 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy) { uint32_t val; - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val); + if (phy == 0) + vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val); + else + vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val); return val; } @@ -151,7 +154,10 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy) */ void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy) { - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); + if (phy == 0) + vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val); + else + vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val); } uint32_t intel_flisdsi_reg_read(uint32_t reg) diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 55206247..84e05e40 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -3568,6 +3568,7 @@ typedef enum { #define IOSF_PORT_PUNIT 0x4 #define IOSF_PORT_NC 0x11 #define IOSF_PORT_DPIO 0x12 +#define IOSF_PORT_DPIO_2 0x1a #define IOSF_PORT_GPIO_NC 0x13 #define IOSF_PORT_CCK 0x14 #define IOSF_PORT_CCU 0xA9