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Code Issues Releases Wiki Activity

fixup VLV reg offsets, add a few more

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This commit is contained in:
Jesse Barnes 2013-04-16 13:16:31 -07:00
parent 25339595a7
commit 0b7da0afb1
2 changed files with 32 additions and 5 deletions
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23
tools/quick_dump/vlv_display.txt
View File

@ -1,7 +1,7 @@
('DPLLA_CRTL', '0x186014', '') ('DPLLA_CTRL', '0x186014', '')
('DPLBA_CRTL', '0x186018', '') ('DPLLB_CTRL', '0x186018', '')
('DPLLAMD_CRTL', '0x18601c', '') ('DPLLAMD_CRTL', '0x18601c', '')
('DPLBAMD_CRTL', '0x186020', '') ('DPLLBMD_CRTL', '0x186020', '')
('RAWCLK_FREQ', '0x186024', '') ('RAWCLK_FREQ', '0x186024', '')
('D_STAT', '0x186104', '') ('D_STAT', '0x186104', '')
('DISPCLK_GATE_D', '0x186200', '') ('DISPCLK_GATE_D', '0x186200', '')
@ -48,8 +48,7 @@
('HDMIC', '0x1e1160', '') ('HDMIC', '0x1e1160', '')
('PORT_HOTPLUG_CTRL', '0x1e1164', '') ('PORT_HOTPLUG_CTRL', '0x1e1164', '')
('DP_B', '0x1e4100', '') ('DP_B', '0x1e4100', '')
('PIPEACONF', '0x001f0008', '') ('DP_C', '0x1e4200', '')
('PIPEASTAT', '0x001f0024', '')
('DPINVGTT', '0x001f002c', '') ('DPINVGTT', '0x001f002c', '')
('DSPARB', '0x001f0030', '') ('DSPARB', '0x001f0030', '')
('FW1', '0x001f0034', '') ('FW1', '0x001f0034', '')
@ -64,6 +63,8 @@
('DSPARB2', '0x001f0060', '') ('DSPARB2', '0x001f0060', '')
('DSPHOWM', '0x001f0064', '') ('DSPHOWM', '0x001f0064', '')
('DSPHOWM1', '0x001f0068', '') ('DSPHOWM1', '0x001f0068', '')
('PIPEACONF', '0x001f0008', '')
('PIPEASTAT', '0x001f0024', '')
('DSPACNTR', '0x001f0180', '') ('DSPACNTR', '0x001f0180', '')
('DSPABASE', '0x001f0184', '') ('DSPABASE', '0x001f0184', '')
('DSPASTRIDE', '0x001f0188', '') ('DSPASTRIDE', '0x001f0188', '')
@ -82,3 +83,15 @@
('DSPCSTRIDE', '0x001f2188', '') ('DSPCSTRIDE', '0x001f2188', '')
('DSPCSURF', '0x001f219c', '') ('DSPCSURF', '0x001f219c', '')
('DSPCTILEOFF', '0x001f21a4', '') ('DSPCTILEOFF', '0x001f21a4', '')
('PIPEA_PP_STATUS', '0x001e1200', '')
('PIPEA_PP_CONTROL', '0x001e1204', '')
('PIPEA_PP_ON_DELAYS', '0x001e1208', '')
('PIPEA_PP_OFF_DELAYS', '0x001e120c', '')
('PIPEA_PP_DIVISOR', '0x001e1210', '')
('PIPEB_PP_STATUS', '0x001e1300', '')
('PIPEB_PP_CONTROL', '0x001e1304', '')
('PIPEB_PP_ON_DELAYS', '0x001e1308', '')
('PIPEB_PP_OFF_DELAYS', '0x001e130c', '')
('PIPEB_PP_DIVISOR', '0x001e1310', '')
('BLC_PWM_CTL2', '0x1e1250', '')
('BLC_PWM_CTL', '0x1e1254', '')

14
tools/quick_dump/vlv_power.txt Normal file
View File

@ -0,0 +1,14 @@
('GTLC wake control', '0x130090', '')
('GTLC power well status', '0x130094', '')
('Render forcewake req', '0x1300b0', '')
('Render forcewake ack', '0x1300b4', '')
('Counter control', '0x138104', '')
('RC6 counter', '0x138108', '')
('RC6_SLEEP', 0xa0b0, '')
('RC6_WAKE_LIMIT', 0xa09c, '')
('RC_EI', 0xa0a8, '')
('RC_IDLE_HYSTERESIS', 0xa0ac, '')
('RC6_THRESHOLD', 0xa0b8, '')
('RC6p_THRESHOLD', 0xa0bc, '')
('RC6pp_THRESHOLD', 0xa0c0, '')
('RC_CONTROL', 0xa090, '')