mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2026-08-21 21:32:56 +00:00
fixup VLV reg offsets, add a few more
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@@ -1,7 +1,7 @@
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('DPLLA_CRTL', '0x186014', '')
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('DPLBA_CRTL', '0x186018', '')
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('DPLLA_CTRL', '0x186014', '')
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('DPLLB_CTRL', '0x186018', '')
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('DPLLAMD_CRTL', '0x18601c', '')
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('DPLBAMD_CRTL', '0x186020', '')
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('DPLLBMD_CRTL', '0x186020', '')
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('RAWCLK_FREQ', '0x186024', '')
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('D_STAT', '0x186104', '')
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('DISPCLK_GATE_D', '0x186200', '')
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@@ -48,8 +48,7 @@
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('HDMIC', '0x1e1160', '')
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('PORT_HOTPLUG_CTRL', '0x1e1164', '')
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('DP_B', '0x1e4100', '')
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('PIPEACONF', '0x001f0008', '')
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('PIPEASTAT', '0x001f0024', '')
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('DP_C', '0x1e4200', '')
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('DPINVGTT', '0x001f002c', '')
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('DSPARB', '0x001f0030', '')
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('FW1', '0x001f0034', '')
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@@ -64,6 +63,8 @@
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('DSPARB2', '0x001f0060', '')
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('DSPHOWM', '0x001f0064', '')
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('DSPHOWM1', '0x001f0068', '')
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('PIPEACONF', '0x001f0008', '')
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('PIPEASTAT', '0x001f0024', '')
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('DSPACNTR', '0x001f0180', '')
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('DSPABASE', '0x001f0184', '')
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('DSPASTRIDE', '0x001f0188', '')
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@@ -82,3 +83,15 @@
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('DSPCSTRIDE', '0x001f2188', '')
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('DSPCSURF', '0x001f219c', '')
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('DSPCTILEOFF', '0x001f21a4', '')
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('PIPEA_PP_STATUS', '0x001e1200', '')
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('PIPEA_PP_CONTROL', '0x001e1204', '')
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('PIPEA_PP_ON_DELAYS', '0x001e1208', '')
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('PIPEA_PP_OFF_DELAYS', '0x001e120c', '')
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('PIPEA_PP_DIVISOR', '0x001e1210', '')
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('PIPEB_PP_STATUS', '0x001e1300', '')
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('PIPEB_PP_CONTROL', '0x001e1304', '')
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('PIPEB_PP_ON_DELAYS', '0x001e1308', '')
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('PIPEB_PP_OFF_DELAYS', '0x001e130c', '')
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('PIPEB_PP_DIVISOR', '0x001e1310', '')
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('BLC_PWM_CTL2', '0x1e1250', '')
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('BLC_PWM_CTL', '0x1e1254', '')
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