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Update dpio read/write to take in extra PHY parameter.

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The extra parameter is for future platform.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Chon Ming Lee 2013-12-04 20:44:33 +08:00 committed by Ville Syrjälä
parent f5643c4a27
commit 0b67c0c421
7 changed files with 26 additions and 13 deletions
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19
lib/intel_dpio.c
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@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t val)
*ptr = val; *ptr = val;
} }
static int get_dpio_port(int phy) {
struct pci_device *dev = intel_get_pci_device();
int dpio_port;
if (IS_VALLEYVIEW(dev->device_id))
dpio_port = DPIO_PORTID;
return dpio_port;
}
/* /*
* In SoCs like Valleyview some of the PLL & Lane control registers * In SoCs like Valleyview some of the PLL & Lane control registers
* can be accessed only through IO side band fabric called DPIO * can be accessed only through IO side band fabric called DPIO
*/ */
uint32_t uint32_t
intel_dpio_reg_read(uint32_t reg) intel_dpio_reg_read(uint32_t reg, int phy)
{ {
/* Check whether the side band fabric is ready to accept commands */ /* Check whether the side band fabric is ready to accept commands */
do { do {
@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg)
intel_display_reg_write(DPIO_REG, reg); intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID | intel_display_reg_write(DPIO_PKT, DPIO_RID |
DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE); DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
do { do {
usleep(1); usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY); } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg)
* can be accessed only through IO side band fabric called DPIO * can be accessed only through IO side band fabric called DPIO
*/ */
void void
intel_dpio_reg_write(uint32_t reg, uint32_t val) intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{ {
/* Check whether the side band fabric is ready to accept commands */ /* Check whether the side band fabric is ready to accept commands */
do { do {
@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val)
intel_display_reg_write(DPIO_DATA, val); intel_display_reg_write(DPIO_DATA, val);
intel_display_reg_write(DPIO_REG, reg); intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID | intel_display_reg_write(DPIO_PKT, DPIO_RID |
DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE); DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
do { do {
usleep(1); usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY); } while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);

4
lib/intel_gpu_tools.h
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@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val);
int intel_register_access_needs_fakewake(void); int intel_register_access_needs_fakewake(void);
/* Following functions are relevant only for SoCs like Valleyview */ /* Following functions are relevant only for SoCs like Valleyview */
uint32_t intel_dpio_reg_read(uint32_t reg); uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
void intel_dpio_reg_write(uint32_t reg, uint32_t val); void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
int intel_punit_read(uint8_t addr, uint32_t *val); int intel_punit_read(uint8_t addr, uint32_t *val);
int intel_punit_write(uint8_t addr, uint32_t val); int intel_punit_write(uint8_t addr, uint32_t val);

2
tools/intel_dpio_read.c
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@ -56,7 +56,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0); intel_register_access_init(dev, 0);
val = intel_dpio_reg_read(reg); val = intel_dpio_reg_read(reg, 0);
printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val); printf("Read DPIO register: 0x%x - Value : 0x%x\n", reg, val);

2
tools/intel_dpio_write.c
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@ -57,7 +57,7 @@ int main(int argc, char** argv)
intel_register_access_init(dev, 0); intel_register_access_init(dev, 0);
intel_dpio_reg_write(reg, val); intel_dpio_reg_write(reg, val, 0);
intel_register_access_fini(); intel_register_access_fini();

4
tools/quick_dump/chipset.i
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@ -16,7 +16,7 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
extern void intel_register_access_fini(); extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake(); extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
extern uint32_t intel_dpio_reg_read(uint32_t reg); extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
%} %}
extern int is_sandybridge(unsigned short pciid); extern int is_sandybridge(unsigned short pciid);
@ -30,4 +30,4 @@ extern uint32_t intel_register_write(uint32_t reg, uint32_t val);
extern void intel_register_access_fini(); extern void intel_register_access_fini();
extern int intel_register_access_needs_fakewake(); extern int intel_register_access_needs_fakewake();
extern unsigned short pcidev_to_devid(struct pci_device *pci_dev); extern unsigned short pcidev_to_devid(struct pci_device *pci_dev);
extern uint32_t intel_dpio_reg_read(uint32_t reg); extern uint32_t intel_dpio_reg_read(uint32_t reg, int phy);

2
tools/quick_dump/quick_dump.py
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@ -21,7 +21,7 @@ def parse_file(file):
for line in file: for line in file:
register = ast.literal_eval(line) register = ast.literal_eval(line)
if register[2] == 'DPIO': if register[2] == 'DPIO':
val = reg.dpio_read(register[1]) val = reg.dpio_read(register[1], 0)
else: else:
val = reg.read(register[1]) val = reg.read(register[1])
intreg = int(register[1], 16) intreg = int(register[1], 16)

6
tools/quick_dump/reg_access.py
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@ -27,9 +27,11 @@ def get_wake():
mt_forcewake_get() mt_forcewake_get()
vlv_forcewake_get() vlv_forcewake_get()
def dpio_read(reg): def dpio_read(reg, phy):
reg = int(reg, 16) reg = int(reg, 16)
val = chipset.intel_dpio_reg_read(reg) phy = int(phy)
val = chipset.intel_dpio_reg_read(reg, phy)
return val return val