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Update dpio read/write to take in extra PHY parameter.

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The extra parameter is for future platform.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This commit is contained in:
Chon Ming Lee
2013-12-04 20:44:33 +08:00
committed by Ville Syrjälä
parent f5643c4a27
commit 0b67c0c421
7 changed files with 26 additions and 13 deletions
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lib/intel_dpio.c
+15 -4
View File
@@ -50,12 +50,23 @@ static void intel_display_reg_write(uint32_t reg, uint32_t val)
*ptr = val;
}
static int get_dpio_port(int phy) {
struct pci_device *dev = intel_get_pci_device();
int dpio_port;
if (IS_VALLEYVIEW(dev->device_id))
dpio_port = DPIO_PORTID;
return dpio_port;
}
/*
* In SoCs like Valleyview some of the PLL & Lane control registers
* can be accessed only through IO side band fabric called DPIO
*/
uint32_t
intel_dpio_reg_read(uint32_t reg)
intel_dpio_reg_read(uint32_t reg, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -64,7 +75,7 @@ intel_dpio_reg_read(uint32_t reg)
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
DPIO_OP_READ | DPIO_PORTID | DPIO_BYTE);
DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
@@ -77,7 +88,7 @@ intel_dpio_reg_read(uint32_t reg)
* can be accessed only through IO side band fabric called DPIO
*/
void
intel_dpio_reg_write(uint32_t reg, uint32_t val)
intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
/* Check whether the side band fabric is ready to accept commands */
do {
@@ -87,7 +98,7 @@ intel_dpio_reg_write(uint32_t reg, uint32_t val)
intel_display_reg_write(DPIO_DATA, val);
intel_display_reg_write(DPIO_REG, reg);
intel_display_reg_write(DPIO_PKT, DPIO_RID |
DPIO_OP_WRITE | DPIO_PORTID | DPIO_BYTE);
DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
do {
usleep(1);
} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
lib/intel_gpu_tools.h
+2 -2
View File
@@ -48,8 +48,8 @@ void intel_register_write(uint32_t reg, uint32_t val);
int intel_register_access_needs_fakewake(void);
/* Following functions are relevant only for SoCs like Valleyview */
uint32_t intel_dpio_reg_read(uint32_t reg);
void intel_dpio_reg_write(uint32_t reg, uint32_t val);
uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
int intel_punit_read(uint8_t addr, uint32_t *val);
int intel_punit_write(uint8_t addr, uint32_t val);