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https://github.com/tiagovignatti/intel-gpu-tools.git
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tests/prime_nv_pcopy: Remove unused tiling tests
We now know that the hardware can't do this, and it's not designed to. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
ee90a4a0dc
commit
0b3407f528
@ -337,132 +337,12 @@ static void swtile_x(uint8_t *out, const uint8_t *in, int w, int h)
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igt_assert(out == endptr);
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}
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#if 0
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/* X tiling is approximately linear, except tiled in 512x8 blocks, so lets abuse that
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*
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* How? Whole contiguous tiles can be copied safely as if linear
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*/
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static int perform_copy_hack(struct nouveau_bo *nvbo, const rect *dst,
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uint32_t dst_x, uint32_t dst_y,
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struct nouveau_bo *nvbi, const rect *src,
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uint32_t src_x, uint32_t src_y,
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uint32_t w, uint32_t h)
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{
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struct nouveau_pushbuf_refn refs[] = {
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{ nvbi, (nvbi->flags & NOUVEAU_BO_APER) | NOUVEAU_BO_RD },
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{ nvbo, (nvbo->flags & NOUVEAU_BO_APER) | NOUVEAU_BO_WR },
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{ query_bo, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR }
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};
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uint32_t exec = 0x00000000;
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uint32_t src_off = 0, dst_off = 0;
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struct nouveau_pushbuf *push = npush;
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uint32_t dw, tiles, tile_src = nvbi->config.nv50.tile_mode, tile_dst = nvbo->config.nv50.tile_mode;
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if (tile_src == tile_intel_x)
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dw = 512 - (src_x & 512);
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else
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dw = 512 - (dst_x % 512);
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if (!nvbi->config.nv50.memtype)
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exec |= 0x00000010;
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if (!tile_src)
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src_off = src_y * src->pitch + src_x;
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if (!nvbo->config.nv50.memtype)
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exec |= 0x00000100;
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if (!tile_dst)
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dst_off = dst_y * dst->pitch + dst_x;
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if (dw > w)
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dw = w;
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tiles = 1 + ((w - dw + 511)/512);
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if (nouveau_pushbuf_space(push, 8 + tiles * 32, 0, 0) ||
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nouveau_pushbuf_refn(push, refs, 3))
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return -1;
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for (; w; w -= dw, src_x += dw, dst_x += dw, dw = w > 512 ? 512 : w) {
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if (tile_src == tile_intel_x) {
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/* Find the correct tiled offset */
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src_off = 8 * dst->pitch * (src_y / 8);
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src_off += src_x / 512 * 4096;
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src_off += (src_x % 512) + 512 * (src_y % 8);
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if (!tile_dst)
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dst_off = dst_y * dst->pitch + dst_x;
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} else {
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if (!tile_src)
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src_off = src_y * src->pitch + src_x;
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dst_off = 8 * dst->pitch * (dst_y / 8);
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dst_off += dst_x / 512 * 4096;
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dst_off += (dst_x % 512) + 512 * (dst_y % 8);
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}
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fprintf(stderr, "Copying from %u to %u for %u bytes\n", src_x, dst_x, dw);
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fprintf(stderr, "src ofs: %u, dst ofs: %u\n", src_off, dst_off);
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BEGIN_NVXX(push, SUBC_COPY(0x0200), 7);
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PUSH_DATA (push, tile_src == tile_intel_x ? 0 : nvbi->config.nv50.tile_mode);
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PUSH_DATA (push, src->pitch);
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PUSH_DATA (push, src->h);
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PUSH_DATA (push, 1);
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PUSH_DATA (push, 0);
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PUSH_DATA (push, src_x);
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PUSH_DATA (push, src_y);
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BEGIN_NVXX(push, SUBC_COPY(0x0220), 7);
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PUSH_DATA (push, tile_dst == tile_intel_x ? 0 : nvbo->config.nv50.tile_mode);
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PUSH_DATA (push, dst->pitch);
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PUSH_DATA (push, dst->h);
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PUSH_DATA (push, 1);
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PUSH_DATA (push, 0);
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PUSH_DATA (push, dst_x);
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PUSH_DATA (push, dst_y);
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BEGIN_NVXX(push, SUBC_COPY(0x030c), 8);
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PUSH_DATA (push, (nvbi->offset + src_off) >> 32);
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PUSH_DATA (push, (nvbi->offset + src_off));
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PUSH_DATA (push, (nvbo->offset + dst_off) >> 32);
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PUSH_DATA (push, (nvbo->offset + dst_off));
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PUSH_DATA (push, src->pitch);
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PUSH_DATA (push, dst->pitch);
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PUSH_DATA (push, dw);
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PUSH_DATA (push, h);
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if (w == dw) {
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exec |= 0x3000; /* QUERY|QUERY_SHORT */
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BEGIN_NVXX(push, SUBC_COPY(0x0338), 3);
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PUSH_DATA (push, (query_bo->offset) >> 32);
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PUSH_DATA (push, (query_bo->offset));
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PUSH_DATA (push, ++query_counter);
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}
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BEGIN_NVXX(push, SUBC_COPY(0x0300), 1);
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PUSH_DATA (push, exec);
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}
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nouveau_pushbuf_kick(push, push->channel);
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while (*query < query_counter) { }
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return 0;
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}
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#endif
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static void perform_copy(struct nouveau_bo *nvbo, const rect *dst,
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uint32_t dst_x, uint32_t dst_y,
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struct nouveau_bo *nvbi, const rect *src,
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uint32_t src_x, uint32_t src_y,
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uint32_t w, uint32_t h)
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{
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#if 0
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/* Too much effort */
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if (nvbi->config.nv50.tile_mode == tile_intel_x &&
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nvbo->config.nv50.tile_mode == tile_intel_x)
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return -1;
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else if (nvbi->config.nv50.tile_mode == tile_intel_x ||
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nvbo->config.nv50.tile_mode == tile_intel_x)
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return perform_copy_hack(nvbo, dst, dst_x, dst_y,
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nvbi, src, src_x, src_y, w, h);
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#endif
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struct nouveau_pushbuf_refn refs[] = {
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{ nvbi, (nvbi->flags & NOUVEAU_BO_APER) | NOUVEAU_BO_RD },
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{ nvbo, (nvbo->flags & NOUVEAU_BO_APER) | NOUVEAU_BO_WR },
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@ -718,139 +598,6 @@ static void test1_micro(void)
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drm_intel_bo_unreference(test_intel_bo);
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}
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#if 0 /* nv can't deswizzle into all possible versions of Intel BO objects ... */
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static int check1_swizzle(uint32_t *p, uint32_t pitch, uint32_t lines,
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uint32_t dst_x, uint32_t dst_y, uint32_t w, uint32_t h)
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{
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uint32_t i, val, j;
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for (j = 0; j < 32; ++j, p += (pitch - w)/4) {
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for (i = 0; i < 8; ++i, p += 4) {
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val = (i * 32) + j;
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val = (val) | (val << 8) | (val << 16) | (val << 24);
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if (p[0] != val || p[1] != val || p[2] != val || p[3] != val) {
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fprintf(stderr, "Retile check failed in first tile!\n");
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fprintf(stderr, "%08x %08x %08x %08x instead of %08x\n",
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p[0], p[1], p[2], p[3], val);
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return -1;
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}
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}
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val = 0x3e3e3e3e;
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for (; i < w/16; ++i, p += 4) {
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if (p[0] != val || p[1] != val || p[2] != val || p[3] != val) {
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fprintf(stderr, "Retile check failed in second tile!\n");
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fprintf(stderr, "%08x %08x %08x %08x instead of %08x\n",
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p[0], p[1], p[2], p[3], val);
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return -1;
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}
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}
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}
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for (j = 32; j < h; ++j, p += (pitch - w)/4) {
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val = 0x7e7e7e7e;
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for (i = 0; i < 8; ++i, p += 4) {
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if (p[0] != val || p[1] != val || p[2] != val || p[3] != val) {
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fprintf(stderr, "Retile check failed in third tile!\n");
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fprintf(stderr, "%08x %08x %08x %08x instead of %08x\n",
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p[0], p[1], p[2], p[3], val);
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return -1;
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}
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}
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val = 0xcececece;
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for (; i < w/16; ++i, p += 4) {
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if (p[0] != val || p[1] != val || p[2] != val || p[3] != val) {
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fprintf(stderr, "Retile check failed in fourth tile!\n");
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fprintf(stderr, "%08x %08x %08x %08x instead of %08x\n",
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p[0], p[1], p[2], p[3], val);
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return -1;
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}
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}
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}
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return 0;
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}
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/* Create a new bo, set tiling to y, and see if macro swizzling is done correctl */
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static int test1_swizzle(void)
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{
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struct nouveau_bo *bo_intel = NULL, *bo_nvidia = NULL, *bo_linear = NULL;
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rect intel, nvidia, linear;
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int ret = -1;
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uint32_t tiling = I915_TILING_Y;
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uint32_t src_x = 0, src_y = 0;
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uint32_t dst_x = 0, dst_y = 0;
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uint32_t x, y, w = 256, h = 64;
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uint8_t *ptr;
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drm_intel_bo *test_intel_bo;
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int prime_fd;
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test_intel_bo = drm_intel_bo_alloc(bufmgr, "test bo", w * h, 4096);
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if (!test_intel_bo)
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return -1;
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drm_intel_bo_set_tiling(test_intel_bo, &tiling, w);
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if (tiling != I915_TILING_Y) {
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fprintf(stderr, "Couldn't set y tiling\n");
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goto out;
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}
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ret = drm_intel_gem_bo_map_gtt(test_intel_bo);
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if (ret)
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goto out;
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drm_intel_bo_gem_export_to_prime(test_intel_bo, &prime_fd);
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if (prime_fd < 0) {
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drm_intel_bo_unreference(test_intel_bo);
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goto out;
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}
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nv_bo_alloc(&bo_intel, &intel, w, h, tile_intel_y, prime_fd, 0);
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nv_bo_alloc(&bo_nvidia, &nvidia, w, h, 0x10, -1, NOUVEAU_BO_VRAM);
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nv_bo_alloc(&bo_linear, &linear, w, h, 0, -1, NOUVEAU_BO_GART);
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noop_intel(test_intel_bo);
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ptr = bo_linear->map;
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for (x = 0; x < 128; x += 16)
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for (y = 0; y < 32; ++y)
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fill16(&ptr[y * w + x], x * 2 + y);
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/* second tile */
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for (x = 128; x < w; x += 16)
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for (y = 0; y < 32; ++y)
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fill16(&ptr[y * w + x], 0x3e);
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/* third tile */
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for (x = 0; x < 128; x += 16)
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for (y = 32; y < h; ++y)
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fill16(&ptr[y * w + x], 0x7e);
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/* last tile */
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for (x = 128; x < w; x += 16)
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for (y = 32; y < h; ++y)
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fill16(&ptr[y * w + x], 0xce);
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ret = perform_copy(bo_nvidia, &nvidia, 0, 0, bo_linear, &linear, 0, 0, nvidia.pitch, nvidia.h);
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if (ret)
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goto out;
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/* Perform the actual sub rectangle copy */
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ret = perform_copy(bo_intel, &intel, dst_x, dst_y, bo_nvidia, &nvidia, src_x, src_y, w, h);
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if (ret)
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goto out;
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noop_intel(test_intel_bo);
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ret = check1_swizzle(test_intel_bo->virtual, intel.pitch, intel.h, dst_x, dst_y, w, h);
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out:
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nouveau_bo_ref(NULL, &bo_linear);
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nouveau_bo_ref(NULL, &bo_nvidia);
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nouveau_bo_ref(NULL, &bo_intel);
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drm_intel_bo_unreference(test_intel_bo);
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return ret;
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}
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#endif
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/* test 2, see if we can copy from linear to intel X format safely
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* Seems nvidia lacks a method to do it, so just keep this test
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* as a reference for potential future tests. Software tiling is
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