mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
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tests/pm_sseu: Create new test pm_sseu
New test pm_sseu is intended for any subtest related to the
slice/subslice/EU power gating feature. The sole initial subtest,
'full-enable', confirms that the slice/subslice/EU state is at
full enablement when the render engine is active. Starting with
Gen9 SKL, the render power gating feature can leave SSEU in a
partially enabled state upon resumption of render work unless
explicit action is taken.
v2: Add test description and apply recommendations of igt.cocci
(Thomas Wood).
v3: Skip instead of fail if debugfs entry i915_sseu_status is not
available.
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Tested-by: Lei Liu <lei.a.liu@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
This commit is contained in:
Jeff McGee
Thomas Wood
parent
aef4605f7c
commit
07707aff75
1
tests/.gitignore
vendored
1
tests/.gitignore
vendored
@ -146,6 +146,7 @@ pm_lpsp
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pm_rc6_residency
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pm_rpm
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pm_rps
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pm_sseu
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prime_nv_api
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prime_nv_pcopy
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prime_nv_test
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@ -86,6 +86,7 @@ TESTS_progs_M = \
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pm_rpm \
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pm_rps \
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pm_rc6_residency \
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pm_sseu \
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prime_self_import \
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template \
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$(NULL)
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376
tests/pm_sseu.c
Normal file
376
tests/pm_sseu.c
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@ -0,0 +1,376 @@
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jeff McGee <jeff.mcgee@intel.com>
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*/
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#include <fcntl.h>
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#include <unistd.h>
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#include <string.h>
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#include <errno.h>
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#include <time.h>
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#include "drmtest.h"
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#include "i915_drm.h"
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#include "intel_io.h"
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#include "intel_bufmgr.h"
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#include "intel_batchbuffer.h"
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#include "intel_chipset.h"
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#include "ioctl_wrappers.h"
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#include "igt_debugfs.h"
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#include "media_spin.h"
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IGT_TEST_DESCRIPTION("Tests slice/subslice/EU power gating functionality.\n");
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static double
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to_dt(const struct timespec *start, const struct timespec *end)
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{
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double dt;
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dt = (end->tv_sec - start->tv_sec) * 1e3;
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dt += (end->tv_nsec - start->tv_nsec) * 1e-6;
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return dt;
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}
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struct status {
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struct {
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int slice_total;
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int subslice_total;
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int subslice_per;
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int eu_total;
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int eu_per;
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bool has_slice_pg;
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bool has_subslice_pg;
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bool has_eu_pg;
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} info;
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struct {
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int slice_total;
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int subslice_total;
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int subslice_per;
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int eu_total;
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int eu_per;
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} hw;
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};
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#define DBG_STATUS_BUF_SIZE 4096
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struct {
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int init;
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int status_fd;
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char status_buf[DBG_STATUS_BUF_SIZE];
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} dbg;
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static void
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dbg_get_status_section(const char *title, char **first, char **last)
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{
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char *pos;
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*first = strstr(dbg.status_buf, title);
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igt_assert(*first != NULL);
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pos = *first;
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do {
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pos = strchr(pos, '\n');
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igt_assert(pos != NULL);
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pos++;
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} while (*pos == ' '); /* lines in the section begin with a space */
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*last = pos - 1;
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}
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static int
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dbg_get_int(const char *first, const char *last, const char *name)
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{
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char *pos;
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pos = strstr(first, name);
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igt_assert(pos != NULL);
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pos = strstr(pos, ":");
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igt_assert(pos != NULL);
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pos += 2;
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igt_assert(pos != last);
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return strtol(pos, &pos, 10);
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}
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static bool
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dbg_get_bool(const char *first, const char *last, const char *name)
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{
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char *pos;
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pos = strstr(first, name);
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igt_assert(pos != NULL);
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pos = strstr(pos, ":");
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igt_assert(pos != NULL);
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pos += 2;
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igt_assert(pos < last);
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if (*pos == 'y')
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return true;
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if (*pos == 'n')
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return false;
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igt_assert_f(false, "Could not read boolean value for %s.\n", name);
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return false;
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}
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static void
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dbg_get_status(struct status *stat)
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{
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char *first, *last;
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int nread;
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lseek(dbg.status_fd, 0, SEEK_SET);
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nread = read(dbg.status_fd, dbg.status_buf, DBG_STATUS_BUF_SIZE);
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igt_assert_lt(nread, DBG_STATUS_BUF_SIZE);
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dbg.status_buf[nread] = '\0';
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memset(stat, 0, sizeof(*stat));
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dbg_get_status_section("SSEU Device Info", &first, &last);
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stat->info.slice_total =
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dbg_get_int(first, last, "Available Slice Total:");
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stat->info.subslice_total =
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dbg_get_int(first, last, "Available Subslice Total:");
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stat->info.subslice_per =
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dbg_get_int(first, last, "Available Subslice Per Slice:");
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stat->info.eu_total =
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dbg_get_int(first, last, "Available EU Total:");
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stat->info.eu_per =
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dbg_get_int(first, last, "Available EU Per Subslice:");
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stat->info.has_slice_pg =
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dbg_get_bool(first, last, "Has Slice Power Gating:");
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stat->info.has_subslice_pg =
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dbg_get_bool(first, last, "Has Subslice Power Gating:");
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stat->info.has_eu_pg =
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dbg_get_bool(first, last, "Has EU Power Gating:");
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dbg_get_status_section("SSEU Device Status", &first, &last);
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stat->hw.slice_total =
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dbg_get_int(first, last, "Enabled Slice Total:");
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stat->hw.subslice_total =
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dbg_get_int(first, last, "Enabled Subslice Total:");
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stat->hw.subslice_per =
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dbg_get_int(first, last, "Enabled Subslice Per Slice:");
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stat->hw.eu_total =
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dbg_get_int(first, last, "Enabled EU Total:");
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stat->hw.eu_per =
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dbg_get_int(first, last, "Enabled EU Per Subslice:");
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}
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static void
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dbg_init(void)
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{
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dbg.status_fd = igt_debugfs_open("i915_sseu_status", O_RDONLY);
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igt_skip_on_f(dbg.status_fd == -1,
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"debugfs entry 'i915_sseu_status' not found\n");
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dbg.init = 1;
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}
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static void
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dbg_deinit(void)
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{
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switch (dbg.init)
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{
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case 1:
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close(dbg.status_fd);
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}
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}
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struct {
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int init;
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int drm_fd;
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int devid;
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int gen;
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int has_ppgtt;
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drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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igt_media_spinfunc_t spinfunc;
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struct igt_buf buf;
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uint32_t spins_per_msec;
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} gem;
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static void
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gem_check_spin(uint32_t spins)
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{
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uint32_t *data;
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data = (uint32_t*)gem.buf.bo->virtual;
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igt_assert_eq_u32(*data, spins);
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}
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static uint32_t
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gem_get_target_spins(double dt)
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{
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struct timespec tstart, tdone;
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double prev_dt, cur_dt;
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uint32_t spins;
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int i, ret;
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/* Double increments until we bound the target time */
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prev_dt = 0.0;
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for (i = 0; i < 32; i++) {
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spins = 1 << i;
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clock_gettime(CLOCK_MONOTONIC, &tstart);
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gem.spinfunc(gem.batch, &gem.buf, spins);
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ret = drm_intel_bo_map(gem.buf.bo, 0);
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igt_assert_eq(ret, 0);
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clock_gettime(CLOCK_MONOTONIC, &tdone);
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gem_check_spin(spins);
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drm_intel_bo_unmap(gem.buf.bo);
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cur_dt = to_dt(&tstart, &tdone);
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if (cur_dt > dt)
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break;
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prev_dt = cur_dt;
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}
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igt_assert_neq(i, 32);
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/* Linearly interpolate between i and i-1 to get target increments */
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spins = 1 << (i-1); /* lower bound spins */
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spins += spins * (dt - prev_dt)/(cur_dt - prev_dt); /* target spins */
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return spins;
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}
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static void
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gem_init(void)
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{
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gem.drm_fd = drm_open_any();
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gem.init = 1;
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gem.devid = intel_get_drm_devid(gem.drm_fd);
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gem.gen = intel_gen(gem.devid);
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gem.has_ppgtt = gem_uses_aliasing_ppgtt(gem.drm_fd);
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gem.bufmgr = drm_intel_bufmgr_gem_init(gem.drm_fd, 4096);
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igt_assert(gem.bufmgr);
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gem.init = 2;
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drm_intel_bufmgr_gem_enable_reuse(gem.bufmgr);
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gem.batch = intel_batchbuffer_alloc(gem.bufmgr, gem.devid);
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igt_assert(gem.batch);
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gem.init = 3;
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gem.spinfunc = igt_get_media_spinfunc(gem.devid);
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igt_assert(gem.spinfunc);
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gem.buf.stride = sizeof(uint32_t);
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gem.buf.tiling = I915_TILING_NONE;
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gem.buf.size = gem.buf.stride;
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gem.buf.bo = drm_intel_bo_alloc(gem.bufmgr, "", gem.buf.size, 4096);
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igt_assert(gem.buf.bo);
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gem.init = 4;
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gem.spins_per_msec = gem_get_target_spins(100) / 100;
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}
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static void
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gem_deinit(void)
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{
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switch (gem.init)
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{
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case 4:
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drm_intel_bo_unmap(gem.buf.bo);
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drm_intel_bo_unreference(gem.buf.bo);
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case 3:
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intel_batchbuffer_free(gem.batch);
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case 2:
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drm_intel_bufmgr_destroy(gem.bufmgr);
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case 1:
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close(gem.drm_fd);
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}
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}
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static void
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check_full_enable(struct status *stat)
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{
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igt_assert_eq(stat->hw.slice_total, stat->info.slice_total);
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igt_assert_eq(stat->hw.subslice_total, stat->info.subslice_total);
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igt_assert_eq(stat->hw.subslice_per, stat->info.subslice_per);
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/*
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* EU are powered in pairs, but it is possible for one EU in the pair
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* to be non-functional due to fusing. The determination of enabled
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* EU does not account for this and can therefore actually exceed the
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* available count. Allow for this small discrepancy in our
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* comparison.
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*/
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igt_assert_lte(stat->info.eu_total, stat->hw.eu_total);
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igt_assert_lte(stat->info.eu_per, stat->hw.eu_per);
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}
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static void
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full_enable(void)
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{
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struct status stat;
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const int spin_msec = 10;
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int ret, spins;
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/* Simulation doesn't currently model slice/subslice/EU power gating. */
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igt_skip_on_simulation();
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/*
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* Gen9 SKL is the first case in which render power gating can leave
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* slice/subslice/EU in a partially enabled state upon resumption of
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* render work. So start checking that this is prevented as of Gen9.
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*/
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igt_require(gem.gen >= 9);
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spins = spin_msec * gem.spins_per_msec;
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gem.spinfunc(gem.batch, &gem.buf, spins);
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usleep(2000); /* 2ms wait to make sure batch is running */
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dbg_get_status(&stat);
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ret = drm_intel_bo_map(gem.buf.bo, 0);
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igt_assert_eq(ret, 0);
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gem_check_spin(spins);
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drm_intel_bo_unmap(gem.buf.bo);
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check_full_enable(&stat);
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}
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static void
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exit_handler(int sig)
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{
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gem_deinit();
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dbg_deinit();
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}
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igt_main
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{
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igt_fixture {
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igt_install_exit_handler(exit_handler);
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dbg_init();
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gem_init();
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}
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igt_subtest("full-enable")
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full_enable();
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}
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