mirror of
https://github.com/ioacademy-jikim/debugging
synced 2025-06-10 01:16:12 +00:00
225 lines
6.3 KiB
C
225 lines
6.3 KiB
C
#define OFFSET_x86_EAX 8
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#define OFFSET_x86_EBX 20
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#define OFFSET_x86_ECX 12
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#define OFFSET_x86_EDX 16
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#define OFFSET_x86_ESI 32
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#define OFFSET_x86_EDI 36
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#define OFFSET_x86_EBP 28
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#define OFFSET_x86_ESP 24
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#define OFFSET_x86_EIP 68
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#define OFFSET_x86_CS 288
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#define OFFSET_x86_DS 290
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#define OFFSET_x86_ES 292
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#define OFFSET_x86_FS 294
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#define OFFSET_x86_GS 296
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#define OFFSET_x86_SS 298
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#define OFFSET_amd64_RAX 16
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#define OFFSET_amd64_RBX 40
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#define OFFSET_amd64_RCX 24
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#define OFFSET_amd64_RDX 32
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#define OFFSET_amd64_RSI 64
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#define OFFSET_amd64_RDI 72
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#define OFFSET_amd64_RSP 48
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#define OFFSET_amd64_RBP 56
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#define OFFSET_amd64_R8 80
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#define OFFSET_amd64_R9 88
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#define OFFSET_amd64_R10 96
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#define OFFSET_amd64_R11 104
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#define OFFSET_amd64_R12 112
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#define OFFSET_amd64_R13 120
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#define OFFSET_amd64_R14 128
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#define OFFSET_amd64_R15 136
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#define OFFSET_amd64_RIP 184
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#define OFFSET_ppc32_GPR0 16
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#define OFFSET_ppc32_GPR1 20
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#define OFFSET_ppc32_GPR2 24
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#define OFFSET_ppc32_GPR3 28
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#define OFFSET_ppc32_GPR4 32
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#define OFFSET_ppc32_GPR5 36
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#define OFFSET_ppc32_GPR6 40
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#define OFFSET_ppc32_GPR7 44
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#define OFFSET_ppc32_GPR8 48
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#define OFFSET_ppc32_GPR9 52
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#define OFFSET_ppc32_GPR10 56
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#define OFFSET_ppc32_CIA 1168
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#define OFFSET_ppc32_CR0_0 1185
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#define OFFSET_ppc64_GPR0 16
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#define OFFSET_ppc64_GPR1 24
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#define OFFSET_ppc64_GPR2 32
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#define OFFSET_ppc64_GPR3 40
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#define OFFSET_ppc64_GPR4 48
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#define OFFSET_ppc64_GPR5 56
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#define OFFSET_ppc64_GPR6 64
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#define OFFSET_ppc64_GPR7 72
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#define OFFSET_ppc64_GPR8 80
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#define OFFSET_ppc64_GPR9 88
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#define OFFSET_ppc64_GPR10 96
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#define OFFSET_ppc64_CIA 1296
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#define OFFSET_ppc64_CR0_0 1325
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#define OFFSET_arm_R0 8
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#define OFFSET_arm_R1 12
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#define OFFSET_arm_R2 16
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#define OFFSET_arm_R3 20
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#define OFFSET_arm_R4 24
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#define OFFSET_arm_R5 28
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#define OFFSET_arm_R7 36
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#define OFFSET_arm_R13 60
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#define OFFSET_arm_R14 64
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#define OFFSET_arm_R15T 68
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#define OFFSET_arm64_X0 16
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#define OFFSET_arm64_X1 24
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#define OFFSET_arm64_X2 32
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#define OFFSET_arm64_X3 40
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#define OFFSET_arm64_X4 48
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#define OFFSET_arm64_X5 56
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#define OFFSET_arm64_X6 64
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#define OFFSET_arm64_X7 72
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#define OFFSET_arm64_X8 80
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#define OFFSET_arm64_XSP 264
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#define OFFSET_arm64_PC 272
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#define OFFSET_s390x_r2 208
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#define OFFSET_s390x_r3 216
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#define OFFSET_s390x_r4 224
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#define OFFSET_s390x_r5 232
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#define OFFSET_s390x_r6 240
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#define OFFSET_s390x_r7 248
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#define OFFSET_s390x_r15 312
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#define OFFSET_s390x_IA 336
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#define OFFSET_s390x_SYSNO 344
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#define OFFSET_s390x_IP_AT_SYSCALL 408
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#define OFFSET_s390x_fpc 328
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#define OFFSET_s390x_CC_OP 352
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#define OFFSET_s390x_CC_DEP1 360
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#define OFFSET_s390x_CC_DEP2 368
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#define OFFSET_s390x_CC_NDEP 376
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#define OFFSET_mips32_r0 0
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#define OFFSET_mips32_r1 4
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#define OFFSET_mips32_r2 8
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#define OFFSET_mips32_r3 12
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#define OFFSET_mips32_r4 16
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#define OFFSET_mips32_r5 20
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#define OFFSET_mips32_r6 24
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#define OFFSET_mips32_r7 28
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#define OFFSET_mips32_r8 32
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#define OFFSET_mips32_r9 36
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#define OFFSET_mips32_r10 40
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#define OFFSET_mips32_r11 44
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#define OFFSET_mips32_r12 48
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#define OFFSET_mips32_r13 52
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#define OFFSET_mips32_r14 56
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#define OFFSET_mips32_r15 60
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#define OFFSET_mips32_r15 60
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#define OFFSET_mips32_r17 68
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#define OFFSET_mips32_r18 72
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#define OFFSET_mips32_r19 76
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#define OFFSET_mips32_r20 80
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#define OFFSET_mips32_r21 84
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#define OFFSET_mips32_r22 88
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#define OFFSET_mips32_r23 92
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#define OFFSET_mips32_r24 96
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#define OFFSET_mips32_r25 100
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#define OFFSET_mips32_r26 104
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#define OFFSET_mips32_r27 108
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#define OFFSET_mips32_r28 112
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#define OFFSET_mips32_r29 116
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#define OFFSET_mips32_r30 120
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#define OFFSET_mips32_r31 124
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#define OFFSET_mips32_PC 128
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#define OFFSET_mips32_HI 132
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#define OFFSET_mips32_LO 136
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#define OFFSET_mips64_r0 0
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#define OFFSET_mips64_r1 8
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#define OFFSET_mips64_r2 16
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#define OFFSET_mips64_r3 24
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#define OFFSET_mips64_r4 32
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#define OFFSET_mips64_r5 40
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#define OFFSET_mips64_r6 48
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#define OFFSET_mips64_r7 56
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#define OFFSET_mips64_r8 64
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#define OFFSET_mips64_r9 72
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#define OFFSET_mips64_r10 80
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#define OFFSET_mips64_r11 88
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#define OFFSET_mips64_r12 96
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#define OFFSET_mips64_r13 104
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#define OFFSET_mips64_r14 112
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#define OFFSET_mips64_r15 120
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#define OFFSET_mips64_r15 120
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#define OFFSET_mips64_r17 136
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#define OFFSET_mips64_r18 144
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#define OFFSET_mips64_r19 152
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#define OFFSET_mips64_r20 160
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#define OFFSET_mips64_r21 168
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#define OFFSET_mips64_r22 176
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#define OFFSET_mips64_r23 184
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#define OFFSET_mips64_r24 192
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#define OFFSET_mips64_r25 200
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#define OFFSET_mips64_r26 208
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#define OFFSET_mips64_r27 216
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#define OFFSET_mips64_r28 224
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#define OFFSET_mips64_r29 232
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#define OFFSET_mips64_r30 240
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#define OFFSET_mips64_r31 248
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#define OFFSET_mips64_PC 256
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#define OFFSET_mips64_HI 264
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#define OFFSET_mips64_LO 272
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#define OFFSET_tilegx_r0 0
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#define OFFSET_tilegx_r1 8
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#define OFFSET_tilegx_r2 16
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#define OFFSET_tilegx_r3 24
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#define OFFSET_tilegx_r4 32
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#define OFFSET_tilegx_r5 40
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#define OFFSET_tilegx_r6 48
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#define OFFSET_tilegx_r7 56
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#define OFFSET_tilegx_r8 64
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#define OFFSET_tilegx_r9 72
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#define OFFSET_tilegx_r10 80
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#define OFFSET_tilegx_r11 88
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#define OFFSET_tilegx_r12 96
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#define OFFSET_tilegx_r13 104
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#define OFFSET_tilegx_r14 112
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#define OFFSET_tilegx_r15 120
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#define OFFSET_tilegx_r16 128
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#define OFFSET_tilegx_r17 136
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#define OFFSET_tilegx_r18 144
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#define OFFSET_tilegx_r19 152
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#define OFFSET_tilegx_r20 160
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#define OFFSET_tilegx_r21 168
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#define OFFSET_tilegx_r22 176
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#define OFFSET_tilegx_r23 184
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#define OFFSET_tilegx_r24 192
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#define OFFSET_tilegx_r25 200
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#define OFFSET_tilegx_r26 208
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#define OFFSET_tilegx_r27 216
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#define OFFSET_tilegx_r28 224
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#define OFFSET_tilegx_r29 232
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#define OFFSET_tilegx_r30 240
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#define OFFSET_tilegx_r31 248
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#define OFFSET_tilegx_r32 256
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#define OFFSET_tilegx_r33 264
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#define OFFSET_tilegx_r34 272
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#define OFFSET_tilegx_r35 280
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#define OFFSET_tilegx_r36 288
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#define OFFSET_tilegx_r37 296
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#define OFFSET_tilegx_r38 304
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#define OFFSET_tilegx_r39 312
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#define OFFSET_tilegx_r40 320
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#define OFFSET_tilegx_r41 328
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#define OFFSET_tilegx_r42 336
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#define OFFSET_tilegx_r43 344
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#define OFFSET_tilegx_r44 352
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#define OFFSET_tilegx_r45 360
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#define OFFSET_tilegx_r46 368
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#define OFFSET_tilegx_r47 376
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#define OFFSET_tilegx_r48 384
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#define OFFSET_tilegx_r49 392
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#define OFFSET_tilegx_r50 400
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#define OFFSET_tilegx_r51 408
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#define OFFSET_tilegx_r52 416
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#define OFFSET_tilegx_r53 424
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#define OFFSET_tilegx_r54 432
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#define OFFSET_tilegx_r55 440
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#define OFFSET_tilegx_pc 512
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#define OFFSET_tilegx_EMNOTE 528
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#define OFFSET_tilegx_CMSTART 536
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#define OFFSET_tilegx_NRADDR 552
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