mirror of
https://github.com/ioacademy-jikim/debugging
synced 2026-08-29 16:59:40 +00:00
jikim
58 lines
2.5 KiB
XML
58 lines
2.5 KiB
XML
<?xml version="1.0"?>
|
|
<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
are permitted in any medium without royalty provided the copyright
|
|
notice and this notice are preserved. -->
|
|
|
|
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
|
<feature name="org.gnu.gdb.power.altivec-valgrind-s1">
|
|
<vector id="v4f" type="ieee_single" count="4"/>
|
|
<vector id="v4i32" type="int32" count="4"/>
|
|
<vector id="v8i16" type="int16" count="8"/>
|
|
<vector id="v16i8" type="int8" count="16"/>
|
|
<union id="vec128">
|
|
<field name="uint128" type="uint128"/>
|
|
<field name="v4_float" type="v4f"/>
|
|
<field name="v4_int32" type="v4i32"/>
|
|
<field name="v8_int16" type="v8i16"/>
|
|
<field name="v16_int8" type="v16i8"/>
|
|
</union>
|
|
|
|
<reg name="vr0s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr1s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr2s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr3s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr4s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr5s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr6s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr7s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr8s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr9s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr10s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr11s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr12s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr13s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr14s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr15s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr16s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr17s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr18s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr19s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr20s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr21s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr22s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr23s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr24s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr25s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr26s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr27s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr28s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr29s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr30s1" bitsize="128" type="vec128"/>
|
|
<reg name="vr31s1" bitsize="128" type="vec128"/>
|
|
|
|
<reg name="vscrs1" bitsize="32" group="vector"/>
|
|
<reg name="vrsaves1" bitsize="32" group="vector"/>
|
|
</feature>
|