mirror of
https://github.com/ioacademy-jikim/debugging
synced 2025-06-17 12:56:19 +00:00
676 lines
22 KiB
C
676 lines
22 KiB
C
/* Copyright (C) 2012 IBM
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Author: Maynard Johnson <maynardj@us.ibm.com>
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Carl Love <carll@us.ibm.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <elf.h>
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#include <link.h>
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#define PPC_FEATURE_HAS_VSX 0x00000080 /* Vector Scalar Extension. */
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#if defined(HAS_DFP)
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register double f14 __asm__ ("fr14");
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register double f15 __asm__ ("fr15");
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register double f16 __asm__ ("fr16");
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register double f17 __asm__ ("fr17");
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register double f18 __asm__ ("fr18");
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register double f19 __asm__ ("fr19");
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typedef unsigned char Bool;
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#define True 1
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#define False 0
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#define SET_FPSCR_ZERO \
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do { double _d = 0.0; \
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__asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
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} while (0)
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#define GET_FPSCR(_arg) \
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__asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
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#define SET_FPSCR_DRN \
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__asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
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#define SH_0 0
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#define SH_1 1
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#define SH_2 15
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#define SH_3 63
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#define NUM_RND_MODES 8
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#define CONDREG_MASK 0x0f000000
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#define CONDREG_SHIFT 24
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static char ** my_envp;
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static inline char** __auxv_find(void)
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{
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char **result = my_envp;
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/* Scan over the env vector looking for the ending NULL */
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for (; *result != NULL; ++result) {
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}
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/* Bump the pointer one more step, which should be the auxv. */
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return ++result;
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}
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static unsigned long fetch_at_hwcap(void)
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{
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static unsigned long auxv_hwcap = 0;
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int i;
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ElfW(auxv_t) * auxv_buf = NULL;
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if (auxv_hwcap)
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return auxv_hwcap;
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auxv_buf = (ElfW(auxv_t)*) __auxv_find();
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for (i = 0; auxv_buf[i].a_type != AT_NULL; i++)
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if (auxv_buf[i].a_type == AT_HWCAP) {
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auxv_hwcap = auxv_buf[i].a_un.a_val;
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break;
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}
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return auxv_hwcap;
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}
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int get_vsx(void)
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{
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/* Check to see if the AUX vector has the bit set indicating the HW
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* supports the vsx instructions. This implies the processor is
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* at least a POWER 7.
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*/
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unsigned long hwcap;
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hwcap = fetch_at_hwcap();
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if ((hwcap & PPC_FEATURE_HAS_VSX) == PPC_FEATURE_HAS_VSX)
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return 1;
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return 0;
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}
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/* The assembly-level instructions being tested */
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static void _test_dscri (int shift)
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{
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switch(shift) {
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case SH_0:
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__asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
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break;
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case SH_1:
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__asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
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break;
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case SH_2:
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__asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
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break;
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case SH_3:
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__asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
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break;
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default:
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printf(" dscri, unsupported shift case %d\n", shift);
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}
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}
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static void _test_dscli (int shift)
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{
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switch(shift) {
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case SH_0:
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__asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
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break;
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case SH_1:
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__asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
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break;
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case SH_2:
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__asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
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break;
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case SH_3:
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__asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
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break;
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default:
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printf(" dscli, unsupported shift case %d\n", shift);
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}
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}
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static void _test_dctdp (void)
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{
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__asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_drsp (void)
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{
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__asm__ __volatile__ ("drsp %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_dctfix (void)
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{
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__asm__ __volatile__ ("dctfix %0, %1" : "=f" (f18) : "f" (f14));
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}
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/* Power 7 and newer processors support this instruction */
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static void _test_dcffix (void)
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{
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__asm__ __volatile__ ("dcffix %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_dscriq (int shift)
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{
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switch(shift) {
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case SH_0:
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__asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
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break;
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case SH_1:
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__asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
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break;
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case SH_2:
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__asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
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break;
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case SH_3:
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__asm__ __volatile__ ("dscriq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
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break;
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default:
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printf(" dscriq, unsupported shift case %d\n", shift);
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}
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}
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static void _test_dscliq (int shift)
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{
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switch(shift) {
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case SH_0:
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__asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0));
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break;
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case SH_1:
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__asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1));
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break;
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case SH_2:
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__asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2));
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break;
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case SH_3:
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__asm__ __volatile__ ("dscliq %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3));
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break;
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default:
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printf(" dscliq, unsupported shift case %d\n", shift);
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}
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}
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static void _test_dctqpq (void)
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{
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__asm__ __volatile__ ("dctqpq %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_dctfixq (void)
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{
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__asm__ __volatile__ ("dctfixq %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_drdpq (void)
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{
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__asm__ __volatile__ ("drdpq %0, %1" : "=f" (f18) : "f" (f14));
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}
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static void _test_dcffixq (void)
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{
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__asm__ __volatile__ ("dcffixq %0, %1" : "=f" (f18) : "f" (f14));
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}
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typedef void (*test_func_t)();
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typedef void (*test_func_main_t)(int);
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typedef void (*test_func_shift_t)(int);
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typedef struct test_table
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{
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test_func_main_t test_category;
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char * name;
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} test_table_t;
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static unsigned long long dfp128_vals[] = {
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// Some finite numbers
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0x2207c00000000000ULL, 0x0000000000000e50ULL,
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0x2f07c00000000000ULL, 0x000000000014c000ULL, //large number
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0xa207c00000000000ULL, 0x00000000000000e0ULL,
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0x2206c00000000000ULL, 0x00000000000000cfULL,
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0xa205c00000000000ULL, 0x000000010a395bcfULL,
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0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // a small number
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0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
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// flavors of zero
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0x2208000000000000ULL, 0x0000000000000000ULL,
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0xa208000000000000ULL, 0x0000000000000000ULL, // negative
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0xa248000000000000ULL, 0x0000000000000000ULL,
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// flavors of NAN
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0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
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0xfc00000000000000ULL, 0xc00100035b007700ULL,
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0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
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// flavors of Infinity
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0x7800000000000000ULL, 0x0000000000000000ULL,
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0xf800000000000000ULL, 0x0000000000000000ULL, // negative
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0xf900000000000000ULL, 0x0000000000000000ULL
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};
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static unsigned long long int64_vals[] = {
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// I64 values
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0x0ULL, // zero
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0x1ULL, // one
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0xffffffffffffffffULL, // minus one
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0x2386f26fc0ffffULL, // 9999999999999999
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0xffdc790d903f0001ULL, // -9999999999999999
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0x462d53c8abac0ULL, // 1234567890124567
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0xfffb9d2ac3754540ULL, // -1234567890124567
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};
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static unsigned long long dfp64_vals[] = {
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// various finite numbers
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0x2234000000000e50ULL,
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0x223400000014c000ULL,
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0xa2340000000000e0ULL,// negative
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0x22240000000000cfULL,
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0xa21400010a395bcfULL,// negative
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0x6e4d3f1f534acdd4ULL,// large number
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0x000400000089b000ULL,// very small number
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// flavors of zero
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0x2238000000000000ULL,
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0xa238000000000000ULL,
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0x4248000000000000ULL,
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// flavors of NAN
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0x7e34000000000111ULL,
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0xfe000000d0e0a0d0ULL,//signaling
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0xfc00000000000000ULL,//quiet
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// flavors of Infinity
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0x7800000000000000ULL,
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0xf800000000000000ULL,//negative
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0x7a34000000000000ULL,
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};
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typedef struct dfp_test_args {
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int fra_idx;
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int frb_idx;
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} dfp_test_args_t;
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/* Index pairs from dfp64_vals or dfp128_vals array to be used with
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* dfp_two_arg_tests */
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static dfp_test_args_t int64_args_x1[] = {
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/* {int64 input val, unused } */
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{0, 0},
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{1, 0},
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{2, 0},
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{3, 0},
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{4, 0},
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{5, 0},
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{6, 0},
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};
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static dfp_test_args_t dfp_2args_x1[] = {
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/* {dfp_arg, shift_arg} */
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{0, SH_0},
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{0, SH_1},
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{0, SH_2},
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{0, SH_3},
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{5, SH_0},
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{5, SH_1},
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{5, SH_2},
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{5, SH_3},
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{6, SH_0},
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{6, SH_1},
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{6, SH_2},
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{6, SH_3},
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{7, SH_0},
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{7, SH_1},
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{7, SH_2},
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{7, SH_3},
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{10, SH_0},
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{10, SH_1},
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{10, SH_2},
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{10, SH_3},
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{13, SH_0},
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{13, SH_1},
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{13, SH_2},
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{13, SH_3},
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};
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/* Index pairs from dfp64_vals array to be used with dfp_one_arg_tests */
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static dfp_test_args_t dfp_1args_x1[] = {
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/* {dfp_arg, unused} */
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{0, 0},
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{1, 0},
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{2, 0},
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{3, 0},
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{4, 0},
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{5, 0},
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{6, 0},
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{7, 0},
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{8, 0},
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{9, 0},
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{10, 0},
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{11, 0},
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{12, 0},
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{13, 0},
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{14, 0},
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};
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typedef enum {
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LONG_TEST,
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QUAD_TEST
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} precision_type_t;
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typedef struct dfp_test
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{
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test_func_t test_func;
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const char * name;
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dfp_test_args_t * targs;
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int num_tests;
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precision_type_t precision;
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const char * op;
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Bool cr_supported;
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} dfp_test_t;
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/* The dcffix and dcffixq tests are a little different in that they both take
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* an I64 input.
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*/
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static dfp_test_t
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dfp_dcffix_dcffixq_tests[] = {
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{ &_test_dcffixq,"dcffixq", int64_args_x1, 7, QUAD_TEST, "I64S->D128", True},
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/* Power 7 instruction */
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{ &_test_dcffix, "dcffix", int64_args_x1, 7, LONG_TEST, "I64S->D64", True},
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{ NULL, NULL, NULL, 0, 0, NULL}
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};
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static dfp_test_t
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dfp_one_arg_tests[] = {
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{ &_test_dctdp, "dctdp", dfp_1args_x1, 15, LONG_TEST, "D32->D64", True},
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{ &_test_drsp, "drsp", dfp_1args_x1, 15, LONG_TEST, "D64->D32", True},
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{ &_test_dctfix, "dctfix", dfp_1args_x1, 15, LONG_TEST, "D64->I64S", True},
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{ &_test_dctqpq, "dctqpq", dfp_1args_x1, 15, QUAD_TEST, "D64->D128", True},
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{ &_test_dctfixq,"dctfixq", dfp_1args_x1, 15, QUAD_TEST, "D128->I64S", True},
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{ &_test_drdpq, "drdpq", dfp_1args_x1, 15, QUAD_TEST, "D128->D64", True},
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{ NULL, NULL, NULL, 0, 0, NULL}
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};
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static dfp_test_t
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dfp_two_arg_tests[] = {
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{ &_test_dscri, "dscri", dfp_2args_x1, 20, LONG_TEST, ">>", True},
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{ &_test_dscli, "dscli", dfp_2args_x1, 20, LONG_TEST, "<<", True},
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{ &_test_dscriq, "dscriq", dfp_2args_x1, 20, QUAD_TEST, ">>", True},
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{ &_test_dscliq, "dscliq", dfp_2args_x1, 20, QUAD_TEST, "<<", True},
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{ NULL, NULL, NULL, 0, 0, NULL}
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};
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void set_rounding_mode(unsigned long long rnd_mode)
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{
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double fpscr;
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unsigned long long * hex_fpscr = (unsigned long long *)&fpscr;
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*hex_fpscr = 0ULL;
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__asm__ __volatile__ ("mffs %0" : "=f"(f14));
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fpscr = f14;
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*hex_fpscr &= 0xFFFFFFF0FFFFFFFFULL;
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*hex_fpscr |= (rnd_mode << 32);
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f14 = fpscr;
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SET_FPSCR_DRN;
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}
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static void test_dfp_one_arg_ops(int unused)
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{
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test_func_t func;
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unsigned long long u0, u0x;
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double res, d0, *d0p;
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double d0x, *d0xp;
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unsigned long round_mode;
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int k = 0;
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u0x = 0;
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d0p = &d0;
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d0xp = &d0x;
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while ((func = dfp_one_arg_tests[k].test_func)) {
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int i;
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for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
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/* Do each test with each of the possible rounding modes */
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dfp_test_t test_group = dfp_one_arg_tests[k];
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printf("\ntest with rounding mode %lu \n", round_mode);
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/* The set_rounding_mode() uses the global value f14. Call the
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* function before setting up the test for the specific instruction
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* to avoid avoid conflicts using f14.
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*/
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set_rounding_mode(round_mode);
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for (i = 0; i < test_group.num_tests; i++) {
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if (test_group.precision == LONG_TEST) {
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u0 = dfp64_vals[test_group.targs[i].fra_idx];
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} else {
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u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
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u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
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}
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*(unsigned long long *)d0p = u0;
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f14 = d0;
|
|
if (test_group.precision == QUAD_TEST) {
|
|
*(unsigned long long *)d0xp = u0x;
|
|
f15 = d0x;
|
|
}
|
|
|
|
(*func)();
|
|
res = f18;
|
|
|
|
printf("%s %016llx", test_group.name, u0);
|
|
|
|
if (test_group.precision == LONG_TEST) {
|
|
printf(" %s => %016llx",
|
|
test_group.op, *((unsigned long long *)(&res)));
|
|
} else {
|
|
double resx = f19;
|
|
printf(" %016llx %s ==> %016llx %016llx",
|
|
u0x, test_group.op,
|
|
*((unsigned long long *)(&res)),
|
|
*((unsigned long long *)(&resx)));
|
|
}
|
|
printf("\n");
|
|
}
|
|
}
|
|
|
|
k++;
|
|
printf( "\n" );
|
|
}
|
|
}
|
|
|
|
static void test_dfp_two_arg_ops(int unused)
|
|
/* Shift instructions: first argument is the DFP source, second argument
|
|
* is 6 bit shift amount.
|
|
*/
|
|
{
|
|
test_func_shift_t func;
|
|
unsigned long long u0, u0x;
|
|
unsigned int shift_by;
|
|
double res, d0, *d0p;
|
|
double d0x, *d0xp;
|
|
unsigned long round_mode;
|
|
int k = 0;
|
|
|
|
u0x = 0;
|
|
d0p = &d0;
|
|
d0xp = &d0x;
|
|
|
|
while ((func = dfp_two_arg_tests[k].test_func)) {
|
|
int i;
|
|
|
|
for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
|
|
/* Do each test with each of the possible rounding modes */
|
|
dfp_test_t test_group = dfp_two_arg_tests[k];
|
|
|
|
printf("\ntest with rounding mode %lu \n", round_mode);
|
|
|
|
/* The set_rounding_mode() uses the global value f14. Call the
|
|
* function before setting up the test for the specific instruction
|
|
* to avoid avoid conflicts using f14.
|
|
*/
|
|
set_rounding_mode(round_mode);
|
|
|
|
for (i = 0; i < test_group.num_tests; i++) {
|
|
|
|
shift_by = test_group.targs[i].frb_idx;
|
|
|
|
if (test_group.precision == LONG_TEST) {
|
|
u0 = dfp64_vals[test_group.targs[i].fra_idx];
|
|
} else {
|
|
u0 = dfp128_vals[test_group.targs[i].fra_idx * 2];
|
|
u0x = dfp128_vals[(test_group.targs[i].fra_idx * 2) + 1];
|
|
}
|
|
|
|
*(unsigned long long *)d0p = u0;
|
|
f14 = d0;
|
|
if (test_group.precision == QUAD_TEST) {
|
|
*(unsigned long long *)d0xp = u0x;
|
|
f15 = d0x;
|
|
}
|
|
|
|
(*func)(shift_by);
|
|
res = f18;
|
|
|
|
printf("%s %016llx", test_group.name, u0);
|
|
|
|
if (test_group.precision) {
|
|
printf(" %s %-3d => %016llx",
|
|
test_group.op, shift_by, *((unsigned long long *)(&res)));
|
|
} else {
|
|
double resx = f19;
|
|
printf(" %016llx %s %-3d ==> %016llx %016llx",
|
|
u0x, test_group.op, shift_by,
|
|
*((unsigned long long *)(&res)),
|
|
*((unsigned long long *)(&resx)));
|
|
}
|
|
printf("\n" );
|
|
}
|
|
}
|
|
|
|
k++;
|
|
printf( "\n" );
|
|
}
|
|
}
|
|
|
|
static void test_dcffix_dcffixq(int has_vsx)
|
|
{
|
|
test_func_t func;
|
|
unsigned long long u0;
|
|
double res, d0, *d0p;
|
|
int k = 0, round_mode;
|
|
|
|
d0p = &d0;
|
|
|
|
|
|
while ((func = dfp_dcffix_dcffixq_tests[k].test_func)) {
|
|
int i;
|
|
|
|
if ((!has_vsx) && (!strcmp("dcffix", dfp_dcffix_dcffixq_tests[k].name))) {
|
|
k++;
|
|
/* The test instruction is dcffix it is supported on POWER 7
|
|
* and newer processors. Skip if not POWER 7 or newer.
|
|
*/
|
|
continue;
|
|
}
|
|
|
|
for (round_mode = 0; round_mode < NUM_RND_MODES; round_mode++) {
|
|
/* Do each test with each of the possible rounding modes */
|
|
dfp_test_t test_group = dfp_dcffix_dcffixq_tests[k];
|
|
|
|
printf("\ntest with rounding mode %u \n", round_mode);
|
|
|
|
/* The set_rounding_mode() uses the global value f14. Call the
|
|
* function before setting up the test for the specific instruction
|
|
* to avoid avoid conflicts using f14.
|
|
*/
|
|
set_rounding_mode(round_mode);
|
|
|
|
for (i = 0; i < test_group.num_tests; i++) {
|
|
|
|
/* The instructions take I64 inputs */
|
|
u0 = int64_vals[test_group.targs[i].fra_idx];
|
|
|
|
*(unsigned long long *)d0p = u0;
|
|
f14 = d0;
|
|
|
|
(*func)();
|
|
res = f18;
|
|
|
|
printf("%s %016llx", test_group.name, u0);
|
|
|
|
if (test_group.precision) {
|
|
printf(" %s => %016llx",
|
|
test_group.op, *((unsigned long long *)(&res)));
|
|
} else {
|
|
double resx = f19;
|
|
printf(" %s ==> %016llx %016llx",
|
|
test_group.op,
|
|
*((unsigned long long *)(&res)),
|
|
*((unsigned long long *)(&resx)));
|
|
}
|
|
printf("\n" );
|
|
}
|
|
}
|
|
|
|
k++;
|
|
printf( "\n" );
|
|
}
|
|
}
|
|
|
|
static test_table_t
|
|
all_tests[] =
|
|
{
|
|
{ &test_dfp_one_arg_ops,
|
|
"Test DFP fomat conversion instructions" },
|
|
{ &test_dfp_two_arg_ops,
|
|
"Test DFP shift instructions" },
|
|
{ test_dcffix_dcffixq,
|
|
"Test DCFFIX and DCFFIXQ instructions" },
|
|
{ NULL, NULL }
|
|
};
|
|
#endif // HAS_DFP
|
|
|
|
int main(int argc, char ** argv, char ** envp) {
|
|
#if defined(HAS_DFP)
|
|
test_table_t aTest;
|
|
test_func_t func;
|
|
int i = 0, has_vsx;
|
|
|
|
/* If the processor has the VSX functionality then it is POWER 7
|
|
* or newer.
|
|
*/
|
|
my_envp = envp;
|
|
has_vsx = get_vsx();
|
|
|
|
while ((func = all_tests[i].test_category)) {
|
|
aTest = all_tests[i];
|
|
printf( "%s\n", aTest.name );
|
|
(*func)(has_vsx);
|
|
i++;
|
|
}
|
|
|
|
#endif // HAS_DFP
|
|
return 0;
|
|
}
|