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https://github.com/ioacademy-jikim/debugging
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57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
#ifndef OPCODES_H
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#define OPCODES_H
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/* (Along the lines of ../s390x/opcodes.h) Macro definitions to hand-assemble
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* instructions known to cause problems with assemblers or across assembler
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* versions.
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*
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* Notes:
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*
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* 0. Offsets used in encodings are in Valgrind (Right to Left) ordering.
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* 1. Use register numbers, not register names in macro invocations.
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* 2. Insert the definitions for a new instruction/instruction format in
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* the order of the appearance of its definition in the Power ISA.
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*/
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/* Instruction formats:
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*/
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/* Power ISA Version 2.07 (May 3, 2013). pp. 15: X-FORM */
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#define X20_ASM_DIRECTIVE ".long"
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#define X20_OPCODE_OFFSET "26"
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#define X20_TH_OFFSET "21"
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#define X20_RA_OFFSET "16"
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#define X20_RB_OFFSET "11"
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#define X20_XO_OFFSET "1"
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#define X20_RES_OFFSET "0"
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#define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
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X20_ASM_DIRECTIVE " " \
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"(" #OPCODE "<<" X20_OPCODE_OFFSET ")" "+" \
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"(" #TH "<<" X20_TH_OFFSET ")" "+" \
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"(" #RA "<<" X20_RA_OFFSET ")" "+" \
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"(" #RB "<<" X20_RB_OFFSET ")" "+" \
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"(" #XO "<<" X20_XO_OFFSET ")" "+" \
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"(" #RES "<<" X20_RES_OFFSET ")"
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#define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
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/* Instruction specifics:
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*/
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/* Power ISA Version 2.07 (May 3, 2013). pp. 770: dcbt (Category: Server Syntax) */
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#define DCBT_OPCODE 31
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#define DCBT_XO 278
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#define DCBT_RES 0
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#define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
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#define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
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/* Power ISA Version 2.07 (May 3, 2013). pp. 771: dcbtst (Category: Server Syntax) */
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#define DCBTST_OPCODE 31
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#define DCBTST_XO 246
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#define DCBTST_RES 0
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#define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES)
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#define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH))
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#endif /* OPCODES_H */
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