mirror of
https://github.com/ioacademy-jikim/debugging
synced 2025-06-08 16:36:21 +00:00
206 lines
9.4 KiB
C
206 lines
9.4 KiB
C
#include <stdio.h>
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#include "const.h"
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#include "macro_int.h"
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typedef enum {
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DROTR=0, DROTR32, DROTRV, DSLL,
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DSLL32, DSLLV, DSRA, DSRA32,
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DSRAV, DSRL, DSRL32, DSRLV,
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ROTR, ROTRV, SLL, SLLV,
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SRA, SRAV, SRL, SRLV
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} logical_op;
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int main()
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{
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logical_op op;
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int i;
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init_reg_val2();
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for (op = DROTR; op <= SRLV; op++) {
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for (i = 0; i < N; i++) {
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switch(op) {
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case DROTR:
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/* Release 2 Only */
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#if (__mips == 64) && (__mips_isa_rev >= 2)
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TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("drotr $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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#endif
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break;
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case DROTR32:
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/* Release 2 Only */
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#if (__mips == 64) && (__mips_isa_rev >= 2)
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TEST2("drotr32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("drotr32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("drotr32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("drotr32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("drotr32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("drotr32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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#endif
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break;
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case DROTRV:
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/* Release 2 Only */
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#if (__mips == 64) && (__mips_isa_rev >= 2)
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TEST1("drotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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#endif
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break;
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case DSLL:
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TEST2("dsll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSLL32:
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TEST2("dsll32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsll32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsll32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsll32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsll32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsll32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsll32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsll32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSLLV:
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TEST1("dsllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("dsllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case DSRA:
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TEST2("dsra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsra $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsra $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsra $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsra $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSRA32:
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TEST2("dsra32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsra32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsra32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsra32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsra32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsra32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsra32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsra32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSRAV:
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TEST1("dsrav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case DSRL:
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TEST2("dsrl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsrl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsrl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsrl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsrl $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsrl $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsrl $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsrl $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSRL32:
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TEST2("dsrl32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("dsrl32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("dsrl32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("dsrl32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("dsrl32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("dsrl32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("dsrl32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("dsrl32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case DSRLV:
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TEST1("dsrlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("dsrlv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case ROTR:
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/* Release 2 Only */
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#if (__mips == 64) && (__mips_isa_rev >= 2)
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TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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#endif
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break;
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case ROTRV:
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/* Release 2 Only */
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#if (__mips == 64) && (__mips_isa_rev >= 2)
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TEST1("rotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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#endif
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break;
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case SLL:
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TEST2("sll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("sll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("sll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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TEST2("sll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
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TEST2("sll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
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TEST2("sll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
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TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
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break;
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case SLLV:
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TEST1("sllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("sllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case SRA:
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TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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break;
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case SRAV:
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TEST1("srav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case SRL:
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TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
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TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
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TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
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TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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break;
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case SRLV:
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TEST1("srlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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}
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}
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}
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return 0;
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}
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