mirror of
https://github.com/ioacademy-jikim/debugging
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563 lines
20 KiB
C
563 lines
20 KiB
C
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/*---------------------------------------------------------------*/
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/*--- begin host_tilegx_defs.h ---*/
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/*---------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2010-2015 Tilera Corp.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
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#ifndef __VEX_HOST_TILEGX_DEFS_H
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#define __VEX_HOST_TILEGX_DEFS_H
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#include "tilegx_disasm.h"
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/* Num registers used for function calls */
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#define TILEGX_N_REGPARMS 10
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/* --------- Registers. --------- */
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/* The usual HReg abstraction.
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There are 56 general purpose regs.
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*/
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#define ST_IN static inline
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ST_IN HReg hregTILEGX_R30 ( void ) { return mkHReg(False, HRcInt64, 30, 0); }
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ST_IN HReg hregTILEGX_R31 ( void ) { return mkHReg(False, HRcInt64, 31, 1); }
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ST_IN HReg hregTILEGX_R32 ( void ) { return mkHReg(False, HRcInt64, 32, 2); }
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ST_IN HReg hregTILEGX_R33 ( void ) { return mkHReg(False, HRcInt64, 33, 3); }
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ST_IN HReg hregTILEGX_R34 ( void ) { return mkHReg(False, HRcInt64, 34, 4); }
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ST_IN HReg hregTILEGX_R35 ( void ) { return mkHReg(False, HRcInt64, 35, 5); }
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ST_IN HReg hregTILEGX_R36 ( void ) { return mkHReg(False, HRcInt64, 36, 6); }
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ST_IN HReg hregTILEGX_R37 ( void ) { return mkHReg(False, HRcInt64, 37, 7); }
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ST_IN HReg hregTILEGX_R38 ( void ) { return mkHReg(False, HRcInt64, 38, 8); }
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ST_IN HReg hregTILEGX_R39 ( void ) { return mkHReg(False, HRcInt64, 39, 9); }
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ST_IN HReg hregTILEGX_R40 ( void ) { return mkHReg(False, HRcInt64, 40, 10); }
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ST_IN HReg hregTILEGX_R41 ( void ) { return mkHReg(False, HRcInt64, 41, 11); }
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ST_IN HReg hregTILEGX_R42 ( void ) { return mkHReg(False, HRcInt64, 42, 12); }
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ST_IN HReg hregTILEGX_R43 ( void ) { return mkHReg(False, HRcInt64, 43, 13); }
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ST_IN HReg hregTILEGX_R44 ( void ) { return mkHReg(False, HRcInt64, 44, 14); }
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ST_IN HReg hregTILEGX_R45 ( void ) { return mkHReg(False, HRcInt64, 45, 15); }
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ST_IN HReg hregTILEGX_R46 ( void ) { return mkHReg(False, HRcInt64, 46, 16); }
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ST_IN HReg hregTILEGX_R47 ( void ) { return mkHReg(False, HRcInt64, 47, 17); }
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ST_IN HReg hregTILEGX_R48 ( void ) { return mkHReg(False, HRcInt64, 48, 18); }
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ST_IN HReg hregTILEGX_R49 ( void ) { return mkHReg(False, HRcInt64, 49, 19); }
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ST_IN HReg hregTILEGX_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 20); }
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ST_IN HReg hregTILEGX_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 21); }
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ST_IN HReg hregTILEGX_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 22); }
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ST_IN HReg hregTILEGX_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 23); }
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ST_IN HReg hregTILEGX_R16 ( void ) { return mkHReg(False, HRcInt64, 16, 24); }
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ST_IN HReg hregTILEGX_R17 ( void ) { return mkHReg(False, HRcInt64, 17, 25); }
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ST_IN HReg hregTILEGX_R18 ( void ) { return mkHReg(False, HRcInt64, 18, 26); }
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ST_IN HReg hregTILEGX_R19 ( void ) { return mkHReg(False, HRcInt64, 19, 27); }
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ST_IN HReg hregTILEGX_R20 ( void ) { return mkHReg(False, HRcInt64, 20, 28); }
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ST_IN HReg hregTILEGX_R21 ( void ) { return mkHReg(False, HRcInt64, 21, 29); }
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ST_IN HReg hregTILEGX_R22 ( void ) { return mkHReg(False, HRcInt64, 22, 30); }
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ST_IN HReg hregTILEGX_R23 ( void ) { return mkHReg(False, HRcInt64, 23, 31); }
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ST_IN HReg hregTILEGX_R24 ( void ) { return mkHReg(False, HRcInt64, 24, 32); }
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ST_IN HReg hregTILEGX_R25 ( void ) { return mkHReg(False, HRcInt64, 25, 33); }
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ST_IN HReg hregTILEGX_R26 ( void ) { return mkHReg(False, HRcInt64, 26, 34); }
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ST_IN HReg hregTILEGX_R27 ( void ) { return mkHReg(False, HRcInt64, 27, 35); }
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ST_IN HReg hregTILEGX_R28 ( void ) { return mkHReg(False, HRcInt64, 28, 36); }
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ST_IN HReg hregTILEGX_R29 ( void ) { return mkHReg(False, HRcInt64, 29, 37); }
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ST_IN HReg hregTILEGX_R0 ( void ) { return mkHReg(False, HRcInt64, 0, 38); }
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ST_IN HReg hregTILEGX_R1 ( void ) { return mkHReg(False, HRcInt64, 1, 39); }
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ST_IN HReg hregTILEGX_R2 ( void ) { return mkHReg(False, HRcInt64, 2, 40); }
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ST_IN HReg hregTILEGX_R3 ( void ) { return mkHReg(False, HRcInt64, 3, 41); }
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ST_IN HReg hregTILEGX_R4 ( void ) { return mkHReg(False, HRcInt64, 4, 42); }
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ST_IN HReg hregTILEGX_R5 ( void ) { return mkHReg(False, HRcInt64, 5, 43); }
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ST_IN HReg hregTILEGX_R6 ( void ) { return mkHReg(False, HRcInt64, 6, 44); }
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ST_IN HReg hregTILEGX_R7 ( void ) { return mkHReg(False, HRcInt64, 7, 45); }
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ST_IN HReg hregTILEGX_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 46); }
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ST_IN HReg hregTILEGX_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 47); }
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ST_IN HReg hregTILEGX_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 48); }
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ST_IN HReg hregTILEGX_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 49); }
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ST_IN HReg hregTILEGX_R50 ( void ) { return mkHReg(False, HRcInt64, 50, 50); }
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ST_IN HReg hregTILEGX_R51 ( void ) { return mkHReg(False, HRcInt64, 51, 51); }
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ST_IN HReg hregTILEGX_R52 ( void ) { return mkHReg(False, HRcInt64, 52, 52); }
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ST_IN HReg hregTILEGX_R53 ( void ) { return mkHReg(False, HRcInt64, 53, 53); }
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ST_IN HReg hregTILEGX_R54 ( void ) { return mkHReg(False, HRcInt64, 54, 54); }
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ST_IN HReg hregTILEGX_R55 ( void ) { return mkHReg(False, HRcInt64, 55, 55); }
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ST_IN HReg hregTILEGX_R63 ( void ) { return mkHReg(False, HRcInt64, 63, 56); }
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extern void ppHRegTILEGX ( HReg );
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#define TILEGXGuestStatePointer() hregTILEGX_R50()
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#define TILEGXStackFramePointer() hregTILEGX_R52()
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#define TILEGXLinkRegister() hregTILEGX_R55()
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#define TILEGXStackPointer() hregTILEGX_R54()
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/* r0, r1, r2, r3 ... r9 */
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#define TILEGX_N_ARGREGS 10
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/* --------- Condition codes, Tilegx encoding. --------- */
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typedef enum {
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TILEGXcc_EQ = 0, /* equal */
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TILEGXcc_NE = 1, /* not equal */
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TILEGXcc_HS = 2, /* >=u (higher or same) */
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TILEGXcc_LO = 3, /* <u (lower) */
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TILEGXcc_MI = 4, /* minus (negative) */
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TILEGXcc_PL = 5, /* plus (zero or +ve) */
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TILEGXcc_VS = 6, /* overflow */
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TILEGXcc_VC = 7, /* no overflow */
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TILEGXcc_HI = 8, /* >u (higher) */
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TILEGXcc_LS = 9, /* <=u (lower or same) */
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TILEGXcc_GE = 10, /* >=s (signed greater or equal) */
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TILEGXcc_LT = 11, /* <s (signed less than) */
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TILEGXcc_GT = 12, /* >s (signed greater) */
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TILEGXcc_LE = 13, /* <=s (signed less or equal) */
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TILEGXcc_AL = 14, /* always (unconditional) */
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TILEGXcc_NV = 15, /* never (unconditional): */
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TILEGXcc_EQ8x8 = 16,/* V1 equal */
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TILEGXcc_NE8x8 = 17,/* V1 not equal */
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TILEGXcc_EZ = 18, /* equal 0 */
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TILEGXcc_NZ = 19, /* not equal */
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} TILEGXCondCode;
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/* --------- Memory address expressions (amodes). --------- */
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typedef enum {
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GXam_IR, /* Immediate (signed 16-bit) + Reg */
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} TILEGXAModeTag;
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typedef struct {
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TILEGXAModeTag tag;
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union {
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struct {
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HReg base;
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Int index;
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} IR;
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struct {
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HReg base;
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HReg index;
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} RR;
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} GXam;
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} TILEGXAMode;
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extern TILEGXAMode *TILEGXAMode_IR ( Int, HReg );
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extern TILEGXAMode *TILEGXAMode_RR ( HReg, HReg );
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extern TILEGXAMode *dopyTILEGXAMode ( TILEGXAMode * );
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extern TILEGXAMode *nextTILEGXAModeFloat ( TILEGXAMode * );
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extern TILEGXAMode *nextTILEGXAModeInt ( TILEGXAMode * );
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extern void ppTILEGXAMode ( const TILEGXAMode * );
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/* --------- Operand, which can be a reg or a u16/s16. --------- */
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/* ("RH" == "Register or Halfword immediate") */
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typedef enum {
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GXrh_Imm,
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GXrh_Reg
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} TILEGXRHTag;
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typedef struct {
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TILEGXRHTag tag;
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union {
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struct {
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Bool syned;
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UShort imm16;
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} Imm;
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struct {
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HReg reg;
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} Reg;
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} GXrh;
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} TILEGXRH;
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extern void ppTILEGXRH ( const TILEGXRH * );
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extern TILEGXRH *TILEGXRH_Imm ( Bool, UShort );
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extern TILEGXRH *TILEGXRH_Reg ( HReg );
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/* --------- Reg or imm5 operands --------- */
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typedef enum {
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TILEGXri5_I5 = 7, /* imm5, 1 .. 31 only (no zero!) */
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TILEGXri5_R /* reg */
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} TILEGXRI5Tag;
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typedef struct {
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TILEGXRI5Tag tag;
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union {
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struct {
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UInt imm5;
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} I5;
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struct {
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HReg reg;
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} R;
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} TILEGXri5;
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} TILEGXRI5;
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extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 );
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extern TILEGXRI5 *TILEGXRI5_R ( HReg );
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extern void ppTILEGXRI5 ( const TILEGXRI5 * );
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/* --------- Instructions. --------- */
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/*Tags for operations*/
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/* --------- */
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typedef enum {
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GXun_CLZ,
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GXun_CTZ,
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GXun_NOP,
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} TILEGXUnaryOp;
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/* --------- */
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typedef enum {
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GXalu_INVALID,
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GXalu_ADD,
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GXalu_SUB,
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GXalu_AND,
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GXalu_OR,
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GXalu_NOR,
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GXalu_XOR,
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} TILEGXAluOp;
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/* --------- */
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typedef enum {
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GXshft_INVALID,
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GXshft_SLL,
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GXshft_SRL,
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GXshft_SRA,
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GXshft_SLL8x8,
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GXshft_SRL8x8,
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} TILEGXShftOp;
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/* --------- */
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typedef enum {
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GXbf_EXTS,
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GXbf_EXTU,
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GXbf_INS
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} TILEGXBfOp;
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/* --------- */
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/* --------- */
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typedef enum {
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GXacas_CMPEXCH,
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GXacas_EXCH,
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GXacas_FetchAnd,
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GXacas_FetchAdd,
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GXacas_FetchAddgez,
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GXacas_FetchOr,
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} TILEGXAcasOp;
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/* --------- */
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/* ----- Instruction tags ----- */
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typedef enum {
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GXin_LI, /* load word (32/64-bit) immediate (fake insn) */
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GXin_Alu, /* word add/sub/and/or/xor/nor/others? */
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GXin_Shft, /* word sll/srl/sra */
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GXin_Unary, /* clo, clz, nop, neg */
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GXin_Cmp, /* word compare (fake insn) */
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GXin_CmpI,
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GXin_Mul, /* widening/non-widening multiply */
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GXin_Call, /* call to address in register */
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GXin_XDirect, /* direct transfer to GA */
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GXin_XIndir, /* indirect transfer to GA */
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GXin_XAssisted, /* assisted transfer to GA */
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GXin_EvCheck, /* Event check */
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GXin_ProfInc, /* 64-bit profile counter increment */
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GXin_RdWrLR, /* Read/Write Link Register */
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GXin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
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GXin_Store, /* store a 8|16|32|64 bit value to mem */
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GXin_MovCond,
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GXin_Bf, /* Bitfield operations */
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GXin_Acas, /* Atomic Campare and swap. */
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} TILEGXInstrTag;
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/*--------- Structure for instructions ----------*/
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/* Destinations are on the LEFT (first operand) */
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typedef struct {
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TILEGXInstrTag tag;
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union {
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/* Get a 32/64-bit literal into a register.
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May turn into a number of real insns. */
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struct {
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HReg dst;
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ULong imm;
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} LI;
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/* Integer add/sub/and/or/xor. Limitations:
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- For add, the immediate, if it exists, is a signed 16.
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- For sub, the immediate, if it exists, is a signed 16
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which may not be -32768, since no such instruction
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exists, and so we have to emit addi with +32768, but
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that is not possible.
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- For and/or/xor, the immediate, if it exists,
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is an unsigned 16.
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*/
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struct {
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TILEGXAluOp op;
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HReg dst;
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HReg srcL;
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TILEGXRH *srcR;
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} Alu;
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struct {
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TILEGXBfOp op;
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HReg dst;
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HReg src;
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UInt Start;
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UInt End;
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} Bf;
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struct {
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TILEGXAcasOp op;
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HReg addr;
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HReg exp;
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HReg new;
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HReg old;
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UInt sz;
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} Acas;
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/* Integer shl/shr/sar.
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Limitations: the immediate, if it exists,
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is a signed 5-bit value between 1 and 31 inclusive.
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*/
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struct {
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TILEGXShftOp op;
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Bool sz32;
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HReg dst;
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HReg srcL;
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TILEGXRH *srcR;
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} Shft;
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/* Clz, Ctz, Clo, nop */
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struct {
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TILEGXUnaryOp op;
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HReg dst;
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HReg src;
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} Unary;
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/* Word compare. Fake instruction, used for basic block ending */
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struct {
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Bool syned;
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Bool sz32;
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HReg dst;
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HReg srcL;
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HReg srcR;
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TILEGXCondCode cond;
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} Cmp;
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struct {
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Bool syned;
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Bool sz32;
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HReg dst;
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HReg srcL;
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TILEGXRH *srcR;
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TILEGXCondCode cond;
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} CmpI;
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struct {
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Bool widening; //True => widening, False => non-widening
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Bool syned; //signed/unsigned - meaningless if widenind = False
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Bool sz32;
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HReg dst;
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HReg srcL;
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HReg srcR;
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} Mul;
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/* Pseudo-insn. Call target (an absolute address), on given
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condition (which could be Mcc_ALWAYS). argiregs indicates
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which of r0 .. r9
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carries argument values for this call,
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using a bit mask (1<<N is set if rN holds an arg, for N in
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0 .. 9 inclusive).
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If cond is != Mcc_ALWAYS, src is checked.
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Otherwise, unconditional call */
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struct {
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TILEGXCondCode cond;
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Addr64 target;
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ULong argiregs;
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HReg src;
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RetLoc rloc; /* where the return value saved. */
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} Call;
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/* Update the guest IP value, then exit requesting to chain
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to it. May be conditional. Urr, use of Addr32 implicitly
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assumes that wordsize(guest) == wordsize(host). */
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struct {
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Addr64 dstGA; /* next guest address */
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TILEGXAMode* amPC; /* amode in guest state for PC */
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TILEGXCondCode cond; /* can be TILEGXcc_AL */
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Bool toFastEP; /* chain to the slow or fast point? */
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} XDirect;
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/* Boring transfer to a guest address not known at JIT time.
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Not chainable. May be conditional. */
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struct {
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HReg dstGA;
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TILEGXAMode* amPC;
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TILEGXCondCode cond; /* can be TILEGXcc_AL */
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} XIndir;
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/* Assisted transfer to a guest address, most general case.
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Not chainable. May be conditional. */
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struct {
|
|
HReg dstGA;
|
|
TILEGXAMode* amPC;
|
|
TILEGXCondCode cond; /* can be TILEGXcc_AL */
|
|
IRJumpKind jk;
|
|
} XAssisted;
|
|
|
|
struct {
|
|
TILEGXAMode* amCounter;
|
|
TILEGXAMode* amFailAddr;
|
|
} EvCheck;
|
|
|
|
struct {
|
|
/* No fields. The address of the counter to inc is
|
|
installed later, post-translation, by patching it in,
|
|
as it is not known at translation time. */
|
|
} ProfInc;
|
|
/* Zero extending loads. Dst size is host word size */
|
|
struct {
|
|
UChar sz; /* 1|2|4|8 */
|
|
HReg dst;
|
|
TILEGXAMode *src;
|
|
} Load;
|
|
/* 64/32/16/8 bit stores */
|
|
struct {
|
|
UChar sz; /* 1|2|4|8 */
|
|
TILEGXAMode *dst;
|
|
HReg src;
|
|
} Store;
|
|
/* Read/Write Link Register */
|
|
struct {
|
|
Bool wrLR;
|
|
HReg gpr;
|
|
} RdWrLR;
|
|
struct {
|
|
HReg dst;
|
|
HReg srcL;
|
|
TILEGXRH *srcR;
|
|
HReg condR;
|
|
TILEGXCondCode cond;
|
|
} MovCond;
|
|
} GXin;
|
|
} TILEGXInstr;
|
|
extern TILEGXInstr *TILEGXInstr_LI ( HReg, ULong );
|
|
extern TILEGXInstr *TILEGXInstr_Alu ( TILEGXAluOp, HReg, HReg, TILEGXRH * );
|
|
extern TILEGXInstr *TILEGXInstr_Shft ( TILEGXShftOp, Bool sz32, HReg, HReg,
|
|
TILEGXRH * );
|
|
extern TILEGXInstr *TILEGXInstr_Unary ( TILEGXUnaryOp op, HReg dst, HReg src );
|
|
extern TILEGXInstr *TILEGXInstr_Cmp ( Bool, Bool, HReg, HReg, HReg,
|
|
TILEGXCondCode );
|
|
extern TILEGXInstr *TILEGXInstr_CmpI ( Bool, Bool, HReg, HReg, TILEGXRH *,
|
|
TILEGXCondCode );
|
|
extern TILEGXInstr *TILEGXInstr_Bf ( TILEGXBfOp op, HReg dst, HReg src,
|
|
UInt Start, UInt End );
|
|
extern TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old, HReg addr,
|
|
HReg exp, HReg new, UInt sz );
|
|
extern TILEGXInstr *TILEGXInstr_Mul ( Bool syned, Bool hi32, Bool sz32, HReg,
|
|
HReg, HReg );
|
|
extern TILEGXInstr *TILEGXInstr_Div ( Bool syned, Bool sz32, HReg, HReg );
|
|
extern TILEGXInstr *TILEGXInstr_Madd ( Bool, HReg, HReg );
|
|
extern TILEGXInstr *TILEGXInstr_Msub ( Bool, HReg, HReg );
|
|
|
|
extern TILEGXInstr *TILEGXInstr_Load ( UChar sz, HReg dst, TILEGXAMode * src );
|
|
|
|
extern TILEGXInstr *TILEGXInstr_Store ( UChar sz, TILEGXAMode * dst, HReg src );
|
|
|
|
extern TILEGXInstr *TILEGXInstr_LoadL ( UChar sz, HReg dst, TILEGXAMode * src );
|
|
|
|
extern TILEGXInstr *TILEGXInstr_StoreC ( UChar sz, TILEGXAMode * dst, HReg src );
|
|
|
|
extern TILEGXInstr *TILEGXInstr_Call ( TILEGXCondCode, Addr64, ULong, HReg );
|
|
extern TILEGXInstr *TILEGXInstr_CallAlways ( TILEGXCondCode, Addr64, ULong );
|
|
extern TILEGXInstr *TILEGXInstr_XDirect ( Addr64 dstGA, TILEGXAMode* amPC,
|
|
TILEGXCondCode cond, Bool toFastEP );
|
|
extern TILEGXInstr *TILEGXInstr_XIndir ( HReg dstGA, TILEGXAMode* amPC,
|
|
TILEGXCondCode cond );
|
|
extern TILEGXInstr *TILEGXInstr_XAssisted ( HReg dstGA, TILEGXAMode* amPC,
|
|
TILEGXCondCode cond, IRJumpKind jk );
|
|
extern TILEGXInstr *TILEGXInstr_EvCheck ( TILEGXAMode* amCounter,
|
|
TILEGXAMode* amFailAddr );
|
|
extern TILEGXInstr* TILEGXInstr_ProfInc (void);
|
|
|
|
extern TILEGXInstr *TILEGXInstr_Goto ( IRJumpKind, TILEGXCondCode,
|
|
TILEGXRH * dst, HReg );
|
|
extern TILEGXInstr *TILEGXInstr_GotoAlways ( IRJumpKind, TILEGXRH * );
|
|
extern TILEGXInstr *TILEGXInstr_RdWrLR ( Bool wrLR, HReg gpr );
|
|
extern TILEGXInstr *TILEGXInstr_MovCond ( HReg dst, HReg srcL, TILEGXRH * src,
|
|
HReg condR, TILEGXCondCode cond );
|
|
extern void ppTILEGXInstr ( const TILEGXInstr * );
|
|
|
|
/* Some functions that insulate the register allocator from details
|
|
of the underlying instruction set. */
|
|
extern void getRegUsage_TILEGXInstr ( HRegUsage *, TILEGXInstr *);
|
|
extern void mapRegs_TILEGXInstr ( HRegRemap *, TILEGXInstr *);
|
|
extern Bool isMove_TILEGXInstr ( TILEGXInstr *, HReg *, HReg * );
|
|
extern Int emit_TILEGXInstr ( Bool*, UChar*, Int, TILEGXInstr*, Bool, VexEndness,
|
|
void*, void*, void*, void* );
|
|
extern void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
|
|
HReg rreg, Int offset );
|
|
extern void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
|
|
HReg rreg, Int offset );
|
|
|
|
extern const RRegUniverse* getRRegUniverse_TILEGX ( void );
|
|
|
|
extern HInstrArray *iselSB_TILEGX ( const IRSB*, VexArch,
|
|
const VexArchInfo*,
|
|
const VexAbiInfo*,
|
|
Int, Int, Bool, Bool, Addr);
|
|
extern const HChar *showTILEGXCondCode ( TILEGXCondCode cond );
|
|
extern Int evCheckSzB_TILEGX (void);
|
|
extern VexInvalRange chainXDirect_TILEGX ( VexEndness endness_host,
|
|
void* place_to_chain,
|
|
const void* disp_cp_chain_me_EXPECTED,
|
|
const void* place_to_jump_to,
|
|
Bool mode64 );
|
|
extern VexInvalRange unchainXDirect_TILEGX ( VexEndness endness_host,
|
|
void* place_to_unchain,
|
|
const void* place_to_jump_to_EXPECTED,
|
|
const void* disp_cp_chain_me,
|
|
Bool mode64 );
|
|
extern VexInvalRange patchProfInc_TILEGX ( VexEndness endness_host,
|
|
void* place_to_patch,
|
|
const ULong* location_of_counter,
|
|
Bool mode64 );
|
|
|
|
extern Int decode_and_display ( tilegx_bundle_bits *p, Int count, ULong pc );
|
|
|
|
#endif /* __LIBVEX_HOST_TILEGX_HDEFS_H */
|
|
|
|
/*---------------------------------------------------------------*/
|
|
/*--- end host-tilegx_defs.h ---*/
|
|
/*---------------------------------------------------------------*/
|