mirror of
https://github.com/ioacademy-jikim/debugging
synced 2025-06-08 16:36:21 +00:00
1104 lines
20 KiB
C
1104 lines
20 KiB
C
/*---------------------------------------------------------------*/
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/*--- begin guest_tilegx_helpers.c ---*/
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/*---------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2010-2015 Tilera Corp.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
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#include "libvex_basictypes.h"
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#include "libvex_emnote.h"
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#include "libvex_guest_tilegx.h"
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#include "libvex_ir.h"
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#include "libvex.h"
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#include "main_util.h"
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#include "guest_generic_bb_to_IR.h"
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#include "guest_tilegx_defs.h"
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/* This file contains helper functions for tilegx guest code. Calls to
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these functions are generated by the back end.
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*/
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#define ALWAYSDEFD(field) \
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{ offsetof(VexGuestTILEGXState, field), \
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(sizeof ((VexGuestTILEGXState*)0)->field) }
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IRExpr *guest_tilegx_spechelper ( const HChar * function_name, IRExpr ** args,
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IRStmt ** precedingStmts, Int n_precedingStmts)
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{
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return NULL;
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}
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/* VISIBLE TO LIBVEX CLIENT */
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void LibVEX_GuestTILEGX_initialise ( VexGuestTILEGXState * vex_state )
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{
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vex_state->guest_r0 = 0;
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vex_state->guest_r1 = 0;
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vex_state->guest_r2 = 0;
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vex_state->guest_r3 = 0;
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vex_state->guest_r4 = 0;
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vex_state->guest_r5 = 0;
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vex_state->guest_r6 = 0;
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vex_state->guest_r7 = 0;
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vex_state->guest_r8 = 0;
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vex_state->guest_r9 = 0;
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vex_state->guest_r10 = 0;
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vex_state->guest_r11 = 0;
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vex_state->guest_r12 = 0;
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vex_state->guest_r13 = 0;
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vex_state->guest_r14 = 0;
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vex_state->guest_r15 = 0;
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vex_state->guest_r16 = 0;
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vex_state->guest_r17 = 0;
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vex_state->guest_r18 = 0;
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vex_state->guest_r19 = 0;
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vex_state->guest_r20 = 0;
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vex_state->guest_r21 = 0;
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vex_state->guest_r22 = 0;
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vex_state->guest_r23 = 0;
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vex_state->guest_r24 = 0;
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vex_state->guest_r25 = 0;
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vex_state->guest_r26 = 0;
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vex_state->guest_r27 = 0;
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vex_state->guest_r28 = 0;
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vex_state->guest_r29 = 0;
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vex_state->guest_r30 = 0;
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vex_state->guest_r31 = 0;
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vex_state->guest_r32 = 0;
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vex_state->guest_r33 = 0;
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vex_state->guest_r34 = 0;
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vex_state->guest_r35 = 0;
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vex_state->guest_r36 = 0;
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vex_state->guest_r37 = 0;
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vex_state->guest_r38 = 0;
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vex_state->guest_r39 = 0;
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vex_state->guest_r40 = 0;
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vex_state->guest_r41 = 0;
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vex_state->guest_r42 = 0;
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vex_state->guest_r43 = 0;
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vex_state->guest_r44 = 0;
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vex_state->guest_r45 = 0;
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vex_state->guest_r46 = 0;
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vex_state->guest_r47 = 0;
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vex_state->guest_r48 = 0;
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vex_state->guest_r49 = 0;
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vex_state->guest_r50 = 0;
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vex_state->guest_r51 = 0;
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vex_state->guest_r52 = 0;
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vex_state->guest_r53 = 0;
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vex_state->guest_r54 = 0;
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vex_state->guest_r55 = 0;
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vex_state->guest_pc = 0; /* Program counter */
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vex_state->guest_EMNOTE = 0;
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vex_state->guest_CMSTART = 0;
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/* For clflush: record start and length of area to invalidate */
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vex_state->guest_CMSTART = 0;
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vex_state->guest_CMLEN = 0;
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/* Used to record the unredirected guest address at the start of
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a translation whose start has been redirected. By reading
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this pseudo-register shortly afterwards, the translation can
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find out what the corresponding no-redirection address was.
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Note, this is only set for wrap-style redirects, not for
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replace-style ones. */
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vex_state->guest_NRADDR = 0;
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}
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/*-----------------------------------------------------------*/
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/*--- Describing the tilegx guest state, for the benefit ---*/
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/*--- of iropt and instrumenters. ---*/
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/*-----------------------------------------------------------*/
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/* Figure out if any part of the guest state contained in minoff
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.. maxoff requires precise memory exceptions. If in doubt return
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True (but this is generates significantly slower code).
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We enforce precise exns for guest SP, PC.
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*/
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Bool guest_tilegx_state_requires_precise_mem_exns (
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Int minoff, Int maxoff,
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VexRegisterUpdates pxControl)
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{
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Int sp_min = offsetof(VexGuestTILEGXState, guest_r54);
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Int sp_max = sp_min + 8 - 1;
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Int pc_min = offsetof(VexGuestTILEGXState, guest_pc);
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Int pc_max = pc_min + 8 - 1;
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if (maxoff < sp_min || minoff > sp_max) {
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/* no overlap with sp */
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if (pxControl == VexRegUpdSpAtMemAccess)
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return False; /* We only need to check stack pointer. */
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} else {
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return True;
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}
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if (maxoff < pc_min || minoff > pc_max) {
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/* no overlap with pc */
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} else {
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return True;
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}
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/* We appear to need precise updates of R52 in order to get proper
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stacktraces from non-optimised code. */
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Int fp_min = offsetof(VexGuestTILEGXState, guest_r52);
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Int fp_max = fp_min + 8 - 1;
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if (maxoff < fp_min || minoff > fp_max) {
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/* no overlap with fp */
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} else {
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return True;
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}
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return False;
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}
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VexGuestLayout tilegxGuest_layout = {
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/* Total size of the guest state, in bytes. */
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.total_sizeB = sizeof(VexGuestTILEGXState),
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/* Describe the stack pointer. */
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.offset_SP = offsetof(VexGuestTILEGXState, guest_r54),
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.sizeof_SP = 8,
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/* Describe the frame pointer. */
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.offset_FP = offsetof(VexGuestTILEGXState, guest_r52),
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.sizeof_FP = 8,
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/* Describe the instruction pointer. */
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.offset_IP = offsetof(VexGuestTILEGXState, guest_pc),
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.sizeof_IP = 8,
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/* Describe any sections to be regarded by Memcheck as
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'always-defined'. */
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.n_alwaysDefd = 8,
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/* ? :( */
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.alwaysDefd = {
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/* 0 */ ALWAYSDEFD(guest_r0),
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/* 1 */ ALWAYSDEFD(guest_r1),
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/* 2 */ ALWAYSDEFD(guest_EMNOTE),
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/* 3 */ ALWAYSDEFD(guest_CMSTART),
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/* 4 */ ALWAYSDEFD(guest_CMLEN),
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/* 5 */ ALWAYSDEFD(guest_r52),
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/* 6 */ ALWAYSDEFD(guest_r55),
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/* 7 */ ALWAYSDEFD(guest_pc),
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}
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};
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#ifdef __tilegx__
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ULong tilegx_dirtyhelper_gen ( ULong opc,
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ULong rd0, ULong rd1,
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ULong rd2, ULong rd3)
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{
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switch (opc)
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{
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case 0:
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{
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/* break point */
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switch (rd0) {
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case 0x286a44ae90048fffULL:
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asm (" bpt ");
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break;
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default:
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vex_printf("unhandled \"bpt\": cins=%016llx\n", rd0);
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vassert(0);
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return 0;
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}
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}
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break;
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case 28:
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{
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return __insn_addxsc(rd1, rd2);
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}
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break;
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case 150:
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{
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__insn_mf();
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return 0;
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}
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break;
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case 152: /* mm rd, ra, imm0, imm1 */
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{
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ULong mask;
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if( rd2 <= rd3)
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mask = (-1ULL << rd2) ^ ((-1ULL << rd3) << 1);
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else
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mask = (-1ULL << rd2) | (-1ULL >> (63 - rd3));
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return (rd0 & mask) | (rd1 & (-1ULL ^ mask));
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}
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break;
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case 154: /* mtspr imm, ra */
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{
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switch(rd0)
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{
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case 0x2785:
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__insn_mtspr(0x2785, rd1);
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break;
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case 0x2780:
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__insn_mtspr(0x2780, rd1);
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break;
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case 0x2708:
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__insn_mtspr(0x2708, rd1);
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break;
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case 0x2580:
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__insn_mtspr(0x2580, rd1);
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break;
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case 0x2581:
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__insn_mtspr(0x2581, rd1);
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break;
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case 0x2709: // PASS
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__insn_mtspr(0x2709, rd1);
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break;
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case 0x2707: // FAIL
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__insn_mtspr(0x2707, rd1);
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break;
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case 0x2705: // DONE
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__insn_mtspr(0x2705, rd1);
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break;
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case 0x2870: //
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default:
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vex_printf("opc=%d rd0=%llx rd1=%llx\n",
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(int)opc, rd0, rd1);
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vassert(0);
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}
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}
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break;
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case 151: /* mfspr rd, imm */
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{
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switch(rd1)
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{
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case 0x2785: // SIM_CTRL
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return __insn_mfspr(0x2785);
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break;
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case 0x2708: // ICS
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return __insn_mfspr(0x2708);
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break;
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case 0x2780: // CMPEXCH_VALUE
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return __insn_mfspr(0x2780);
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break;
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case 0x2781: // CYCLE
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return __insn_mfspr(0x2781);
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break;
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case 0x2709: // PASS
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return __insn_mfspr(0x2709);
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break;
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case 0x2707: // FAIL
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return __insn_mfspr(0x2707);
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break;
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case 0x2705: // DONE
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return __insn_mfspr(0x2705);
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break;
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case 0x2580: // EX_CONTEXT_0
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return __insn_mfspr(0x2580);
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break;
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case 0x2581: // EX_CONTEXT_1
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return __insn_mfspr(0x2581);
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break;
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default:
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vex_printf("opc=%d rd0=%llx rd1=%llx\n",
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(int)opc, rd0, rd1);
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vassert(0);
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}
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}
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break;
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case 183:
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{
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return __insn_pcnt(rd1);
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}
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break;
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case 184:
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{
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return __insn_revbits(rd1);
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}
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break;
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case 185: /* revbytes rd, ra */
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{
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return __insn_revbytes(rd1);
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}
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break;
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case 102:
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return __insn_fsingle_add1(rd1, rd2);
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break;
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case 103:
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return __insn_fsingle_addsub2(rd0, rd1, rd2);
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break;
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case 104:
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return __insn_fsingle_mul1(rd1, rd2);
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break;
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case 105:
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return __insn_fsingle_mul2(rd1, rd2);
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break;
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case 106:
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return __insn_fsingle_pack1(rd1);
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break;
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case 107:
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return __insn_fsingle_pack2(rd1, rd2);
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break;
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case 108:
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return __insn_fsingle_sub1(rd1, rd2);
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break;
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case 21:
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switch (rd0) {
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case 0x286a44ae90048fffULL:
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asm ("{ moveli zero, 72 ; raise }");
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break;
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default:
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vex_printf("unhandled \"raise\": cins=%016llx\n", rd0);
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__insn_ill();
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return 0;
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}
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break;
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case 64:
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{
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return __insn_cmul(rd1, rd2);
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}
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break;
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case 65:
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{
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return __insn_cmula(rd0, rd1, rd2);
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}
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break;
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case 66:
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{
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return __insn_cmulaf(rd0, rd1, rd2);
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}
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break;
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case 67:
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{
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return __insn_cmulf(rd1, rd2);
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}
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break;
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case 68:
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{
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return __insn_cmulfr(rd1, rd2);
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}
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break;
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case 69:
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{
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return __insn_cmulh(rd1, rd2);
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}
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break;
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case 70:
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{
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return __insn_cmulhr(rd1, rd2);
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}
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break;
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case 71:
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{
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return __insn_crc32_32(rd1, rd2);
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}
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break;
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case 72:
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{
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return __insn_crc32_8(rd1, rd2);
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}
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break;
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case 75:
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{
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return __insn_dblalign2(rd1, rd2);
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}
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break;
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case 76:
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{
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return __insn_dblalign4(rd1, rd2);
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}
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break;
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case 77:
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{
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return __insn_dblalign6(rd1, rd2);
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}
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break;
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case 78:
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{
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__insn_drain();
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return 0;
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}
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break;
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case 79:
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{
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__insn_dtlbpr(rd0);
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return 0;
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}
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break;
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case 82:
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{
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return __insn_fdouble_add_flags(rd1, rd2);
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}
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break;
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case 83:
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{
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return __insn_fdouble_addsub(rd0, rd1, rd2);
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}
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break;
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case 84:
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{
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return __insn_fdouble_mul_flags(rd1, rd2);
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}
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break;
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case 85:
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{
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return __insn_fdouble_pack1(rd1, rd2);
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}
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break;
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case 86:
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{
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return __insn_fdouble_pack2(rd0, rd1, rd2);
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}
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break;
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case 87:
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{
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return __insn_fdouble_sub_flags(rd1, rd2);
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}
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break;
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|
case 88:
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|
{
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return __insn_fdouble_unpack_max(rd1, rd2);
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}
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break;
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|
case 89:
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|
{
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return __insn_fdouble_unpack_min(rd1, rd2);
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}
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break;
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|
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|
case 98:
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{
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__insn_finv(rd0);
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return 0;
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}
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break;
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|
case 99:
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{
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__insn_flush(rd0);
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return 0;
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}
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break;
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|
case 100:
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{
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__insn_flushwb();
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return 0;
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}
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break;
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|
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|
case 109:
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{
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__insn_icoh((ULong *)rd0);
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return 0;
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}
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break;
|
|
case 110:
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{
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__insn_ill();
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}
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break;
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|
case 111:
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{
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__insn_inv((ULong *)rd0);
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return 0;
|
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}
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break;
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|
|
|
case 169:
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|
{
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return __insn_mula_hu_hu(rd0, rd1, rd2);
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}
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break;
|
|
case 170:
|
|
{
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return __insn_mula_hu_ls(rd0, rd1, rd2);
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|
}
|
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break;
|
|
case 205:
|
|
{
|
|
return __insn_shufflebytes(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 224:
|
|
{
|
|
return __insn_subxsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 229:
|
|
{
|
|
return __insn_tblidxb0(rd0, rd1);
|
|
}
|
|
break;
|
|
case 230:
|
|
{
|
|
return __insn_tblidxb1(rd0, rd1);
|
|
}
|
|
break;
|
|
case 231:
|
|
{
|
|
return __insn_tblidxb2(rd0, rd1);
|
|
}
|
|
break;
|
|
case 232:
|
|
{
|
|
return __insn_tblidxb3(rd0, rd1);
|
|
}
|
|
break;
|
|
case 233:
|
|
{
|
|
return __insn_v1add(rd1, rd2);
|
|
}
|
|
break;
|
|
case 234:
|
|
{
|
|
return __insn_v1add(rd1, rd2);
|
|
}
|
|
break;
|
|
case 235:
|
|
{
|
|
return __insn_v1adduc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 236:
|
|
{
|
|
return __insn_v1adiffu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 237:
|
|
{
|
|
return __insn_v1avgu(rd1, rd2);
|
|
}
|
|
break;
|
|
|
|
case 238:
|
|
{
|
|
return __insn_v1cmpeq(rd1, rd2);
|
|
}
|
|
break;
|
|
case 239:
|
|
{
|
|
return __insn_v1cmpeq(rd1, rd2);
|
|
}
|
|
break;
|
|
case 240:
|
|
{
|
|
return __insn_v1cmples(rd1, rd2);
|
|
}
|
|
break;
|
|
case 241:
|
|
{
|
|
return __insn_v1cmpleu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 242:
|
|
{
|
|
return __insn_v1cmplts(rd1, rd2);
|
|
}
|
|
break;
|
|
case 243:
|
|
{
|
|
return __insn_v1cmplts(rd1, rd2);
|
|
}
|
|
break;
|
|
case 244:
|
|
{
|
|
return __insn_v1cmpltu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 245:
|
|
{
|
|
return __insn_v1cmpltu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 246:
|
|
{
|
|
return __insn_v1cmpne(rd1, rd2);
|
|
}
|
|
break;
|
|
case 247:
|
|
{
|
|
return __insn_v1ddotpu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 248:
|
|
{
|
|
return __insn_v1ddotpua(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 249:
|
|
{
|
|
return __insn_v1ddotpus(rd1, rd2);
|
|
}
|
|
break;
|
|
case 250:
|
|
{
|
|
return __insn_v1ddotpusa(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 251:
|
|
{
|
|
return __insn_v1dotp(rd1, rd2);
|
|
}
|
|
break;
|
|
case 252:
|
|
{
|
|
return __insn_v1dotpa(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 253:
|
|
{
|
|
return __insn_v1dotpu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 254:
|
|
{
|
|
return __insn_v1dotpua(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 255:
|
|
{
|
|
return __insn_v1dotpus(rd1, rd2);
|
|
}
|
|
break;
|
|
case 256:
|
|
{
|
|
return __insn_v1dotpusa(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 257:
|
|
{
|
|
return __insn_v1int_h(rd1, rd2);
|
|
}
|
|
break;
|
|
case 258:
|
|
{
|
|
return __insn_v1int_l(rd1, rd2);
|
|
}
|
|
break;
|
|
case 259:
|
|
{
|
|
return __insn_v1maxu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 260:
|
|
{
|
|
return __insn_v1maxu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 261:
|
|
{
|
|
return __insn_v1minu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 262:
|
|
{
|
|
return __insn_v1minu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 263:
|
|
{
|
|
return __insn_v1mnz(rd1, rd2);
|
|
}
|
|
break;
|
|
case 264:
|
|
{
|
|
return __insn_v1multu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 265:
|
|
{
|
|
return __insn_v1mulu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 266:
|
|
{
|
|
return __insn_v1mulus(rd1, rd2);
|
|
}
|
|
break;
|
|
case 267:
|
|
{
|
|
return __insn_v1mz(rd1, rd2);
|
|
}
|
|
break;
|
|
case 268:
|
|
{
|
|
return __insn_v1sadau(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 269:
|
|
{
|
|
return __insn_v1sadu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 270:
|
|
{
|
|
return __insn_v1shl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 271:
|
|
{
|
|
return __insn_v1shl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 272:
|
|
{
|
|
return __insn_v1shrs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 273:
|
|
{
|
|
return __insn_v1shrs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 274:
|
|
{
|
|
return __insn_v1shru(rd1, rd2);
|
|
}
|
|
break;
|
|
case 275:
|
|
{
|
|
return __insn_v1shrui(rd1, rd2);
|
|
}
|
|
break;
|
|
case 276:
|
|
{
|
|
return __insn_v1sub(rd1, rd2);
|
|
}
|
|
break;
|
|
case 277:
|
|
{
|
|
return __insn_v1subuc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 278:
|
|
{
|
|
return __insn_v2add(rd1, rd2);
|
|
}
|
|
break;
|
|
case 279:
|
|
{
|
|
return __insn_v2add(rd1, rd2);
|
|
}
|
|
break;
|
|
case 280:
|
|
{
|
|
return __insn_v2addsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 281:
|
|
{
|
|
return __insn_v2adiffs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 282:
|
|
{
|
|
return __insn_v2avgs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 283:
|
|
{
|
|
return __insn_v2cmpeq(rd1, rd2);
|
|
}
|
|
break;
|
|
case 284:
|
|
{
|
|
return __insn_v2cmpeq(rd1, rd2);
|
|
}
|
|
break;
|
|
case 285:
|
|
{
|
|
return __insn_v2cmples(rd1, rd2);
|
|
}
|
|
break;
|
|
case 286:
|
|
{
|
|
return __insn_v2cmpleu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 287:
|
|
{
|
|
return __insn_v2cmplts(rd1, rd2);
|
|
}
|
|
break;
|
|
case 288:
|
|
{
|
|
return __insn_v2cmplts(rd1, rd2);
|
|
}
|
|
break;
|
|
case 289:
|
|
{
|
|
return __insn_v2cmpltu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 290:
|
|
{
|
|
return __insn_v2cmpltu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 291:
|
|
{
|
|
return __insn_v2cmpne(rd1, rd2);
|
|
}
|
|
break;
|
|
case 292:
|
|
{
|
|
return __insn_v2dotp(rd1, rd2);
|
|
}
|
|
break;
|
|
case 293:
|
|
{
|
|
return __insn_v2dotpa(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 294:
|
|
{
|
|
return __insn_v2int_h(rd1, rd2);
|
|
}
|
|
break;
|
|
case 295:
|
|
{
|
|
return __insn_v2int_l(rd1, rd2);
|
|
}
|
|
break;
|
|
case 296:
|
|
{
|
|
return __insn_v2maxs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 297:
|
|
{
|
|
return __insn_v2maxs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 298:
|
|
{
|
|
return __insn_v2mins(rd1, rd2);
|
|
}
|
|
break;
|
|
case 299:
|
|
{
|
|
return __insn_v2mins(rd1, rd2);
|
|
}
|
|
break;
|
|
case 300:
|
|
{
|
|
return __insn_v2mnz(rd1, rd2);
|
|
}
|
|
break;
|
|
case 301:
|
|
{
|
|
return __insn_v2mulfsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 302:
|
|
{
|
|
return __insn_v2muls(rd1, rd2);
|
|
}
|
|
break;
|
|
case 303:
|
|
{
|
|
return __insn_v2mults(rd1, rd2);
|
|
}
|
|
break;
|
|
case 304:
|
|
{
|
|
return __insn_v2mz(rd1, rd2);
|
|
}
|
|
break;
|
|
case 305:
|
|
{
|
|
return __insn_v2packh(rd1, rd2);
|
|
}
|
|
break;
|
|
case 306:
|
|
{
|
|
return __insn_v2packl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 307:
|
|
{
|
|
return __insn_v2packuc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 308:
|
|
{
|
|
return __insn_v2sadas(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 309:
|
|
{
|
|
return __insn_v2sadau(rd0, rd1, rd2);
|
|
}
|
|
break;
|
|
case 310:
|
|
{
|
|
return __insn_v2sads(rd1, rd2);
|
|
}
|
|
break;
|
|
case 311:
|
|
{
|
|
return __insn_v2sadu(rd1, rd2);
|
|
}
|
|
break;
|
|
case 312:
|
|
{
|
|
return __insn_v2shl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 313:
|
|
{
|
|
return __insn_v2shl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 314:
|
|
{
|
|
return __insn_v2shlsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 315:
|
|
{
|
|
return __insn_v2shrs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 316:
|
|
{
|
|
return __insn_v2shrs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 317:
|
|
{
|
|
return __insn_v2shru(rd1, rd2);
|
|
}
|
|
break;
|
|
case 318:
|
|
{
|
|
return __insn_v2shru(rd1, rd2);
|
|
}
|
|
break;
|
|
case 319:
|
|
{
|
|
return __insn_v2sub(rd1, rd2);
|
|
}
|
|
break;
|
|
case 320:
|
|
{
|
|
return __insn_v2subsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 321:
|
|
{
|
|
return __insn_v4add(rd1, rd2);
|
|
}
|
|
break;
|
|
case 322:
|
|
{
|
|
return __insn_v4addsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 323:
|
|
{
|
|
return __insn_v4int_h(rd1, rd2);
|
|
}
|
|
break;
|
|
case 324:
|
|
{
|
|
return __insn_v4int_l(rd1, rd2);
|
|
}
|
|
break;
|
|
case 325:
|
|
{
|
|
return __insn_v4packsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 326:
|
|
{
|
|
return __insn_v4shl(rd1, rd2);
|
|
}
|
|
break;
|
|
case 327:
|
|
{
|
|
return __insn_v4shlsc(rd1, rd2);
|
|
}
|
|
break;
|
|
case 328:
|
|
{
|
|
return __insn_v4shrs(rd1, rd2);
|
|
}
|
|
break;
|
|
case 329:
|
|
{
|
|
return __insn_v4shru(rd1, rd2);
|
|
}
|
|
break;
|
|
case 330:
|
|
{
|
|
return __insn_v4sub(rd1, rd2);
|
|
}
|
|
break;
|
|
case 331:
|
|
{
|
|
return __insn_v4subsc(rd1, rd2);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
vex_printf("opc=%d rd0=%llx rd1=%llx\n",
|
|
(int)opc, rd0, rd1);
|
|
vassert(0);
|
|
}
|
|
}
|
|
#else
|
|
ULong tilegx_dirtyhelper_gen ( ULong opc,
|
|
ULong rd0, ULong rd1,
|
|
ULong rd2, ULong rd3 )
|
|
{
|
|
vex_printf("NOT a TILEGX platform");
|
|
return 0;
|
|
}
|
|
#endif /* __tilegx__ */
|
|
|
|
/*---------------------------------------------------------------*/
|
|
/*--- end guest_tilegx_helpers.c ---*/
|
|
/*---------------------------------------------------------------*/
|