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mirror of https://github.com/ioacademy-jikim/debugging synced 2026-08-30 01:09:34 +00:00

first commit

This commit is contained in:
jikim
2015-12-13 22:34:58 +09:00
commit 0b589c7986
9455 changed files with 4350134 additions and 0 deletions
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# dummy
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# dummy
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# dummy
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# dummy
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# dummy
File diff suppressed because it is too large Load Diff
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include $(top_srcdir)/Makefile.tool-tests.am
dist_noinst_SCRIPTS = filter_stderr
INSN_TESTS = insn_basic insn_mmx insn_sse insn_sse2 insn_fpu
EXTRA_DIST = \
$(addsuffix .stderr.exp,$(INSN_TESTS)) \
$(addsuffix .stdout.exp,$(INSN_TESTS)) \
$(addsuffix .vgtest,$(INSN_TESTS)) \
bt_everything.stderr.exp bt_everything.stdout.exp \
bt_everything.vgtest \
bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \
bug279698.vgtest bug279698.stderr.exp bug279698.stdout.exp \
fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \
insn-bsfl.vgtest insn-bsfl.stdout.exp insn-bsfl.stderr.exp \
insn-pcmpistri.vgtest insn-pcmpistri.stdout.exp insn-pcmpistri.stderr.exp \
insn-pmovmskb.vgtest insn-pmovmskb.stdout.exp insn-pmovmskb.stderr.exp \
more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
sh-mem-vec128-plo-no.vgtest \
sh-mem-vec128-plo-no.stderr.exp \
sh-mem-vec128-plo-no.stdout.exp \
sh-mem-vec128-plo-yes.vgtest \
sh-mem-vec128-plo-yes.stderr.exp \
sh-mem-vec128-plo-yes.stdout.exp \
sh-mem-vec256-plo-no.vgtest \
sh-mem-vec256-plo-no.stderr.exp \
sh-mem-vec256-plo-no.stdout.exp \
sh-mem-vec256-plo-yes.vgtest \
sh-mem-vec256-plo-yes.stderr.exp \
sh-mem-vec256-plo-yes.stdout.exp \
sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
xor-undef-amd64.vgtest \
xsave-avx.vgtest xsave-avx.stdout.exp xsave-avx.stderr.exp
check_PROGRAMS = \
bt_everything \
bug132146 \
bug279698 \
fxsave-amd64 \
insn-bsfl \
insn-pmovmskb \
sh-mem-vec128 \
sse_memory \
xor-undef-amd64
if BUILD_AVX_TESTS
check_PROGRAMS += sh-mem-vec256 xsave-avx
endif
if HAVE_ASM_CONSTRAINT_P
check_PROGRAMS += insn-pcmpistri
endif
# clang 3.5.0 barfs about -mfancy-math-387
if !COMPILER_IS_CLANG
check_PROGRAMS += more_x87_fp
endif
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
AM_CCASFLAGS += @FLAG_M64@
insn_pcmpistri_CFLAGS = $(AM_CFLAGS)
if VGCONF_OS_IS_SOLARIS
insn_pcmpistri_CFLAGS += --std=c99
endif
more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
-mfancy-math-387
more_x87_fp_LDADD = -lm
File diff suppressed because it is too large Load Diff
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#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
typedef unsigned long long int ULong;
typedef unsigned int UInt;
typedef unsigned short UShort;
typedef unsigned char UChar;
typedef signed int Int;
typedef signed short Short;
typedef signed long int Word;
unsigned long myrandom(void)
{
/* Simple multiply-with-carry random generator. */
static unsigned long m_w = 11;
static unsigned long m_z = 13;
m_z = 36969 * (m_z & 65535) + (m_z >> 16);
m_w = 18000 * (m_w & 65535) + (m_w >> 16);
return (m_z << 16) + m_w;
}
/* ------------ MEM, Q ------------ */
ULong btsq_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btsq\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" (bitno));
/* Pretty meaningless to dereference base here, but that's what you
have to do to get a btsl insn which refers to memory starting at
base. */
return res;
}
ULong btrq_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btrq\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" (bitno));
return res;
}
ULong btcq_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btcq\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" (bitno));
return res;
}
ULong btq_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btq\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" (bitno)
: "cc", "memory");
return res;
}
/* ------------ MEM, L ------------ */
ULong btsl_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btsl\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Int)bitno));
/* Pretty meaningless to dereference base here, but that's what you
have to do to get a btsl insn which refers to memory starting at
base. */
return res;
}
ULong btrl_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btrl\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Int)bitno));
return res;
}
ULong btcl_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btcl\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Int)bitno));
return res;
}
ULong btl_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btl\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Int)bitno)
: "cc", "memory");
return res;
}
/* ------------ MEM, W ------------ */
ULong btsw_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btsw\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Short)bitno));
/* Pretty meaningless to dereference base here, but that's what you
have to do to get a btsl insn which refers to memory starting at
base. */
return res;
}
ULong btrw_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btrw\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Short)bitno));
return res;
}
ULong btcw_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btcw\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Short)bitno));
return res;
}
ULong btw_mem ( char* base, Word bitno )
{
UChar res;
__asm__
__volatile__("btw\t%2, %0\n\t"
"setc\t%1"
: "=m" (*base), "=q" (res)
: "r" ((Short)bitno)
: "cc", "memory");
return res;
}
/* ------------ REG, Q ------------ */
ULong btsq_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btsq\t%2, %%rax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" (bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btrq_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btrq\t%2, %%rax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" (bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btcq_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btcq\t%2, %%rax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" (bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btq_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btq\t%2, %%rax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" (bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
/* ------------ REG, L ------------ */
ULong btsl_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btsl\t%2, %%eax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Int)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btrl_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btrl\t%2, %%eax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Int)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btcl_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btcl\t%2, %%eax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Int)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btl_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btl\t%2, %%eax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Int)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
/* ------------ REG, W ------------ */
ULong btsw_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btsw\t%2, %%ax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Short)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btrw_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btrw\t%2, %%ax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Short)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btcw_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btcw\t%2, %%ax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Short)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong btw_reg ( ULong reg_in, Word bitno,
ULong* reg_out_p )
{
UChar res;
ULong reg_out;
__asm__
__volatile__("movq\t%3, %%rax\n\t"
"btw\t%2, %%ax\n\t"
"movq\t%%rax, %1\n\t"
"setc\t%0"
: "=q" (res), "=r" (reg_out)
: "r" ((Short)bitno), "r" (reg_in)
: "cc", "eax");
*reg_out_p = reg_out;
return res;
}
ULong rol1 ( ULong x )
{
return (x << 1) | (x >> 63);
}
int main ( void )
{
UInt n, op;
ULong carrydep, c, res;
char* block;
ULong reg;
Word bitoff;
/*------------------------ MEM-L -----------------------*/
carrydep = 0;
block = calloc(200,1);
block += 100;
/* Valid bit offsets are -800 .. 799 inclusive. */
for (n = 0; n < 10000; n++) {
bitoff = (myrandom() % 1600) - 800;
op = myrandom() % 12;
c = 2;
switch (op) {
case 0: c = btsl_mem(block, bitoff); break;
case 1: c = btrl_mem(block, bitoff); break;
case 2: c = btcl_mem(block, bitoff); break;
case 3: c = btl_mem(block, bitoff); break;
case 4: c = btsq_mem(block, bitoff); break;
case 5: c = btrq_mem(block, bitoff); break;
case 6: c = btcq_mem(block, bitoff); break;
case 7: c = btq_mem(block, bitoff); break;
case 8: c = btsw_mem(block, bitoff); break;
case 9: c = btrw_mem(block, bitoff); break;
case 10: c = btcw_mem(block, bitoff); break;
case 11: c = btw_mem(block, bitoff); break;
default: assert(0);
}
assert(c == 0 || c == 1);
carrydep = c ? (rol1(carrydep) ^ bitoff) : carrydep;
}
/* Compute final result */
block -= 100;
res = 0;
for (n = 0; n < 200; n++) {
UChar ch = block[n];
/* printf("%d ", (int)block[n]); */
res = rol1(res) ^ (UInt)ch;
}
printf("MEM-L: final res 0x%llx, carrydep 0x%llx\n", res, carrydep);
/*------------------------ REG-L -----------------------*/
carrydep = 0;
reg = 0;
for (n = 0; n < 1000; n++) {
bitoff = (myrandom() % 100) - 50;
op = myrandom() % 12;
c = 2;
switch (op) {
case 0: c = btsl_reg(reg, bitoff, &reg); break;
case 1: c = btrl_reg(reg, bitoff, &reg); break;
case 2: c = btcl_reg(reg, bitoff, &reg); break;
case 3: c = btl_reg(reg, bitoff, &reg); break;
case 4: c = btsq_reg(reg, bitoff, &reg); break;
case 5: c = btrq_reg(reg, bitoff, &reg); break;
case 6: c = btcq_reg(reg, bitoff, &reg); break;
case 7: c = btq_reg(reg, bitoff, &reg); break;
case 8: c = btsw_reg(reg, bitoff, &reg); break;
case 9: c = btrw_reg(reg, bitoff, &reg); break;
case 10: c = btcw_reg(reg, bitoff, &reg); break;
case 11: c = btw_reg(reg, bitoff, &reg); break;
default: assert(0);
}
assert(c == 0 || c == 1);
carrydep = c ? (rol1(carrydep) ^ bitoff) : carrydep;
}
printf("REG-L: final res 0x%llx, carrydep 0x%llx\n", reg, carrydep);
block += 100;
/* Just try one of these at once; more than one can cause a
confusing merging of error messages. */
//btsl_mem(block, -800); /* should not complain */
//btsl_mem(block, -801); /* should complain */
//btsl_mem(block, 799); /* should not complain */
//btsl_mem(block, 800); /* should complain */
block -= 100;
free(block);
return 0;
}
@@ -0,0 +1,2 @@
MEM-L: final res 0xf7fadd6c64517c70, carrydep 0x8176a65abd735847
REG-L: final res 0x35c459ff, carrydep 0x5d837ee10c6c390
@@ -0,0 +1,2 @@
prog: bt_everything
vgopts: -q
@@ -0,0 +1,106 @@
#include <stdio.h>
typedef unsigned int UInt;
typedef unsigned long long ULong;
#if defined(__x86_64__)
#define BSWAPQ(_lval) \
do { \
__asm__ __volatile__("bswapq %0" \
: /*out*/ "+r"(_lval) ); \
} while (0)
ULong bswapq ( ULong x )
{
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x); BSWAPQ(x);
BSWAPQ(x);
return x;
}
#endif /* defined(__x86_64__) */
#define BSWAPL(_lval) \
do { \
__asm__ __volatile__("bswapl %0" \
: /*out*/ "+r"(_lval) ); \
} while (0)
UInt bswapl ( UInt x )
{
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x); BSWAPL(x);
BSWAPL(x);
return x;
}
int main ( void )
{
#if defined(__x86_64__)
printf("0x%llx\n", bswapq( 0x8877665544332211ULL ));
#endif
printf("0x%x\n", bswapl( 0x44332211ULL ));
return 0;
}
@@ -0,0 +1,2 @@
0x1122334455667788
0x11223344
@@ -0,0 +1,2 @@
prog: bug132146
vgopts: -q
@@ -0,0 +1,27 @@
/* A very trivial test for undefinedness propagation through
saturating narrowing. Obviously need a much more thorough test.
*/
#include <stdio.h>
#include <assert.h>
#include "../../memcheck.h"
int main()
{
unsigned char data[32], vbits[32];
__asm__ __volatile__
("movdqu (%0), %%xmm0 \n"
"packuswb %%xmm0, %%xmm0 \n"
"movdqu %%xmm0, 16(%0) \n"
::"r"(data)
:"memory","xmm0"
);
unsigned int res =
VALGRIND_GET_VBITS( data, vbits, 32 );
assert(res == 1); /* 1 == success */
int i, j;
for(i=0; i<2; i++) {
for(j=0; j<16; j++)
printf("%02x ", vbits[i*16+j]);
printf("\n");
}
return 0;
}
@@ -0,0 +1,2 @@
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
@@ -0,0 +1,2 @@
prog: bug279698
vgopts: -q
@@ -0,0 +1,3 @@
#! /bin/sh
../filter_stderr "$@"
@@ -0,0 +1,218 @@
#include <config.h>
#include <stdio.h>
#include <stdlib.h>
#include "tests/asm.h"
#include "tests/malloc.h"
#include <string.h>
const unsigned int vec0[4]
= { 0x12345678, 0x11223344, 0x55667788, 0x87654321 };
const unsigned int vec1[4]
= { 0xABCDEF01, 0xAABBCCDD, 0xEEFF0011, 0x10FEDCBA };
const unsigned int vecZ[4]
= { 0, 0, 0, 0 };
__attribute__((noinline))
void do_fxsave ( void* p, int rexw ) {
if (rexw) {
#ifdef HAVE_AS_AMD64_FXSAVE64
asm __volatile__("fxsave64 (%0)" : : "r" (p) : "memory" );
#else
asm __volatile__("rex64/fxsave (%0)" : : "r" (p) : "memory" );
#endif
} else {
asm __volatile__("fxsave (%0)" : : "r" (p) : "memory" );
}
}
__attribute__((noinline))
void do_fxrstor ( void* p, int rexw ) {
if (rexw) {
#ifdef HAVE_AS_AMD64_FXSAVE64
asm __volatile__("fxrstor64 (%0)" : : "r" (p) : "memory" );
#else
asm __volatile__("rex64/fxrstor (%0)" : : "r" (p) : "memory" );
#endif
} else {
asm __volatile__("fxrstor (%0)" : : "r" (p) : "memory" );
}
}
void do_zeroise ( void )
{
asm __volatile__("finit");
asm __volatile__(
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"fldz\n\t"
"finit\n");
#ifndef VGP_amd64_darwin
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm0");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm1");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm2");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm3");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm4");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm5");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm6");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm7");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm8");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm9");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm10");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm11");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm12");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm13");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm14");
asm __volatile__("movups " VG_SYM(vecZ) ", %xmm15");
#else
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm0");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm1");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm2");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm3");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm4");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm5");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm6");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm7");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm8");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm9");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm10");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm11");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm12");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm13");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm14");
asm __volatile__("movups " VG_SYM(vecZ) "(%rip), %xmm15");
#endif
asm __volatile__(
"pushq $0\n\t"
"ldmxcsr 0(%rsp)\n\t"
"addq $8,%rsp\n");
}
/* set up the FP and SSE state, and then dump it. */
void do_setup_then_fxsave ( void* p, int rexw )
{
asm __volatile__("finit");
asm __volatile__("fldpi");
asm __volatile__("fld1");
asm __volatile__("fldln2");
asm __volatile__("fldlg2");
asm __volatile__("fld %st(3)");
asm __volatile__("fld %st(3)");
asm __volatile__("fld1");
asm __volatile__("movups (%0), %%xmm0" : : "r"(&vec0[0]) : "xmm0" );
asm __volatile__("movups (%0), %%xmm1" : : "r"(&vec1[0]) : "xmm1" );
asm __volatile__("xorps %xmm2, %xmm2");
asm __volatile__("movaps %xmm0, %xmm3");
asm __volatile__("movaps %xmm1, %xmm4");
asm __volatile__("movaps %xmm2, %xmm5");
asm __volatile__("movaps %xmm0, %xmm6");
asm __volatile__("movaps %xmm1, %xmm7");
asm __volatile__("movaps %xmm1, %xmm8");
asm __volatile__("movaps %xmm2, %xmm9");
asm __volatile__("movaps %xmm0, %xmm10");
asm __volatile__("movaps %xmm1, %xmm11");
asm __volatile__("movaps %xmm1, %xmm12");
asm __volatile__("movaps %xmm2, %xmm13");
asm __volatile__("movaps %xmm0, %xmm14");
asm __volatile__("movaps %xmm1, %xmm15");
do_fxsave(p, rexw);
}
int isFPLsbs ( int i )
{
int q;
q = 32; if (i == q || i == q+1) return 1;
q = 48; if (i == q || i == q+1) return 1;
q = 64; if (i == q || i == q+1) return 1;
q = 80; if (i == q || i == q+1) return 1;
q = 96; if (i == q || i == q+1) return 1;
q = 112; if (i == q || i == q+1) return 1;
q = 128; if (i == q || i == q+1) return 1;
q = 144; if (i == q || i == q+1) return 1;
return 0;
}
void show ( unsigned char* buf, int xx )
{
int i;
for (i = 0; i < 512; i++) {
if ((i % 16) == 0)
printf("%3d ", i);
if (xx && isFPLsbs(i))
printf("xx ");
else
printf("%02x ", buf[i]);
if (i > 0 && ((i % 16) == 15))
printf("\n");
}
}
int main ( int argc, char** argv )
{
unsigned char* buf1 = memalign16(512);
unsigned char* buf2 = memalign16(512);
unsigned char* buf3 = memalign16(512);
int xx = argc > 1;
printf("Re-run with any arg to suppress least-significant\n"
" 16 bits of FP numbers\n");
printf("\n-------- FXSAVE non-64 (REX.W == 0) --------\n");
memset(buf1, 0x55, 512);
memset(buf2, 0x55, 512);
memset(buf3, 0x55, 512);
/* Load up x87/xmm state and dump it. */
do_setup_then_fxsave(buf1, 0);
printf("\nBEFORE\n");
show(buf1, xx);
/* Zeroise x87/xmm state and dump it, to show that the
regs have been cleared out. */
do_zeroise();
do_fxsave(buf2, 0);
printf("\nZEROED\n");
show(buf2, xx);
/* Reload x87/xmm state from buf1 and dump it in buf3. */
do_fxrstor(buf1, 0);
do_fxsave(buf3, 0);
printf("\nRESTORED\n");
show(buf3, xx);
printf("\n-------- FXSAVE 64 (REX.W == 1) --------\n\n");
memset(buf1, 0x55, 512);
memset(buf2, 0x55, 512);
memset(buf3, 0x55, 512);
/* Load up x87/xmm state and dump it. */
do_setup_then_fxsave(buf1, 1);
printf("\nBEFORE\n");
show(buf1, xx);
/* Zeroise x87/xmm state and dump it, to show that the
regs have been cleared out. */
do_zeroise();
do_fxsave(buf2, 1);
printf("\nZEROED\n");
show(buf2, xx);
/* Reload x87/xmm state from buf1 and dump it in buf3. */
do_fxrstor(buf1, 1);
do_fxsave(buf3, 1);
printf("\nRESTORED\n");
show(buf3, xx);
free(buf1); free(buf2); free(buf3);
return 0;
}
@@ -0,0 +1,211 @@
Re-run with any arg to suppress least-significant
16 bits of FP numbers
-------- FXSAVE non-64 (REX.W == 0) --------
BEFORE
0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
ZEROED
0 7f 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
64 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
96 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
128 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
176 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
224 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
272 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
288 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
336 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
352 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
RESTORED
0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
-------- FXSAVE 64 (REX.W == 1) --------
BEFORE
0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
ZEROED
0 7f 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
64 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
96 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
128 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
176 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
224 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
272 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
288 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
336 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
352 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
RESTORED
0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
416 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
432 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
448 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
464 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
480 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
496 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
@@ -0,0 +1,3 @@
prog: fxsave-amd64
vgopts: -q
args: x
@@ -0,0 +1,85 @@
/* https://bugs.kde.org/show_bug.cgi?id=308626 */
#include "../../memcheck.h"
#include <stdio.h>
#include <assert.h>
typedef unsigned int UInt;
/* Calculate ctz(x) using bsfl instruction. */
static int ctz(UInt x)
{
assert(sizeof(UInt) == 4);
int result=8*sizeof(UInt);
/* BSFL does not change the destination when the input is zero. */
asm("bsfl %1,%0" : "=r" (result) : "r" (x), "0" (result) : "cc");
return result;
}
/* Set the V bits at "addr". Note the convention: A zero bit means
"defined"; 1 means "undefined". */
static void set_vbits(UInt *addr, UInt vbits)
{
(void)VALGRIND_SET_VBITS(addr, &vbits, sizeof(unsigned));
}
static void doit(unsigned vbits, unsigned val)
{
/* Since we are about to mark "val" partially undefined, make a
copy that we can use without generating a memcheck warning. */
unsigned val_copy = val;
/* Mark "val" partially undefined. */
set_vbits(&val, vbits);
/* Convince GCC it does not know what is in "val" so it does not
optimize away any uses of it. */
__asm__ ("" : "=r" (val) : "0" (val));
int result = ctz(val);
/* The following code is carefully constructed: The conditional
itself should generate a memcheck warning if and only if it is
false. (Specifically, if the first "1" bit in val comes before
the first "undefined" bit, or the entire word is valid, then
ctz(val) is defined; else it is undefined.) */
if (result < ctz(vbits) || vbits == 0) {
/* There should be no memcheck warning on this printf, since
"result" is fully-defined in this case. */
printf("vbits=0x%08x ctz(0x%08x)=%d\n", vbits, val_copy, result);
}
else {
/* memcheck should have output a warning. But we want
something here so there is no possibiliy of Valgrind
optimizing out the conditional itself. */
fprintf(stderr, "0x%08x: Invalid value is %d\n", val_copy,
ctz(val_copy));
}
}
int main(int argc, char *argv[])
{
doit(0x00000000, 0x00000000);
doit(0x00000000, 0x00000001);
doit(0x00000001, 0x00000000);
doit(0x00000001, 0x00000001);
/* valid bit / data bit sandwich */
doit(0x00000090, 0x00000040);
doit(0x00000040, 0x00000090);
/* Interleaving */
doit(0x00000500, 0x00000a00);
doit(0x00000a00, 0x00000500);
doit(0x000f0000, 0x001e0000);
doit(0x001e0000, 0x000f0000);
doit(0xffffffff, 0xffffffff);
doit(0xfffffffe, 0xffffffff);
doit(0xffffffff, 0xfffffffe);
doit(0xfffffffe, 0xfffffffe);
return 0;
}
@@ -0,0 +1,40 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:65)
0x........: Invalid value is 32
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:66)
0x........: Invalid value is 0
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:69)
0x........: Invalid value is 6
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:73)
0x........: Invalid value is 9
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:76)
0x........: Invalid value is 17
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:79)
0x........: Invalid value is 0
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:81)
0x........: Invalid value is 1
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-bsfl.c:47)
by 0x........: main (insn-bsfl.c:82)
0x........: Invalid value is 1
@@ -0,0 +1,6 @@
vbits=0x00000000 ctz(0x00000000)=32
vbits=0x00000000 ctz(0x00000001)=0
vbits=0x00000040 ctz(0x00000090)=4
vbits=0x00000a00 ctz(0x00000500)=8
vbits=0x001e0000 ctz(0x000f0000)=16
vbits=0xfffffffe ctz(0xffffffff)=0
@@ -0,0 +1,2 @@
prog: insn-bsfl
vgopts: -q
@@ -0,0 +1,119 @@
/* https://bugs.kde.org/show_bug.cgi?id=309921 */
#define _XOPEN_SOURCE 600 /* for posix_memalign() */
#include "../../memcheck.h"
#include <stdio.h>
#include <assert.h>
#include <string.h>
#include <stdlib.h>
/* Exercise pcmpistri instruction in a realistic way. */
int aligned_strlen(const char *const s)
{
assert(((unsigned long)s & 0x0F) == 0);
const char *p = s;
/* volatile asm and "memory" clobber are needed here, since we
access memory in ways we cannot describe to GCC. */
__asm__ __volatile__ ("\n1:\n"
"\tmovdqa (%0),%%xmm6\n"
"\tpcmpistri $0x3a,%%xmm6,%%xmm6\n"
"\tjc 2f\n"
"\tadd $0x10,%0\n"
"\tjmp 1b\n"
"2:\n"
"\tadd %%rcx,%0\n"
: "=p" (p) : "0" (p) : "xmm6", "rcx", "cc", "memory");
return p-s;
}
/* Compute strlen(s). Arrange for result to be valid or invalid
according to second argument. */
int test_strlen(const char *const s, int valid)
{
/* len = length of string including trailing null */
const size_t len = strlen(s) + 1;
const size_t roundup = ((len+15)/16)*16;
int result = -1;
void *space;
posix_memalign(&space, 16, roundup);
memset(space, 'x', roundup);
memcpy(space, s, len);
const char *const s_copy = space;
const unsigned char ff = 0xFF;
if (valid) {
/* Mark all bytes beyond the null as invalid. */
size_t i;
for (i=len ; i < roundup ; ++i)
(void)VALGRIND_SET_VBITS(&s_copy[i], &ff, 1);
}
else {
/* Mark the null byte itself as invalid. */
assert(len > 0);
(void)VALGRIND_SET_VBITS(&s_copy[len-1], &ff, 1);
}
result = aligned_strlen(s_copy);
free(space);
return result;
}
void doit(const char *const s)
{
printf("strlen(\"%s\")=%d\n", s, test_strlen(s, 1));
fprintf(stderr, "strlen(\"%s\")=%s\n", s,
test_strlen(s, 0) ? "true" : "false");
}
int main(int argc, char *argv[])
{
doit("");
doit("a");
doit("ab");
doit("abc");
doit("abcd");
doit("abcde");
doit("abcdef");
doit("abcdefg");
/* 8 */
doit("abcdefgh");
doit("abcdefghi");
doit("abcdefghij");
doit("abcdefghijk");
doit("abcdefghijkl");
doit("abcdefghijklm");
doit("abcdefghijklmn");
doit("abcdefghijklmno");
/* 16 */
doit("abcdefghijklmnop");
doit("abcdefghijklmnopq");
doit("abcdefghijklmnopqr");
doit("abcdefghijklmnopqrs");
doit("abcdefghijklmnopqrst");
doit("abcdefghijklmnopqrstu");
doit("abcdefghijklmnopqrstuv");
doit("abcdefghijklmnopqrstuvw");
doit("abcdefghijklmnopqrstuwvx");
doit("abcdefghijklmnopqrstuwvxy");
doit("abcdefghijklmnopqrstuwvxyz");
/* 255 */
doit("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx");
/* 256 */
doit("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx");
return 0;
}
@@ -0,0 +1,319 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:79)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:79)
strlen("")=false
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:80)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:80)
strlen("a")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:81)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:81)
strlen("ab")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:82)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:82)
strlen("abc")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:83)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:83)
strlen("abcd")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:84)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:84)
strlen("abcde")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:85)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:85)
strlen("abcdef")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:86)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:86)
strlen("abcdefg")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:88)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:88)
strlen("abcdefgh")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:89)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:89)
strlen("abcdefghi")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:90)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:90)
strlen("abcdefghij")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:91)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:91)
strlen("abcdefghijk")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:92)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:92)
strlen("abcdefghijkl")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:93)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:93)
strlen("abcdefghijklm")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:94)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:94)
strlen("abcdefghijklmn")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:95)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:95)
strlen("abcdefghijklmno")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:97)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:97)
strlen("abcdefghijklmnop")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:98)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:98)
strlen("abcdefghijklmnopq")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:99)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:99)
strlen("abcdefghijklmnopqr")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:100)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:100)
strlen("abcdefghijklmnopqrs")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:101)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:101)
strlen("abcdefghijklmnopqrst")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:102)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:102)
strlen("abcdefghijklmnopqrstu")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:103)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:103)
strlen("abcdefghijklmnopqrstuv")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:104)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:104)
strlen("abcdefghijklmnopqrstuvw")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:105)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:105)
strlen("abcdefghijklmnopqrstuwvx")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:106)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:106)
strlen("abcdefghijklmnopqrstuwvxy")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:107)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:107)
strlen("abcdefghijklmnopqrstuwvxyz")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:109)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:109)
strlen("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx")=true
Conditional jump or move depends on uninitialised value(s)
at 0x........: aligned_strlen (insn-pcmpistri.c:21)
by 0x........: test_strlen (insn-pcmpistri.c:62)
by 0x........: doit (insn-pcmpistri.c:74)
by 0x........: main (insn-pcmpistri.c:114)
Conditional jump or move depends on uninitialised value(s)
at 0x........: doit (insn-pcmpistri.c:73)
by 0x........: main (insn-pcmpistri.c:114)
strlen("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx")=true
@@ -0,0 +1,29 @@
strlen("")=0
strlen("a")=1
strlen("ab")=2
strlen("abc")=3
strlen("abcd")=4
strlen("abcde")=5
strlen("abcdef")=6
strlen("abcdefg")=7
strlen("abcdefgh")=8
strlen("abcdefghi")=9
strlen("abcdefghij")=10
strlen("abcdefghijk")=11
strlen("abcdefghijkl")=12
strlen("abcdefghijklm")=13
strlen("abcdefghijklmn")=14
strlen("abcdefghijklmno")=15
strlen("abcdefghijklmnop")=16
strlen("abcdefghijklmnopq")=17
strlen("abcdefghijklmnopqr")=18
strlen("abcdefghijklmnopqrs")=19
strlen("abcdefghijklmnopqrst")=20
strlen("abcdefghijklmnopqrstu")=21
strlen("abcdefghijklmnopqrstuv")=22
strlen("abcdefghijklmnopqrstuvw")=23
strlen("abcdefghijklmnopqrstuwvx")=24
strlen("abcdefghijklmnopqrstuwvxy")=25
strlen("abcdefghijklmnopqrstuwvxyz")=26
strlen("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx")=255
strlen("xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx")=256
@@ -0,0 +1,3 @@
prereq: test -e ./insn-pcmpistri
prog: insn-pcmpistri
vgopts: -q
@@ -0,0 +1,147 @@
/* https://bugs.kde.org/show_bug.cgi?id=308627 */
#include "../../memcheck.h"
#include <stdio.h>
typedef unsigned long ULong;
typedef struct {
ULong w64[2]; /* Note: little-endian */
} V128;
static int getMSBs16x8(V128 v)
{
int result;
__asm__("movups %1,%%xmm6\n"
"\tpmovmskb %%xmm6,%0\n"
: "=r" (result) : "m" (v) : "xmm6");
return result;
}
/* Set the V bits on the data at "addr". Note the convention: A zero
bit means "defined"; 1 means "undefined". */
static void set_vbits(V128 *addr, V128 vbits)
{
int i;
for (i=0 ; i<2 ; ++i) {
(void)VALGRIND_SET_VBITS(&addr->w64[i], &vbits.w64[i], sizeof(vbits.w64[i]));
}
}
static void print(V128 vbits, V128 val, int bit, int result)
{
printf("vbits=0x%016lx%016lx val=0x%016lx%016lx bit=%d result=%d\n",
vbits.w64[1], vbits.w64[0], val.w64[1], val.w64[0],
bit, result);
}
/* Use a value that we know is invalid. */
static void use(int index, int invalid)
{
/* Convince GCC it does not know what is in "invalid" so it cannot
possibly optimize away the conditional branch below. */
__asm__ ("" : "=r" (invalid) : "0" (invalid));
/* Create a conditional branch on which our output depends, so that
memcheck cannot possibly optimize it away, either. */
fprintf(stderr, "%d: Invalid value is %s\n",
index, invalid ? "true" : "false");
}
static void doit(ULong vbits_hi, ULong vbits_lo, ULong val_hi, ULong val_lo)
{
V128 vbits = { { vbits_lo, vbits_hi } };
V128 val = { { val_lo, val_hi } };
/* Since we are about to mark "val" partially undefined, make a
copy that we can use without generating a memcheck warning. */
V128 val_copy = val;
set_vbits(&val, vbits);
int result = getMSBs16x8(val);
int vbits_mask = getMSBs16x8(vbits);
int bit = 0; ULong mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 1; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 2; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 3; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 4; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 5; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 6 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 7 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 8 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 9 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 10 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 11 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 12 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 13 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 14 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
bit = 15 ; mask = (1UL << bit);
if ((vbits_mask & mask) == 0) print(vbits, val_copy, bit, result & mask);
else use(bit, result & mask);
}
int main(int argc, char *argv[])
{
doit(0x0000000000000000, 0x0000000000000000,
0x0000000000000000, 0x0000000000000000);
doit(0x0707070707070707, 0x0707070707070707,
0x0000000000000000, 0x0000000000000000);
doit(0x8080808080808080, 0x8080808080808080,
0x0000000000000000, 0x0000000000000000);
doit(0x13579BDF02468ACE, 0xFEDCBA9876543210,
0xFEEDFACEDEADBEEF, 0xFEE1DEADDABBAD00);
return 0;
}
@@ -0,0 +1,144 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:69)
by 0x........: main (insn-pmovmskb.c:140)
0: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:73)
by 0x........: main (insn-pmovmskb.c:140)
1: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:77)
by 0x........: main (insn-pmovmskb.c:140)
2: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:81)
by 0x........: main (insn-pmovmskb.c:140)
3: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:85)
by 0x........: main (insn-pmovmskb.c:140)
4: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:89)
by 0x........: main (insn-pmovmskb.c:140)
5: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:93)
by 0x........: main (insn-pmovmskb.c:140)
6: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:97)
by 0x........: main (insn-pmovmskb.c:140)
7: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:101)
by 0x........: main (insn-pmovmskb.c:140)
8: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:105)
by 0x........: main (insn-pmovmskb.c:140)
9: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:109)
by 0x........: main (insn-pmovmskb.c:140)
10: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:113)
by 0x........: main (insn-pmovmskb.c:140)
11: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:117)
by 0x........: main (insn-pmovmskb.c:140)
12: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:121)
by 0x........: main (insn-pmovmskb.c:140)
13: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:125)
by 0x........: main (insn-pmovmskb.c:140)
14: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:129)
by 0x........: main (insn-pmovmskb.c:140)
15: Invalid value is false
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:85)
by 0x........: main (insn-pmovmskb.c:143)
4: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:89)
by 0x........: main (insn-pmovmskb.c:143)
5: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:93)
by 0x........: main (insn-pmovmskb.c:143)
6: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:97)
by 0x........: main (insn-pmovmskb.c:143)
7: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:101)
by 0x........: main (insn-pmovmskb.c:143)
8: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:105)
by 0x........: main (insn-pmovmskb.c:143)
9: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:117)
by 0x........: main (insn-pmovmskb.c:143)
12: Invalid value is true
Conditional jump or move depends on uninitialised value(s)
at 0x........: use (insn-pmovmskb.c:48)
by 0x........: doit (insn-pmovmskb.c:121)
by 0x........: main (insn-pmovmskb.c:143)
13: Invalid value is true
@@ -0,0 +1,40 @@
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=0 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=1 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=2 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=3 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=4 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=5 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=6 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=7 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=8 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=9 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=10 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=11 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=12 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=13 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=14 result=0
vbits=0x00000000000000000000000000000000 val=0x00000000000000000000000000000000 bit=15 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=0 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=1 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=2 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=3 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=4 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=5 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=6 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=7 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=8 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=9 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=10 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=11 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=12 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=13 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=14 result=0
vbits=0x07070707070707070707070707070707 val=0x00000000000000000000000000000000 bit=15 result=0
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=0 result=0
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=1 result=2
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=2 result=4
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=3 result=8
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=10 result=1024
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=11 result=2048
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=14 result=16384
vbits=0x13579bdf02468acefedcba9876543210 val=0xfeedfacedeadbeeffee1deaddabbad00 bit=15 result=32768
@@ -0,0 +1,2 @@
prog: insn-pmovmskb
vgopts: -q
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,2 @@
prog: ../../../none/tests/amd64/insn_basic
vgopts: -q
@@ -0,0 +1,452 @@
fabs_1 ... ok
fabs_2 ... ok
fabs_3 ... ok
fabs_4 ... ok
fadds_1 ... ok
fadds_2 ... ok
fadds_3 ... ok
fadds_4 ... ok
faddl_1 ... ok
faddl_2 ... ok
faddl_3 ... ok
faddl_4 ... ok
fadd_1 ... ok
fadd_2 ... ok
fadd_3 ... ok
fadd_4 ... ok
fadd_5 ... ok
fadd_6 ... ok
fadd_7 ... ok
fadd_8 ... ok
fadd_9 ... ok
fadd_10 ... ok
fadd_11 ... ok
fadd_12 ... ok
fadd_13 ... ok
fadd_14 ... ok
fadd_15 ... ok
fadd_16 ... ok
faddp_1 ... ok
faddp_2 ... ok
faddp_3 ... ok
faddp_4 ... ok
faddp_5 ... ok
faddp_6 ... ok
faddp_7 ... ok
faddp_8 ... ok
faddp_9 ... ok
faddp_10 ... ok
faddp_11 ... ok
faddp_12 ... ok
faddp_13 ... ok
faddp_14 ... ok
faddp_15 ... ok
faddp_16 ... ok
fiadds_1 ... ok
fiadds_2 ... ok
fiadds_3 ... ok
fiadds_4 ... ok
fiadds_5 ... ok
fiadds_6 ... ok
fiadds_7 ... ok
fiadds_8 ... ok
fiaddl_1 ... ok
fiaddl_2 ... ok
fiaddl_3 ... ok
fiaddl_4 ... ok
fiaddl_5 ... ok
fiaddl_6 ... ok
fiaddl_7 ... ok
fiaddl_8 ... ok
fcomi_1 ... ok
fcomi_2 ... ok
fcomi_3 ... ok
fcomi_4 ... ok
fcomi_5 ... ok
fcomi_6 ... ok
fcomip_1 ... ok
fcomip_2 ... ok
fcomip_3 ... ok
fcomip_4 ... ok
fcomip_5 ... ok
fcomip_6 ... ok
fucomi_1 ... ok
fucomi_2 ... ok
fucomi_3 ... ok
fucomi_4 ... ok
fucomi_5 ... ok
fucomi_6 ... ok
fucomip_1 ... ok
fucomip_2 ... ok
fucomip_3 ... ok
fucomip_4 ... ok
fucomip_5 ... ok
fucomip_6 ... ok
fchs_1 ... ok
fchs_2 ... ok
fchs_3 ... ok
fchs_4 ... ok
fdivs_1 ... ok
fdivs_2 ... ok
fdivs_3 ... ok
fdivs_4 ... ok
fdivl_1 ... ok
fdivl_2 ... ok
fdivl_3 ... ok
fdivl_4 ... ok
fdiv_1 ... ok
fdiv_2 ... ok
fdiv_3 ... ok
fdiv_4 ... ok
fdiv_5 ... ok
fdiv_6 ... ok
fdiv_7 ... ok
fdiv_8 ... ok
fdiv_9 ... ok
fdiv_10 ... ok
fdiv_11 ... ok
fdiv_12 ... ok
fdiv_13 ... ok
fdiv_14 ... ok
fdiv_15 ... ok
fdiv_16 ... ok
fdivp_1 ... ok
fdivp_2 ... ok
fdivp_3 ... ok
fdivp_4 ... ok
fdivp_5 ... ok
fdivp_6 ... ok
fdivp_7 ... ok
fdivp_8 ... ok
fdivp_9 ... ok
fdivp_10 ... ok
fdivp_11 ... ok
fdivp_12 ... ok
fdivp_13 ... ok
fdivp_14 ... ok
fdivp_15 ... ok
fdivp_16 ... ok
fidivs_1 ... ok
fidivs_2 ... ok
fidivs_3 ... ok
fidivs_4 ... ok
fidivs_5 ... ok
fidivs_6 ... ok
fidivs_7 ... ok
fidivs_8 ... ok
fidivl_1 ... ok
fidivl_2 ... ok
fidivl_3 ... ok
fidivl_4 ... ok
fidivl_5 ... ok
fidivl_6 ... ok
fidivl_7 ... ok
fidivl_8 ... ok
fdivrs_1 ... ok
fdivrs_2 ... ok
fdivrs_3 ... ok
fdivrs_4 ... ok
fdivrl_1 ... ok
fdivrl_2 ... ok
fdivrl_3 ... ok
fdivrl_4 ... ok
fdivr_1 ... ok
fdivr_2 ... ok
fdivr_3 ... ok
fdivr_4 ... ok
fdivr_5 ... ok
fdivr_6 ... ok
fdivr_7 ... ok
fdivr_8 ... ok
fdivr_9 ... ok
fdivr_10 ... ok
fdivr_11 ... ok
fdivr_12 ... ok
fdivr_13 ... ok
fdivr_14 ... ok
fdivr_15 ... ok
fdivr_16 ... ok
fdivrp_1 ... ok
fdivrp_2 ... ok
fdivrp_3 ... ok
fdivrp_4 ... ok
fdivrp_5 ... ok
fdivrp_6 ... ok
fdivrp_7 ... ok
fdivrp_8 ... ok
fdivrp_9 ... ok
fdivrp_10 ... ok
fdivrp_11 ... ok
fdivrp_12 ... ok
fdivrp_13 ... ok
fdivrp_14 ... ok
fdivrp_15 ... ok
fdivrp_16 ... ok
fidivrs_1 ... ok
fidivrs_2 ... ok
fidivrs_3 ... ok
fidivrs_4 ... ok
fidivrs_5 ... ok
fidivrs_6 ... ok
fidivrs_7 ... ok
fidivrs_8 ... ok
fidivrl_1 ... ok
fidivrl_2 ... ok
fidivrl_3 ... ok
fidivrl_4 ... ok
fidivrl_5 ... ok
fidivrl_6 ... ok
fidivrl_7 ... ok
fidivrl_8 ... ok
filds_1 ... ok
filds_2 ... ok
filds_3 ... ok
filds_4 ... ok
fildl_1 ... ok
fildl_2 ... ok
fildl_3 ... ok
fildl_4 ... ok
fildq_1 ... ok
fildq_2 ... ok
fildq_3 ... ok
fildq_4 ... ok
fists_1 ... ok
fists_2 ... ok
fists_3 ... ok
fists_4 ... ok
fists_5 ... ok
fists_6 ... ok
fists_7 ... ok
fists_8 ... ok
fistl_1 ... ok
fistl_2 ... ok
fistl_3 ... ok
fistl_4 ... ok
fistl_5 ... ok
fistl_6 ... ok
fistl_7 ... ok
fistl_8 ... ok
fistps_1 ... ok
fistps_2 ... ok
fistps_3 ... ok
fistps_4 ... ok
fistps_5 ... ok
fistps_6 ... ok
fistps_7 ... ok
fistps_8 ... ok
fistpl_1 ... ok
fistpl_2 ... ok
fistpl_3 ... ok
fistpl_4 ... ok
fistpl_5 ... ok
fistpl_6 ... ok
fistpl_7 ... ok
fistpl_8 ... ok
fistpq_1 ... ok
fistpq_2 ... ok
fistpq_3 ... ok
fistpq_4 ... ok
fistpq_5 ... ok
fistpq_6 ... ok
fistpq_7 ... ok
fistpq_8 ... ok
flds_1 ... ok
flds_2 ... ok
fldl_1 ... ok
fldl_2 ... ok
fld_1 ... ok
fld_2 ... ok
fld_3 ... ok
fld1_1 ... ok
fldl2t_1 ... ok
fldl2e_1 ... ok
fldpi_1 ... ok
fldlg2_1 ... ok
fldln2_1 ... ok
fldz_1 ... ok
fmuls_1 ... ok
fmuls_2 ... ok
fmuls_3 ... ok
fmuls_4 ... ok
fmull_1 ... ok
fmull_2 ... ok
fmull_3 ... ok
fmull_4 ... ok
fmul_1 ... ok
fmul_2 ... ok
fmul_3 ... ok
fmul_4 ... ok
fmul_5 ... ok
fmul_6 ... ok
fmul_7 ... ok
fmul_8 ... ok
fmul_9 ... ok
fmul_10 ... ok
fmul_11 ... ok
fmul_12 ... ok
fmul_13 ... ok
fmul_14 ... ok
fmul_15 ... ok
fmul_16 ... ok
fmulp_1 ... ok
fmulp_2 ... ok
fmulp_3 ... ok
fmulp_4 ... ok
fmulp_5 ... ok
fmulp_6 ... ok
fmulp_7 ... ok
fmulp_8 ... ok
fmulp_9 ... ok
fmulp_10 ... ok
fmulp_11 ... ok
fmulp_12 ... ok
fmulp_13 ... ok
fmulp_14 ... ok
fmulp_15 ... ok
fmulp_16 ... ok
fimuls_1 ... ok
fimuls_2 ... ok
fimuls_3 ... ok
fimuls_4 ... ok
fimuls_5 ... ok
fimuls_6 ... ok
fimuls_7 ... ok
fimuls_8 ... ok
fimull_1 ... ok
fimull_2 ... ok
fimull_3 ... ok
fimull_4 ... ok
fimull_5 ... ok
fimull_6 ... ok
fimull_7 ... ok
fimull_8 ... ok
frndint_1 ... ok
frndint_2 ... ok
frndint_3 ... ok
frndint_4 ... ok
frndint_5 ... ok
frndint_6 ... ok
frndint_7 ... ok
frndint_8 ... ok
frndint_9 ... ok
frndint_10 ... ok
frndint_11 ... ok
frndint_12 ... ok
frndint_13 ... ok
frndint_14 ... ok
frndint_15 ... ok
frndint_16 ... ok
fsubs_1 ... ok
fsubs_2 ... ok
fsubs_3 ... ok
fsubs_4 ... ok
fsubl_1 ... ok
fsubl_2 ... ok
fsubl_3 ... ok
fsubl_4 ... ok
fsub_1 ... ok
fsub_2 ... ok
fsub_3 ... ok
fsub_4 ... ok
fsub_5 ... ok
fsub_6 ... ok
fsub_7 ... ok
fsub_8 ... ok
fsub_9 ... ok
fsub_10 ... ok
fsub_11 ... ok
fsub_12 ... ok
fsub_13 ... ok
fsub_14 ... ok
fsub_15 ... ok
fsub_16 ... ok
fsubp_1 ... ok
fsubp_2 ... ok
fsubp_3 ... ok
fsubp_4 ... ok
fsubp_5 ... ok
fsubp_6 ... ok
fsubp_7 ... ok
fsubp_8 ... ok
fsubp_9 ... ok
fsubp_10 ... ok
fsubp_11 ... ok
fsubp_12 ... ok
fsubp_13 ... ok
fsubp_14 ... ok
fsubp_15 ... ok
fsubp_16 ... ok
fisubs_1 ... ok
fisubs_2 ... ok
fisubs_3 ... ok
fisubs_4 ... ok
fisubs_5 ... ok
fisubs_6 ... ok
fisubs_7 ... ok
fisubs_8 ... ok
fisubl_1 ... ok
fisubl_2 ... ok
fisubl_3 ... ok
fisubl_4 ... ok
fisubl_5 ... ok
fisubl_6 ... ok
fisubl_7 ... ok
fisubl_8 ... ok
fsubrs_1 ... ok
fsubrs_2 ... ok
fsubrs_3 ... ok
fsubrs_4 ... ok
fsubrl_1 ... ok
fsubrl_2 ... ok
fsubrl_3 ... ok
fsubrl_4 ... ok
fsubr_1 ... ok
fsubr_2 ... ok
fsubr_3 ... ok
fsubr_4 ... ok
fsubr_5 ... ok
fsubr_6 ... ok
fsubr_7 ... ok
fsubr_8 ... ok
fsubr_9 ... ok
fsubr_10 ... ok
fsubr_11 ... ok
fsubr_12 ... ok
fsubr_13 ... ok
fsubr_14 ... ok
fsubr_15 ... ok
fsubr_16 ... ok
fsubrp_1 ... ok
fsubrp_2 ... ok
fsubrp_3 ... ok
fsubrp_4 ... ok
fsubrp_5 ... ok
fsubrp_6 ... ok
fsubrp_7 ... ok
fsubrp_8 ... ok
fsubrp_9 ... ok
fsubrp_10 ... ok
fsubrp_11 ... ok
fsubrp_12 ... ok
fsubrp_13 ... ok
fsubrp_14 ... ok
fsubrp_15 ... ok
fsubrp_16 ... ok
fisubrs_1 ... ok
fisubrs_2 ... ok
fisubrs_3 ... ok
fisubrs_4 ... ok
fisubrs_5 ... ok
fisubrs_6 ... ok
fisubrs_7 ... ok
fisubrs_8 ... ok
fisubrl_1 ... ok
fisubrl_2 ... ok
fisubrl_3 ... ok
fisubrl_4 ... ok
fisubrl_5 ... ok
fisubrl_6 ... ok
fisubrl_7 ... ok
fisubrl_8 ... ok
fxch_1 ... ok
fxch_2 ... ok
@@ -0,0 +1,2 @@
prog: ../../../none/tests/amd64/insn_fpu
vgopts: -q
@@ -0,0 +1,105 @@
movd_1 ... ok
movd_2 ... ok
movd_3 ... ok
movd_4 ... ok
movd_5 ... ok
movd_6 ... ok
movq_1 ... ok
movq_2 ... ok
movq_3 ... ok
packssdw_1 ... ok
packssdw_2 ... ok
packsswb_1 ... ok
packsswb_2 ... ok
packuswb_1 ... ok
packuswb_2 ... ok
paddb_1 ... ok
paddb_2 ... ok
paddd_1 ... ok
paddd_2 ... ok
paddsb_1 ... ok
paddsb_2 ... ok
paddsw_1 ... ok
paddsw_2 ... ok
paddusb_1 ... ok
paddusb_2 ... ok
paddusw_1 ... ok
paddusw_2 ... ok
paddw_1 ... ok
paddw_2 ... ok
pand_1 ... ok
pand_2 ... ok
pandn_1 ... ok
pandn_2 ... ok
pcmpeqb_1 ... ok
pcmpeqb_2 ... ok
pcmpeqd_1 ... ok
pcmpeqd_2 ... ok
pcmpeqw_1 ... ok
pcmpeqw_2 ... ok
pcmpgtb_1 ... ok
pcmpgtb_2 ... ok
pcmpgtd_1 ... ok
pcmpgtd_2 ... ok
pcmpgtw_1 ... ok
pcmpgtw_2 ... ok
pmaddwd_1 ... ok
pmaddwd_2 ... ok
pmulhw_1 ... ok
pmulhw_2 ... ok
pmullw_1 ... ok
pmullw_2 ... ok
por_1 ... ok
por_2 ... ok
pslld_1 ... ok
pslld_2 ... ok
pslld_3 ... ok
psllq_1 ... ok
psllq_2 ... ok
psllq_3 ... ok
psllw_1 ... ok
psllw_2 ... ok
psllw_3 ... ok
psrad_1 ... ok
psrad_2 ... ok
psrad_3 ... ok
psraw_1 ... ok
psraw_2 ... ok
psraw_3 ... ok
psrld_1 ... ok
psrld_2 ... ok
psrld_3 ... ok
psrlq_1 ... ok
psrlq_2 ... ok
psrlq_3 ... ok
psrlw_1 ... ok
psrlw_2 ... ok
psrlw_3 ... ok
psubb_1 ... ok
psubb_2 ... ok
psubd_1 ... ok
psubd_2 ... ok
psubsb_1 ... ok
psubsb_2 ... ok
psubsw_1 ... ok
psubsw_2 ... ok
psubusb_1 ... ok
psubusb_2 ... ok
psubusw_1 ... ok
psubusw_2 ... ok
psubw_1 ... ok
psubw_2 ... ok
punpckhbw_1 ... ok
punpckhbw_2 ... ok
punpckhdq_1 ... ok
punpckhdq_2 ... ok
punpckhwd_1 ... ok
punpckhwd_2 ... ok
punpcklbw_1 ... ok
punpcklbw_2 ... ok
punpckldq_1 ... ok
punpckldq_2 ... ok
punpcklwd_1 ... ok
punpcklwd_2 ... ok
pxor_1 ... ok
pxor_2 ... ok
@@ -0,0 +1,2 @@
prog: ../../../none/tests/amd64/insn_mmx
vgopts: -q
@@ -0,0 +1,154 @@
addps_1 ... ok
addps_2 ... ok
addss_1 ... ok
addss_2 ... ok
andnps_1 ... ok
andnps_2 ... ok
andps_1 ... ok
andps_2 ... ok
cmpeqps_1 ... ok
cmpeqps_2 ... ok
cmpeqss_1 ... ok
cmpeqss_2 ... ok
cmpleps_1 ... ok
cmpleps_2 ... ok
cmpless_1 ... ok
cmpless_2 ... ok
cmpltps_1 ... ok
cmpltps_2 ... ok
cmpltss_1 ... ok
cmpltss_2 ... ok
cmpunordps_1 ... ok
cmpunordps_2 ... ok
cmpunordss_1 ... ok
cmpunordss_2 ... ok
cmpneqps_1 ... ok
cmpneqps_2 ... ok
cmpneqss_1 ... ok
cmpneqss_2 ... ok
cmpnleps_1 ... ok
cmpnleps_2 ... ok
cmpnless_1 ... ok
cmpnless_2 ... ok
cmpnltps_1 ... ok
cmpnltps_2 ... ok
cmpnltss_1 ... ok
cmpnltss_2 ... ok
cmpordps_1 ... ok
cmpordps_2 ... ok
cmpordss_1 ... ok
cmpordss_2 ... ok
comiss_1 ... ok
comiss_2 ... ok
comiss_3 ... ok
comiss_4 ... ok
comiss_5 ... ok
comiss_6 ... ok
cvtpi2ps_1 ... ok
cvtpi2ps_2 ... ok
cvtps2pi_1 ... ok
cvtps2pi_2 ... ok
cvtsi2ss_1 ... ok
cvtsi2ss_2 ... ok
cvtss2si_1 ... ok
cvtss2si_2 ... ok
cvttps2pi_1 ... ok
cvttps2pi_2 ... ok
cvttss2si_1 ... ok
cvttss2si_2 ... ok
divps_1 ... ok
divps_2 ... ok
divss_1 ... ok
divss_2 ... ok
maxps_1 ... ok
maxps_2 ... ok
maxss_1 ... ok
maxss_2 ... ok
minps_1 ... ok
minps_2 ... ok
minss_1 ... ok
minss_2 ... ok
movaps_1 ... ok
movaps_2 ... ok
movhlps_1 ... ok
movhps_1 ... ok
movhps_2 ... ok
movlhps_1 ... ok
movlps_1 ... ok
movlps_2 ... ok
movmskps_1 ... ok
movntps_1 ... ok
movntq_1 ... ok
movss_1 ... ok
movss_2 ... ok
movss_3 ... ok
movups_1 ... ok
movups_2 ... ok
mulps_1 ... ok
mulps_2 ... ok
mulss_1 ... ok
mulss_2 ... ok
orps_1 ... ok
orps_2 ... ok
pavgb_1 ... ok
pavgb_2 ... ok
pavgw_1 ... ok
pavgw_2 ... ok
pextrw_1 ... ok
pextrw_2 ... ok
pextrw_3 ... ok
pextrw_4 ... ok
pinsrw_1 ... ok
pinsrw_2 ... ok
pinsrw_3 ... ok
pinsrw_4 ... ok
pinsrw_5 ... ok
pinsrw_6 ... ok
pinsrw_7 ... ok
pinsrw_8 ... ok
pmaxsw_1 ... ok
pmaxsw_2 ... ok
pmaxub_1 ... ok
pmaxub_2 ... ok
pminsw_1 ... ok
pminsw_2 ... ok
pminub_1 ... ok
pminub_2 ... ok
pmovmskb_1 ... ok
pmulhuw_1 ... ok
pmulhuw_2 ... ok
psadbw_1 ... ok
psadbw_2 ... ok
pshufw_1 ... ok
pshufw_2 ... ok
rcpps_1 ... ok
rcpps_2 ... ok
rcpss_1 ... ok
rcpss_2 ... ok
rsqrtps_1 ... ok
rsqrtps_2 ... ok
rsqrtss_1 ... ok
rsqrtss_2 ... ok
sfence_1 ... ok
shufps_1 ... ok
shufps_2 ... ok
sqrtps_1 ... ok
sqrtps_2 ... ok
sqrtss_1 ... ok
sqrtss_2 ... ok
subps_1 ... ok
subps_2 ... ok
subss_1 ... ok
subss_2 ... ok
ucomiss_1 ... ok
ucomiss_2 ... ok
ucomiss_3 ... ok
ucomiss_4 ... ok
ucomiss_5 ... ok
ucomiss_6 ... ok
unpckhps_1 ... ok
unpckhps_2 ... ok
unpcklps_1 ... ok
unpcklps_2 ... ok
xorps_1 ... ok
xorps_2 ... ok
@@ -0,0 +1,2 @@
prog: ../../../none/tests/amd64/insn_sse
vgopts: -q
@@ -0,0 +1,343 @@
addpd_1 ... ok
addpd_2 ... ok
addsd_1 ... ok
addsd_2 ... ok
andpd_1 ... ok
andpd_2 ... ok
andnpd_1 ... ok
andnpd_2 ... ok
cmpeqpd_1 ... ok
cmpeqpd_2 ... ok
cmpltpd_1 ... ok
cmpltpd_2 ... ok
cmplepd_1 ... ok
cmplepd_2 ... ok
cmpunordpd_1 ... ok
cmpunordpd_2 ... ok
cmpneqpd_1 ... ok
cmpneqpd_2 ... ok
cmpnltpd_1 ... ok
cmpnltpd_2 ... ok
cmpnlepd_1 ... ok
cmpnlepd_2 ... ok
cmpordpd_1 ... ok
cmpordpd_2 ... ok
cmpeqsd_1 ... ok
cmpeqsd_2 ... ok
cmpltsd_1 ... ok
cmpltsd_2 ... ok
cmplesd_1 ... ok
cmplesd_2 ... ok
cmpunordsd_1 ... ok
cmpunordsd_2 ... ok
cmpneqsd_1 ... ok
cmpneqsd_2 ... ok
cmpnltsd_1 ... ok
cmpnltsd_2 ... ok
cmpnlesd_1 ... ok
cmpnlesd_2 ... ok
cmpordsd_1 ... ok
cmpordsd_2 ... ok
comisd_1 ... ok
comisd_2 ... ok
comisd_3 ... ok
comisd_4 ... ok
comisd_5 ... ok
comisd_6 ... ok
cvtdq2pd_1 ... ok
cvtdq2pd_2 ... ok
cvtdq2ps_1 ... ok
cvtdq2ps_2 ... ok
cvtpd2dq_1 ... ok
cvtpd2dq_2 ... ok
cvtpd2pi_1 ... ok
cvtpd2pi_2 ... ok
cvtpd2ps_1 ... ok
cvtpd2ps_2 ... ok
cvtpi2pd_1 ... ok
cvtpi2pd_2 ... ok
cvtps2dq_1 ... ok
cvtps2dq_2 ... ok
cvtps2pd_1 ... ok
cvtps2pd_2 ... ok
cvtsd2si_1 ... ok
cvtsd2si_2 ... ok
cvtsd2ss_1 ... ok
cvtsd2ss_2 ... ok
cvtsi2sd_1 ... ok
cvtsi2sd_2 ... ok
cvtss2sd_1 ... ok
cvtss2sd_2 ... ok
cvttpd2pi_1 ... ok
cvttpd2pi_2 ... ok
cvttpd2dq_1 ... ok
cvttpd2dq_2 ... ok
cvttps2dq_1 ... ok
cvttps2dq_2 ... ok
cvttsd2si_1 ... ok
cvttsd2si_2 ... ok
divpd_1 ... ok
divpd_2 ... ok
divsd_1 ... ok
divsd_2 ... ok
lfence_1 ... ok
maxpd_1 ... ok
maxpd_2 ... ok
maxsd_1 ... ok
maxsd_2 ... ok
mfence_1 ... ok
minpd_1 ... ok
minpd_2 ... ok
minsd_1 ... ok
minsd_2 ... ok
movapd_1 ... ok
movapd_2 ... ok
movd_1 ... ok
movd_2 ... ok
movd_3 ... ok
movd_4 ... ok
movdqa_1 ... ok
movdqa_2 ... ok
movdqa_3 ... ok
movdqu_1 ... ok
movdqu_2 ... ok
movdqu_3 ... ok
movdq2q_1 ... ok
movhpd_1 ... ok
movhpd_2 ... ok
movlpd_1 ... ok
movlpd_2 ... ok
movmskpd_1 ... ok
movntdq_1 ... ok
movnti_1 ... ok
movntpd_1 ... ok
movq_1 ... ok
movq_2 ... ok
movq_3 ... ok
movq2dq_1 ... ok
movsd_1 ... ok
movsd_2 ... ok
movsd_3 ... ok
movupd_1 ... ok
movupd_2 ... ok
mulpd_1 ... ok
mulpd_2 ... ok
mulsd_1 ... ok
mulsd_2 ... ok
orpd_1 ... ok
orpd_2 ... ok
packssdw_1 ... ok
packssdw_2 ... ok
packsswb_1 ... ok
packsswb_2 ... ok
packuswb_1 ... ok
packuswb_2 ... ok
paddb_1 ... ok
paddb_2 ... ok
paddd_1 ... ok
paddd_2 ... ok
paddq_1 ... ok
paddq_2 ... ok
paddq_3 ... ok
paddq_4 ... ok
paddsb_1 ... ok
paddsb_2 ... ok
paddsw_1 ... ok
paddsw_2 ... ok
paddusb_1 ... ok
paddusb_2 ... ok
paddusw_1 ... ok
paddusw_2 ... ok
paddw_1 ... ok
paddw_2 ... ok
pand_1 ... ok
pand_2 ... ok
pandn_1 ... ok
pandn_2 ... ok
pavgb_1 ... ok
pavgb_2 ... ok
pavgw_1 ... ok
pavgw_2 ... ok
pcmpeqb_1 ... ok
pcmpeqb_2 ... ok
pcmpeqd_1 ... ok
pcmpeqd_2 ... ok
pcmpeqw_1 ... ok
pcmpeqw_2 ... ok
pcmpgtb_1 ... ok
pcmpgtb_2 ... ok
pcmpgtd_1 ... ok
pcmpgtd_2 ... ok
pcmpgtw_1 ... ok
pcmpgtw_2 ... ok
pextrw_1 ... ok
pextrw_2 ... ok
pextrw_3 ... ok
pextrw_4 ... ok
pextrw_5 ... ok
pextrw_6 ... ok
pextrw_7 ... ok
pextrw_8 ... ok
pinsrw_1 ... ok
pinsrw_2 ... ok
pinsrw_3 ... ok
pinsrw_4 ... ok
pinsrw_5 ... ok
pinsrw_6 ... ok
pinsrw_7 ... ok
pinsrw_8 ... ok
pinsrw_9 ... ok
pinsrw_10 ... ok
pinsrw_11 ... ok
pinsrw_12 ... ok
pinsrw_13 ... ok
pinsrw_14 ... ok
pinsrw_15 ... ok
pinsrw_16 ... ok
pmaddwd_1 ... ok
pmaddwd_2 ... ok
pmaxsw_1 ... ok
pmaxsw_2 ... ok
pmaxub_1 ... ok
pmaxub_2 ... ok
pminsw_1 ... ok
pminsw_2 ... ok
pminub_1 ... ok
pminub_2 ... ok
pmovmskb_1 ... ok
pmulhuw_1 ... ok
pmulhuw_2 ... ok
pmulhw_1 ... ok
pmulhw_2 ... ok
pmullw_1 ... ok
pmullw_2 ... ok
pmuludq_1 ... ok
pmuludq_2 ... ok
pmuludq_3 ... ok
pmuludq_4 ... ok
por_1 ... ok
por_2 ... ok
psadbw_1 ... ok
psadbw_2 ... ok
pshufd_1 ... ok
pshufd_2 ... ok
pshufhw_1 ... ok
pshufhw_2 ... ok
pshuflw_1 ... ok
pshuflw_2 ... ok
pslld_1 ... ok
pslld_2 ... ok
pslld_3 ... ok
pslldq_1 ... ok
pslldq_2 ... ok
pslldq_3 ... ok
pslldq_4 ... ok
pslldq_5 ... ok
pslldq_6 ... ok
pslldq_7 ... ok
pslldq_8 ... ok
pslldq_9 ... ok
pslldq_10 ... ok
pslldq_11 ... ok
pslldq_12 ... ok
pslldq_13 ... ok
pslldq_14 ... ok
pslldq_15 ... ok
pslldq_16 ... ok
pslldq_17 ... ok
psllq_1 ... ok
psllq_2 ... ok
psllq_3 ... ok
psllw_1 ... ok
psllw_2 ... ok
psllw_3 ... ok
psrad_1 ... ok
psrad_2 ... ok
psrad_3 ... ok
psraw_1 ... ok
psraw_2 ... ok
psraw_3 ... ok
psrld_1 ... ok
psrld_2 ... ok
psrld_3 ... ok
psrldq_1 ... ok
psrldq_2 ... ok
psrldq_3 ... ok
psrldq_4 ... ok
psrldq_5 ... ok
psrldq_6 ... ok
psrldq_7 ... ok
psrldq_8 ... ok
psrldq_9 ... ok
psrldq_10 ... ok
psrldq_11 ... ok
psrldq_12 ... ok
psrldq_13 ... ok
psrldq_14 ... ok
psrldq_15 ... ok
psrldq_16 ... ok
psrldq_17 ... ok
psrlq_1 ... ok
psrlq_2 ... ok
psrlq_3 ... ok
psrlw_1 ... ok
psrlw_2 ... ok
psrlw_3 ... ok
psubb_1 ... ok
psubb_2 ... ok
psubd_1 ... ok
psubd_2 ... ok
psubq_1 ... ok
psubq_2 ... ok
psubq_3 ... ok
psubq_4 ... ok
psubsb_1 ... ok
psubsb_2 ... ok
psubsw_1 ... ok
psubsw_2 ... ok
psubusb_1 ... ok
psubusb_2 ... ok
psubusw_1 ... ok
psubusw_2 ... ok
psubw_1 ... ok
psubw_2 ... ok
punpckhbw_1 ... ok
punpckhbw_2 ... ok
punpckhdq_1 ... ok
punpckhdq_2 ... ok
punpckhqdq_1 ... ok
punpckhqdq_2 ... ok
punpckhwd_1 ... ok
punpckhwd_2 ... ok
punpcklbw_1 ... ok
punpcklbw_2 ... ok
punpckldq_1 ... ok
punpckldq_2 ... ok
punpcklqdq_1 ... ok
punpcklqdq_2 ... ok
punpcklwd_1 ... ok
punpcklwd_2 ... ok
pxor_1 ... ok
pxor_2 ... ok
shufpd_1 ... ok
shufpd_2 ... ok
sqrtpd_1 ... ok
sqrtpd_2 ... ok
sqrtsd_1 ... ok
sqrtsd_2 ... ok
subpd_1 ... ok
subpd_2 ... ok
subsd_1 ... ok
subsd_2 ... ok
ucomisd_1 ... ok
ucomisd_2 ... ok
ucomisd_3 ... ok
ucomisd_4 ... ok
ucomisd_5 ... ok
ucomisd_6 ... ok
unpckhpd_1 ... ok
unpckhpd_2 ... ok
unpcklpd_1 ... ok
unpcklpd_2 ... ok
xorpd_1 ... ok
xorpd_2 ... ok
@@ -0,0 +1,2 @@
prog: ../../../none/tests/amd64/insn_sse2
vgopts: -q
@@ -0,0 +1,273 @@
/* On amd64, to exercise x87, compile with
gcc4 -ffast-math -mfpmath=387 -mfancy-math-387
gcc4 really does generate all the sin cos tan stuff as
x87 insns inline. gcc 3.3 doesn't, which makes the test
pretty useless, but it should still pass. To be on the safe
side we need to link with -lm to handle the gcc 3.3 behaviour.
*/
/* Derived from: */
/*
* x86 CPU test
*
* Copyright (c) 2003 Fabrice Bellard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
/**********************************************/
void test_fops(double a, double b)
{
printf("a=%f b=%f a+b=%f\n", a, b, a + b);
printf("a=%f b=%f a-b=%f\n", a, b, a - b);
printf("a=%f b=%f a*b=%f\n", a, b, a * b);
printf("a=%f b=%f a/b=%f\n", a, b, a / b);
// requires fprem/fprem1 -- not done
//printf("a=%f b=%f fmod(a, b)=%f\n", a, b, fmod(a, b));
printf("a=%f sqrt(a)=%f\n", a, sqrt(a));
printf("a=%f sin(a)=%f\n", a, sin(a));
printf("a=%f cos(a)=%f\n", a, cos(a));
printf("a=%f tan(a)=%f\n", a, tan(a));
printf("a=%f log(a)=%f\n", a, log(a));
printf("a=%f exp(a)=%f\n", a, exp(a));
printf("a=%f b=%f atan2(a, b)=%f\n", a, b, atan2(a, b));
/* just to test some op combining */
printf("a=%f asin(sin(a))=%f\n", a, asin(sin(a)));
printf("a=%f acos(cos(a))=%f\n", a, acos(cos(a)));
printf("a=%f atan(tan(a))=%f\n", a, atan(tan(a)));
}
#define CC_C 0x0001
#define CC_P 0x0004
#define CC_A 0x0010
#define CC_Z 0x0040
#define CC_S 0x0080
#define CC_O 0x0800
void test_fcmp(double a, double b)
{
printf("(%f<%f)=%d\n",
a, b, a < b);
printf("(%f<=%f)=%d\n",
a, b, a <= b);
printf("(%f==%f)=%d\n",
a, b, a == b);
printf("(%f>%f)=%d\n",
a, b, a > b);
printf("(%f<=%f)=%d\n",
a, b, a >= b);
{
unsigned long long int eflags;
/* test f(u)comi instruction */
asm("fcomi %2, %1\n"
"pushfq\n"
"popq %0\n"
: "=r" (eflags)
: "t" (a), "u" (b));
printf("fcomi(%f %f)=%08llx\n", a, b, eflags & (CC_Z | CC_P | CC_C));
}
}
void test_fcvt(double a)
{
float fa;
long double la;
int16_t fpuc;
int i;
int64_t lla;
int ia;
int16_t wa;
double ra;
fa = a;
la = a;
printf("(float)%e = %e\n", a, fa);
printf("(long double)%f = %Lf\n", a, la);
printf("a=%016llx\n", *(long long *)&a);
printf("la=%016llx %04x\n", *(long long *)&la,
*(unsigned short *)((char *)(&la) + 8));
/* test all roundings */
asm volatile ("fstcw %0" : "=m" (fpuc));
for(i=0;i<4;i++) {
int16_t tmp = (fpuc & ~0x0c00) | (i << 10);
asm volatile ("fldcw %0" : : "m" (tmp));
wa=0;//asm volatile ("fist %0" : "=m" (wa) : "t" (a));
asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
asm volatile ("fldcw %0" : : "m" (fpuc));
printf("(short)a = %d\n", wa);
printf("(int)a = %d\n", ia);
printf("(int64_t)a = %lld\n", (long long int)lla);
printf("rint(a) = %f\n", ra);
}
}
#define TEST(N) \
asm("fld" #N : "=t" (a)); \
printf("fld" #N "= %f\n", a);
void test_fconst(void)
{
double a;
TEST(1);
TEST(l2t);
TEST(l2e);
TEST(pi);
TEST(lg2);
TEST(ln2);
TEST(z);
}
void test_fbcd(double a)
{
unsigned short bcd[5];
double b;
asm("fbstp %0" : "=m" (bcd[0]) : "t" (a) : "st");
asm("fbld %1" : "=t" (b) : "m" (bcd[0]));
printf("a=%f bcd=%04x%04x%04x%04x%04x b=%f\n",
a, bcd[4], bcd[3], bcd[2], bcd[1], bcd[0], b);
}
#define TEST_ENV(env, save, restore)\
{\
memset((env), 0xaa, sizeof(*(env)));\
for(i=0;i<5;i++)\
asm volatile ("fldl %0" : : "m" (dtab[i]));\
asm(save " %0\n" : : "m" (*(env)));\
asm(restore " %0\n": : "m" (*(env)));\
for(i=0;i<5;i++)\
asm volatile ("fstpl %0" : "=m" (rtab[i]));\
for(i=0;i<5;i++)\
printf("res[%d]=%f\n", i, rtab[i]);\
printf("fpuc=%04x fpus=%04x fptag=%04x\n",\
(env)->fpuc,\
(env)->fpus & 0xff00,\
(env)->fptag);\
}
void test_fenv(void)
{
struct __attribute__((packed)) {
uint16_t fpuc;
uint16_t dummy1;
uint16_t fpus;
uint16_t dummy2;
uint16_t fptag;
uint16_t dummy3;
uint32_t ignored[4];
long double fpregs[8];
} float_env32;
struct __attribute__((packed)) {
uint16_t fpuc;
uint16_t fpus;
uint16_t fptag;
uint16_t ignored[4];
long double fpregs[8];
} float_env16;
double dtab[8];
double rtab[8];
int i;
for(i=0;i<8;i++)
dtab[i] = i + 1;
TEST_ENV(&float_env16, "data16 fnstenv", "data16 fldenv");
TEST_ENV(&float_env16, "data16 fnsave", "data16 frstor");
TEST_ENV(&float_env32, "fnstenv", "fldenv");
TEST_ENV(&float_env32, "fnsave", "frstor");
/* test for ffree */
for(i=0;i<5;i++)
asm volatile ("fldl %0" : : "m" (dtab[i]));
asm volatile("ffree %st(2)");
asm volatile ("fnstenv %0\n" : : "m" (float_env32));
asm volatile ("fninit");
printf("fptag=%04x\n", float_env32.fptag);
}
#define TEST_FCMOV(a, b, eflags, CC)\
{\
double res;\
asm("pushq %3\n"\
"popfq\n"\
"fcmov" CC " %2, %0\n"\
: "=t" (res)\
: "0" (a), "u" (b), "g" ((long long int)eflags));\
printf("fcmov%s eflags=0x%04llx-> %f\n", \
CC, (long long int)eflags, res);\
}
void test_fcmov(void)
{
double a, b;
long long int eflags, i;
a = 1.0;
b = 2.0;
for(i = 0; i < 4; i++) {
eflags = 0;
if (i & 1)
eflags |= CC_C;
if (i & 2)
eflags |= CC_Z;
TEST_FCMOV(a, b, eflags, "b");
TEST_FCMOV(a, b, eflags, "e");
TEST_FCMOV(a, b, eflags, "be");
TEST_FCMOV(a, b, eflags, "nb");
TEST_FCMOV(a, b, eflags, "ne");
TEST_FCMOV(a, b, eflags, "nbe");
}
TEST_FCMOV(a, b, 0, "u");
TEST_FCMOV(a, b, CC_P, "u");
TEST_FCMOV(a, b, 0, "nu");
TEST_FCMOV(a, b, CC_P, "nu");
}
void test_floats(void)
{
test_fops(2, 3);
test_fops(1.4, -5);
test_fcmp(2, -1);
test_fcmp(2, 2);
test_fcmp(2, 3);
test_fcvt(0.5);
test_fcvt(-0.5);
test_fcvt(1.0/7.0);
test_fcvt(-1.0/9.0);
test_fcvt(32768);
test_fcvt(-1e20);
test_fconst();
}
int main ( void )
{
test_floats();
return 0;
}
@@ -0,0 +1,173 @@
a=2.000000 b=3.000000 a+b=5.000000
a=2.000000 b=3.000000 a-b=-1.000000
a=2.000000 b=3.000000 a*b=6.000000
a=2.000000 b=3.000000 a/b=0.666667
a=2.000000 sqrt(a)=1.414214
a=2.000000 sin(a)=0.909297
a=2.000000 cos(a)=-0.416147
a=2.000000 tan(a)=-2.185040
a=2.000000 log(a)=0.693147
a=2.000000 exp(a)=7.389056
a=2.000000 b=3.000000 atan2(a, b)=0.588003
a=2.000000 asin(sin(a))=1.141593
a=2.000000 acos(cos(a))=2.000000
a=2.000000 atan(tan(a))=-1.141593
a=1.400000 b=-5.000000 a+b=-3.600000
a=1.400000 b=-5.000000 a-b=6.400000
a=1.400000 b=-5.000000 a*b=-7.000000
a=1.400000 b=-5.000000 a/b=-0.280000
a=1.400000 sqrt(a)=1.183216
a=1.400000 sin(a)=0.985450
a=1.400000 cos(a)=0.169967
a=1.400000 tan(a)=5.797884
a=1.400000 log(a)=0.336472
a=1.400000 exp(a)=4.055200
a=1.400000 b=-5.000000 atan2(a, b)=2.868584
a=1.400000 asin(sin(a))=1.400000
a=1.400000 acos(cos(a))=1.400000
a=1.400000 atan(tan(a))=1.400000
(2.000000<-1.000000)=0
(2.000000<=-1.000000)=0
(2.000000==-1.000000)=0
(2.000000>-1.000000)=1
(2.000000<=-1.000000)=1
fcomi(2.000000 -1.000000)=00000000
(2.000000<2.000000)=0
(2.000000<=2.000000)=1
(2.000000==2.000000)=1
(2.000000>2.000000)=0
(2.000000<=2.000000)=1
fcomi(2.000000 2.000000)=00000040
(2.000000<3.000000)=1
(2.000000<=3.000000)=1
(2.000000==3.000000)=0
(2.000000>3.000000)=0
(2.000000<=3.000000)=0
fcomi(2.000000 3.000000)=00000001
(float)5.000000e-01 = 5.000000e-01
(long double)0.500000 = 0.500000
a=3fe0000000000000
la=8000000000000000 3ffe
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(short)a = 0
(int)a = 1
(int64_t)a = 1
rint(a) = 1.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(float)-5.000000e-01 = -5.000000e-01
(long double)-0.500000 = -0.500000
a=bfe0000000000000
la=8000000000000000 bffe
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(short)a = 0
(int)a = -1
(int64_t)a = -1
rint(a) = -1.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(float)1.428571e-01 = 1.428571e-01
(long double)0.142857 = 0.142857
a=3fc2492492492492
la=9249249249249000 3ffc
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(short)a = 0
(int)a = 1
(int64_t)a = 1
rint(a) = 1.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = 0.000000
(float)-1.111111e-01 = -1.111111e-01
(long double)-0.111111 = -0.111111
a=bfbc71c71c71c71c
la=e38e38e38e38e000 bffb
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(short)a = 0
(int)a = -1
(int64_t)a = -1
rint(a) = -1.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(short)a = 0
(int)a = 0
(int64_t)a = 0
rint(a) = -0.000000
(float)3.276800e+04 = 3.276800e+04
(long double)32768.000000 = 32768.000000
a=40e0000000000000
la=8000000000000000 400e
(short)a = 0
(int)a = 32768
(int64_t)a = 32768
rint(a) = 32768.000000
(short)a = 0
(int)a = 32768
(int64_t)a = 32768
rint(a) = 32768.000000
(short)a = 0
(int)a = 32768
(int64_t)a = 32768
rint(a) = 32768.000000
(short)a = 0
(int)a = 32768
(int64_t)a = 32768
rint(a) = 32768.000000
(float)-1.000000e+20 = -1.000000e+20
(long double)-100000000000000000000.000000 = -100000000000000000000.000000
a=c415af1d78b58c40
la=ad78ebc5ac620000 c041
(short)a = 0
(int)a = -2147483648
(int64_t)a = -9223372036854775808
rint(a) = -100000000000000000000.000000
(short)a = 0
(int)a = -2147483648
(int64_t)a = -9223372036854775808
rint(a) = -100000000000000000000.000000
(short)a = 0
(int)a = -2147483648
(int64_t)a = -9223372036854775808
rint(a) = -100000000000000000000.000000
(short)a = 0
(int)a = -2147483648
(int64_t)a = -9223372036854775808
rint(a) = -100000000000000000000.000000
fld1= 1.000000
fldl2t= 3.321928
fldl2e= 1.442695
fldpi= 3.141593
fldlg2= 0.301030
fldln2= 0.693147
fldz= 0.000000
@@ -0,0 +1,3 @@
prereq: test -e more_x87_fp
prog: more_x87_fp
vgopts: -q
@@ -0,0 +1,577 @@
sh-mem-vec128: config: little-endian, 64-bit word size
20537 136 171 75 38 63 139 23 5 110 66 421 194 86 232 115
56 198 303 65 285 137 309 203 147 37 179 137 65 181 379 118
91 235 54 135 110 40 362 74 146 108 159 174 313 106 292 271
183 65 277 34 250 172 283 111 141 30 26 15 184 93 79 99
75 89 153 157 9 113 189 58 90 31 81 79 133 132 61 113
282 15 119 12 57 361 14 250 93 116 226 215 229 275 186 126
209 371 84 74 93 159 286 179 84 112 60 137 116 117 394 217
77 133 197 265 72 43 280 26 604 47 194 171 199 411 123 112
281 26 47 64 236 89 223 86 68 125 47 391 18 171 124 110
59 135 143 240 73 242 72 59 345 20 46 415 77 87 34 125
152 85 107 117 334 183 8 131 63 70 27 238 6 181 71 108
242 542 53 94 50 86 181 173 141 125 33 75 409 38 109 70
52 179 48 94 212 60 330 150 147 26 462 307 88 171 85 76
108 108 296 253 152 124 196 227 116 12 606 61 197 120 94 269
121 38 37 167 138 92 172 234 138 67 96 19 346 10 56 241
142 130 85 495 65 176 87 140 46 124 70 100 78 142 270 22165
160000 copies, 30739 d_aligned, 30741 s_aligned, 7092 both_aligned
0 failures
Expect 2 x no error
Expect 2 x error
Invalid read of size 16
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Expect 2 x no error
Expect 2 x error
Invalid read of size 16
...
Address 0x........ is 79,985 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 79,993 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
------ PL Aligned case with 0 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 1 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 2 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 3 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 4 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 5 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 6 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 7 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 8 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 9 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 10 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 11 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 12 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 13 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 14 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 15 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddd
------ PL Unaligned case with 0 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 1 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 2 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 3 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 4 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 5 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 6 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 7 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 8 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 9 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 10 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 11 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 12 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 13 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 14 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 15 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddd
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
total heap usage: 33 allocs, 33 frees, 82,048 bytes allocated
For a detailed leak analysis, rerun with: --leak-check=full
For counts of detected and suppressed errors, rerun with: -v
Use --track-origins=yes to see where uninitialised values come from
ERROR SUMMARY: 66 errors from 66 contexts (suppressed: 0 from 0)
@@ -0,0 +1,3 @@
prog: sh-mem-vec128
args: -q
vgopts: --partial-loads-ok=no
@@ -0,0 +1,468 @@
sh-mem-vec128: config: little-endian, 64-bit word size
20537 136 171 75 38 63 139 23 5 110 66 421 194 86 232 115
56 198 303 65 285 137 309 203 147 37 179 137 65 181 379 118
91 235 54 135 110 40 362 74 146 108 159 174 313 106 292 271
183 65 277 34 250 172 283 111 141 30 26 15 184 93 79 99
75 89 153 157 9 113 189 58 90 31 81 79 133 132 61 113
282 15 119 12 57 361 14 250 93 116 226 215 229 275 186 126
209 371 84 74 93 159 286 179 84 112 60 137 116 117 394 217
77 133 197 265 72 43 280 26 604 47 194 171 199 411 123 112
281 26 47 64 236 89 223 86 68 125 47 391 18 171 124 110
59 135 143 240 73 242 72 59 345 20 46 415 77 87 34 125
152 85 107 117 334 183 8 131 63 70 27 238 6 181 71 108
242 542 53 94 50 86 181 173 141 125 33 75 409 38 109 70
52 179 48 94 212 60 330 150 147 26 462 307 88 171 85 76
108 108 296 253 152 124 196 227 116 12 606 61 197 120 94 269
121 38 37 167 138 92 172 234 138 67 96 19 346 10 56 241
142 130 85 495 65 176 87 140 46 124 70 100 78 142 270 22165
160000 copies, 30739 d_aligned, 30741 s_aligned, 7092 both_aligned
0 failures
Expect 2 x no error
Expect 2 x error
Invalid read of size 16
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Expect 2 x no error
Expect 2 x error
Invalid read of size 16
...
Address 0x........ is 79,985 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 79,993 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
------ PL Aligned case with 0 leading acc+def bytes ------
UUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 1 leading acc+def bytes ------
dUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 2 leading acc+def bytes ------
ddUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 3 leading acc+def bytes ------
dddUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 4 leading acc+def bytes ------
ddddUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 5 leading acc+def bytes ------
dddddUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 6 leading acc+def bytes ------
ddddddUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 7 leading acc+def bytes ------
dddddddUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 8 leading acc+def bytes ------
ddddddddUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 9 leading acc+def bytes ------
dddddddddUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 10 leading acc+def bytes ------
ddddddddddUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 11 leading acc+def bytes ------
dddddddddddUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 12 leading acc+def bytes ------
ddddddddddddUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 13 leading acc+def bytes ------
dddddddddddddUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 14 leading acc+def bytes ------
ddddddddddddddUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 15 leading acc+def bytes ------
dddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 0 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 1 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 2 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 3 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 4 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 5 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 6 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 7 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 8 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 9 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 10 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 11 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 12 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 13 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 14 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 15 leading acc+def bytes ------
Invalid read of size 16
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddd
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
total heap usage: 33 allocs, 33 frees, 82,048 bytes allocated
For a detailed leak analysis, rerun with: --leak-check=full
For counts of detected and suppressed errors, rerun with: -v
Use --track-origins=yes to see where uninitialised values come from
ERROR SUMMARY: 51 errors from 51 contexts (suppressed: 0 from 0)
@@ -0,0 +1,3 @@
prog: sh-mem-vec128
args: -q
vgopts: --partial-loads-ok=yes
@@ -0,0 +1,18 @@
// Set up the 128-bit shadow memory test, by defining the
// required vector-copy function, and then including the
// template.
#define VECTOR_BYTES 16
static __attribute__((noinline))
void vector_copy ( void* dst, void* src )
{
__asm__ __volatile__(
"movups (%1), %%xmm7 ; movups %%xmm7, (%0)"
: /*OUT*/ : /*IN*/ "r"(dst), "r"(src) : "memory","xmm7"
);
}
// Include the test body, which refers to the above function
#include "../common/sh-mem-vec128.tmpl.c"
@@ -0,0 +1,942 @@
sh-mem-vec256: config: little-endian, 64-bit word size
19543 109 126 31 206 54 112 34 102 152 335 1 36 0 23 33
203 7 50 141 18 261 24 189 248 15 11 0 145 304 228 457
4 367 20 32 269 3 319 51 448 85 88 166 21 228 238 41
298 39 98 35 90 64 0 254 817 91 328 214 163 64 0 266
214 347 234 32 536 233 13 171 91 42 332 189 177 14 81 142
313 400 77 4 48 114 3 113 324 87 525 413 205 184 126 294
182 0 244 88 0 254 45 134 226 248 0 27 262 0 173 244
494 165 241 116 217 32 112 0 117 335 230 79 193 174 60 243
19 94 163 16 59 184 1 79 247 214 378 142 239 253 0 61
50 48 0 304 196 109 109 186 9 389 389 7 329 157 283 234
4 724 74 247 99 92 35 376 242 54 309 549 23 264 61 143
87 0 22 96 148 563 411 54 288 34 2 14 33 88 73 339
122 18 347 145 208 251 266 265 3 261 146 207 831 213 146 59
119 18 117 303 132 315 296 70 210 707 138 537 29 492 86 188
292 6 312 158 32 107 0 259 53 379 45 115 38 324 36 32
0 264 235 135 192 262 40 0 401 38 157 20 0 160 325 18430
160000 copies, 26427 d_aligned, 26424 s_aligned, 6016 both_aligned
0 failures
Expect 2 x no error
Expect 2 x error
Invalid read of size 32
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Expect 2 x no error
Expect 2 x error
Invalid read of size 32
...
Address 0x........ is 79,969 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 79,993 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
------ PL Aligned case with 0 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 1 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 2 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 3 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 4 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 5 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 6 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 7 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 8 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 9 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 10 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 11 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 12 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 13 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 14 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 15 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 16 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 17 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 18 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 19 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 20 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 21 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 22 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 23 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 24 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 25 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 26 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 27 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 28 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 29 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddddddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 30 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 31 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 0 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddddd
------ PL Unaligned case with 0 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 1 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 2 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 3 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 4 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 5 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 6 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 7 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 8 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 9 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 10 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 11 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 12 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 13 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 14 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 15 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 16 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddUddUddUddUddUdd
More than 100 errors detected. Subsequent errors
will still be recorded, but in less detail than before.
------ PL Unaligned case with 17 leading acc+def bytes ------
ddddddddddddddddddUddUddUddUddUd
------ PL Unaligned case with 18 leading acc+def bytes ------
dddddddddddddddddddUddUddUddUddU
------ PL Unaligned case with 19 leading acc+def bytes ------
ddddddddddddddddddddUddUddUddUdd
------ PL Unaligned case with 20 leading acc+def bytes ------
dddddddddddddddddddddUddUddUddUd
------ PL Unaligned case with 21 leading acc+def bytes ------
ddddddddddddddddddddddUddUddUddU
------ PL Unaligned case with 22 leading acc+def bytes ------
dddddddddddddddddddddddUddUddUdd
------ PL Unaligned case with 23 leading acc+def bytes ------
ddddddddddddddddddddddddUddUddUd
------ PL Unaligned case with 24 leading acc+def bytes ------
dddddddddddddddddddddddddUddUddU
------ PL Unaligned case with 25 leading acc+def bytes ------
ddddddddddddddddddddddddddUddUdd
------ PL Unaligned case with 26 leading acc+def bytes ------
dddddddddddddddddddddddddddUddUd
------ PL Unaligned case with 27 leading acc+def bytes ------
ddddddddddddddddddddddddddddUddU
------ PL Unaligned case with 28 leading acc+def bytes ------
dddddddddddddddddddddddddddddUdd
------ PL Unaligned case with 29 leading acc+def bytes ------
ddddddddddddddddddddddddddddddUd
------ PL Unaligned case with 30 leading acc+def bytes ------
dddddddddddddddddddddddddddddddU
------ PL Unaligned case with 31 leading acc+def bytes ------
dddddddddddddddddddddddddddddddd
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
total heap usage: 65 allocs, 65 frees, 84,096 bytes allocated
For a detailed leak analysis, rerun with: --leak-check=full
For counts of detected and suppressed errors, rerun with: -v
Use --track-origins=yes to see where uninitialised values come from
ERROR SUMMARY: 130 errors from 100 contexts (suppressed: 0 from 0)
@@ -0,0 +1,4 @@
prog: sh-mem-vec256
prereq: ../../../tests/x86_amd64_features amd64-avx
args: -q
vgopts: --partial-loads-ok=no
@@ -0,0 +1,868 @@
sh-mem-vec256: config: little-endian, 64-bit word size
19543 109 126 31 206 54 112 34 102 152 335 1 36 0 23 33
203 7 50 141 18 261 24 189 248 15 11 0 145 304 228 457
4 367 20 32 269 3 319 51 448 85 88 166 21 228 238 41
298 39 98 35 90 64 0 254 817 91 328 214 163 64 0 266
214 347 234 32 536 233 13 171 91 42 332 189 177 14 81 142
313 400 77 4 48 114 3 113 324 87 525 413 205 184 126 294
182 0 244 88 0 254 45 134 226 248 0 27 262 0 173 244
494 165 241 116 217 32 112 0 117 335 230 79 193 174 60 243
19 94 163 16 59 184 1 79 247 214 378 142 239 253 0 61
50 48 0 304 196 109 109 186 9 389 389 7 329 157 283 234
4 724 74 247 99 92 35 376 242 54 309 549 23 264 61 143
87 0 22 96 148 563 411 54 288 34 2 14 33 88 73 339
122 18 347 145 208 251 266 265 3 261 146 207 831 213 146 59
119 18 117 303 132 315 296 70 210 707 138 537 29 492 86 188
292 6 312 158 32 107 0 259 53 379 45 115 38 324 36 32
0 264 235 135 192 262 40 0 401 38 157 20 0 160 325 18430
160000 copies, 26427 d_aligned, 26424 s_aligned, 6016 both_aligned
0 failures
Expect 2 x no error
Expect 2 x error
Invalid read of size 32
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 1 bytes before a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Expect 2 x no error
Expect 2 x error
Invalid read of size 32
...
Address 0x........ is 79,969 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
Invalid write of size 8
...
Address 0x........ is 79,993 bytes inside a block of size 80,000 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
------ PL Aligned case with 0 leading acc+def bytes ------
UUdUUdUUdUUdUUdUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 1 leading acc+def bytes ------
dUUdUUdUUdUUdUUdUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 2 leading acc+def bytes ------
ddUUdUUdUUdUUdUUdUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 3 leading acc+def bytes ------
dddUUdUUdUUdUUdUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 4 leading acc+def bytes ------
ddddUUdUUdUUdUUdUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 5 leading acc+def bytes ------
dddddUUdUUdUUdUUdUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 6 leading acc+def bytes ------
ddddddUUdUUdUUdUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 7 leading acc+def bytes ------
dddddddUUdUUdUUdUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 8 leading acc+def bytes ------
ddddddddUUdUUdUUdUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 9 leading acc+def bytes ------
dddddddddUUdUUdUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 10 leading acc+def bytes ------
ddddddddddUUdUUdUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 11 leading acc+def bytes ------
dddddddddddUUdUUdUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 12 leading acc+def bytes ------
ddddddddddddUUdUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 13 leading acc+def bytes ------
dddddddddddddUUdUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 14 leading acc+def bytes ------
ddddddddddddddUUdUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 15 leading acc+def bytes ------
dddddddddddddddUUdUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 16 leading acc+def bytes ------
ddddddddddddddddUUdUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 17 leading acc+def bytes ------
dddddddddddddddddUUdUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 18 leading acc+def bytes ------
ddddddddddddddddddUUdUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 19 leading acc+def bytes ------
dddddddddddddddddddUUdUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 20 leading acc+def bytes ------
ddddddddddddddddddddUUdUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 21 leading acc+def bytes ------
dddddddddddddddddddddUUdUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 22 leading acc+def bytes ------
ddddddddddddddddddddddUUdUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 23 leading acc+def bytes ------
dddddddddddddddddddddddUUdUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 24 leading acc+def bytes ------
ddddddddddddddddddddddddUUdUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 25 leading acc+def bytes ------
dddddddddddddddddddddddddUUdUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 26 leading acc+def bytes ------
ddddddddddddddddddddddddddUUdUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 27 leading acc+def bytes ------
dddddddddddddddddddddddddddUUdUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 28 leading acc+def bytes ------
ddddddddddddddddddddddddddddUUdU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 29 leading acc+def bytes ------
dddddddddddddddddddddddddddddUUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 30 leading acc+def bytes ------
ddddddddddddddddddddddddddddddUU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Aligned case with 31 leading acc+def bytes ------
dddddddddddddddddddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 0 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dUddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 1 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddUddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 2 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddUddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 3 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddUddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 4 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddUddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 5 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddUddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 6 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddUddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 7 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddUddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 8 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddUddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 9 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddUddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 10 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddUddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 11 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddUddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 12 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddUddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 13 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddUddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 14 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddUddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 15 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddUddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 16 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddUddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 17 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddUddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 18 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddUddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 19 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddUddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 20 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddUddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 21 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddUddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 22 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddUddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 23 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddUddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 24 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddUddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 25 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddUddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 26 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddUddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 27 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddddUddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 28 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddUdd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 29 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
ddddddddddddddddddddddddddddddUd
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 30 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddddU
Conditional jump or move depends on uninitialised value(s)
...
------ PL Unaligned case with 31 leading acc+def bytes ------
Invalid read of size 32
...
Address 0x........ is 1 bytes inside a block of size 64 alloc'd
at 0x........: memalign (vg_replace_malloc.c:...)
by 0x........: posix_memalign (vg_replace_malloc.c:...)
...
dddddddddddddddddddddddddddddddd
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
total heap usage: 65 allocs, 65 frees, 84,096 bytes allocated
For a detailed leak analysis, rerun with: --leak-check=full
For counts of detected and suppressed errors, rerun with: -v
Use --track-origins=yes to see where uninitialised values come from
ERROR SUMMARY: 99 errors from 99 contexts (suppressed: 0 from 0)
@@ -0,0 +1,4 @@
prog: sh-mem-vec256
prereq: ../../../tests/x86_amd64_features amd64-avx
args: -q
vgopts: --partial-loads-ok=yes
@@ -0,0 +1,21 @@
// Set up the 256-bit shadow memory test, by defining the
// required vector-copy function, and then including the
// template.
#define VECTOR_BYTES 32
static __attribute__((noinline))
void vector_copy ( void* dst, void* src )
{
/* Note: Verions of GCC through 4.8.1 do not allow "ymm7" in the
clobber list. (See http://stackoverflow.com/a/15767111/768469).
Simulate it with "xmm7". */
__asm__ __volatile__(
"vmovupd (%1), %%ymm7 ; vmovupd %%ymm7, (%0)"
: /*OUT*/ : /*IN*/ "r"(dst), "r"(src) : "memory","xmm7"
);
}
// Include the test body, which refers to the above function
#include "../common/sh-mem-vec128.tmpl.c"
@@ -0,0 +1,623 @@
/* A program to test that SSE/SSE2 insns do not read memory they
should not. Covers insns of the form OP %xmm, %xmm and OP memory,
%xmm only. */
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "tests/malloc.h"
#include <string.h>
typedef unsigned char V128[16];
typedef unsigned int UInt;
typedef signed int Int;
typedef unsigned char UChar;
typedef
struct {
V128 arg1;
V128 arg2;
V128 res;
}
RRArgs;
typedef
struct {
V128 arg1;
V128 res;
}
RMArgs;
static UChar randUChar ( void )
{
static UInt seed = 80021;
seed = 1103515245 * seed + 12345;
return (seed >> 17) & 0xFF;
}
static void randomise ( UChar* p, Int n )
{
Int i;
for (i = 0; i < n; i++)
p[i] = randUChar();
}
static void randV128 ( V128* v )
{
Int i;
for (i = 0; i < 16; i++)
(*v)[i] = randUChar();
}
static void randRRArgs ( RRArgs* rra )
{
randV128(&rra->arg1);
randV128(&rra->arg2);
randV128(&rra->res);
}
static void randRMArgs ( RMArgs* rra )
{
randV128(&rra->arg1);
randV128(&rra->res);
}
static void showV128 ( V128* v )
{
Int i;
for (i = 0; i < 16; i++)
printf("%02x", (Int)(*v)[i]);
}
static void showMaskedV128 ( V128* v, V128* mask )
{
Int i;
for (i = 0; i < 16; i++)
printf("%02x", (Int)( ((*v)[i]) & ((*mask)[i]) ));
}
static void showRR ( char* op, RRArgs* rra, V128* rmask )
{
printf("r %10s ", op);
showV128(&rra->arg1);
printf(" ");
showV128(&rra->arg2);
printf(" ");
showMaskedV128(&rra->res, rmask);
printf("\n");
}
static void showRM ( char* op, RMArgs* rra, UChar* mem, Int nMem, V128* rmask )
{
Int i;
assert(nMem == 4 || nMem == 8 || nMem == 16 || nMem==0);
printf("m %10s ", op);
for (i = 0; i < nMem; i++)
printf("%02x", (Int)mem[i]);
printf(" ");
showV128(&rra->arg1);
printf(" ");
showMaskedV128(&rra->res, rmask );
printf("\n");
}
#define Wrapper_RegReg(OP) \
void r_r_##OP ( RRArgs* p ) \
{ \
__asm__ __volatile__("\n" \
"\tmovups 0(%0), %%xmm6\n" \
"\tmovups 16(%0), %%xmm7\n" \
"\t" #OP " %%xmm6, %%xmm7\n" \
"\tmovups %%xmm7, 32(%0)\n" \
: \
: "r" (p) \
: "memory", "xmm6", "xmm7", "cc" \
); \
}
#define Wrapper_RegMem(OP) \
void r_m_##OP ( RMArgs* p, void* mem ) \
{ \
__asm__ __volatile__("\n" \
"\tmovups 0(%0), %%xmm7\n" \
"\t" #OP " 0(%1), %%xmm7\n" \
"\tmovups %%xmm7, 16(%0)\n" \
: \
: "r" (p), "r" (mem) \
: "memory", "xmm7", "cc" \
); \
}
#define TEST_INSN(res_mask,mem_size,insn) \
\
Wrapper_RegReg(insn) \
Wrapper_RegMem(insn) \
\
void do_##insn ( void ) \
{ \
Int i; \
UChar* buf; \
RRArgs rargs __attribute__((aligned(16))); \
RMArgs margs __attribute__((aligned(16))); \
for (i = 0; i < 5; i++) { \
randRRArgs(&rargs); \
r_r_##insn(&rargs); \
showRR(#insn, &rargs, res_mask); \
} \
for (i = 0; i < 5; i++) { \
randRMArgs(&margs); \
buf = memalign16(mem_size); \
randomise(buf,mem_size); \
r_m_##insn(&margs,buf); \
showRM(#insn, &margs, buf, mem_size, res_mask);\
free(buf); \
} \
}
/* Note: these are little endian. Hence first byte is the least
significant byte of lane zero. */
/* Mask for insns where all result bits are non-approximated. */
static V128 AllMask = { 0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF };
/* Mark for insns which produce approximated vector short results. */
static V128 ApproxPS = { 0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF,
0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF };
/* Mark for insns which produce approximated scalar short results. */
static V128 ApproxSS = { 0x00,0x00,0x80,0xFF, 0xFF,0xFF,0xFF,0xFF,
0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF };
#define PD 16
#define SD 8
#define PS 16
#define SS 4
/* ------------------------ SSE1 ------------------------ */
TEST_INSN( &AllMask, PS,addps)
TEST_INSN( &AllMask, SS,addss)
TEST_INSN( &AllMask, PS,andnps)
TEST_INSN( &AllMask, PS,andps)
TEST_INSN( &AllMask, PS,cmpeqps)
TEST_INSN( &AllMask, SS,cmpeqss)
TEST_INSN( &AllMask, PS,cmpleps)
TEST_INSN( &AllMask, SS,cmpless)
TEST_INSN( &AllMask, PS,cmpltps)
TEST_INSN( &AllMask, SS,cmpltss)
TEST_INSN( &AllMask, PS,cmpneqps)
TEST_INSN( &AllMask, SS,cmpneqss)
TEST_INSN( &AllMask, PS,cmpnleps)
TEST_INSN( &AllMask, SS,cmpnless)
TEST_INSN( &AllMask, PS,cmpnltps)
TEST_INSN( &AllMask, SS,cmpnltss)
TEST_INSN( &AllMask, PS,cmpordps)
TEST_INSN( &AllMask, SS,cmpordss)
TEST_INSN( &AllMask, PS,cmpunordps)
TEST_INSN( &AllMask, SS,cmpunordss)
TEST_INSN( &AllMask, SS,comiss)
//TEST_INSN( &AllMask, 0,cvtpi2ps)
//TEST_INSN( &AllMask, 0,cvtps2pi)
//TEST_INSN( &AllMask, 0,cvtsi2ss)
//TEST_INSN( &AllMask, 0,cvtss2si)
//TEST_INSN( &AllMask, 0,cvttps2pi)
//TEST_INSN( &AllMask, 0,cvttss2si)
TEST_INSN( &AllMask, PS,divps)
TEST_INSN( &AllMask, SS,divss)
TEST_INSN( &AllMask, PS,maxps)
TEST_INSN( &AllMask, SS,maxss)
TEST_INSN( &AllMask, PS,minps)
TEST_INSN( &AllMask, SS,minss)
TEST_INSN( &AllMask, 16,movaps)
//TEST_INSN( &AllMask, 0,movhlps)
//TEST_INSN( &AllMask, 0,movhps)
//TEST_INSN( &AllMask, 0,movlhps)
//TEST_INSN( &AllMask, 0,movlps)
//TEST_INSN( &AllMask, 0,movmskps)
//TEST_INSN( &AllMask, 0,movntps)
//TEST_INSN( &AllMask, 0,movntq)
TEST_INSN( &AllMask, 4,movss)
TEST_INSN( &AllMask, 16,movups)
TEST_INSN( &AllMask, PS,mulps)
TEST_INSN( &AllMask, SS,mulss)
TEST_INSN( &AllMask, PS,orps)
//TEST_INSN( &AllMask, 0,pavgb) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pavgw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pextrw)
//TEST_INSN( &AllMask, 0,pinsrw)
//TEST_INSN( &AllMask, 0,pmaxsw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pmaxub) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pminsw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pminub) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pmovmskb)
//TEST_INSN( &AllMask, 0,pmulhuw) -- dup with sse2?
TEST_INSN( &AllMask, 16,psadbw) // -- XXXXXXXXXXXXXXXX sse2 (xmm variant) not implemented!
//TEST_INSN( &AllMask, 0,pshufw)
TEST_INSN(&ApproxPS, PS,rcpps)
TEST_INSN(&ApproxSS, SS,rcpss)
TEST_INSN(&ApproxPS, PS,rsqrtps)
TEST_INSN(&ApproxSS, SS,rsqrtss)
//TEST_INSN( &AllMask, PS,shufps)
TEST_INSN( &AllMask, PS,sqrtps)
TEST_INSN( &AllMask, SS,sqrtss)
TEST_INSN( &AllMask, PS,subps)
TEST_INSN( &AllMask, SS,subss)
TEST_INSN( &AllMask, SS,ucomiss)
TEST_INSN( &AllMask, PS,unpckhps)
TEST_INSN( &AllMask, PS,unpcklps)
TEST_INSN( &AllMask, PS,xorps)
/* ------------------------ SSE2 ------------------------ */
TEST_INSN( &AllMask, PD,addpd)
TEST_INSN( &AllMask, SD,addsd)
TEST_INSN( &AllMask, PD,andnpd)
TEST_INSN( &AllMask, PD,andpd)
TEST_INSN( &AllMask, PD,cmpeqpd)
TEST_INSN( &AllMask, SD,cmpeqsd)
TEST_INSN( &AllMask, PD,cmplepd)
TEST_INSN( &AllMask, SD,cmplesd)
TEST_INSN( &AllMask, PD,cmpltpd)
TEST_INSN( &AllMask, SD,cmpltsd)
TEST_INSN( &AllMask, PD,cmpneqpd)
TEST_INSN( &AllMask, SD,cmpneqsd)
TEST_INSN( &AllMask, PD,cmpnlepd)
TEST_INSN( &AllMask, SD,cmpnlesd)
TEST_INSN( &AllMask, PD,cmpnltpd)
TEST_INSN( &AllMask, SD,cmpnltsd)
TEST_INSN( &AllMask, PD,cmpordpd)
TEST_INSN( &AllMask, SD,cmpordsd)
TEST_INSN( &AllMask, PD,cmpunordpd)
TEST_INSN( &AllMask, SD,cmpunordsd)
TEST_INSN( &AllMask, SD,comisd)
TEST_INSN( &AllMask, 8,cvtdq2pd)
TEST_INSN( &AllMask, 16,cvtdq2ps)
TEST_INSN( &AllMask, 16,cvtpd2dq)
//TEST_INSN( &AllMask, 0,cvtpd2pi)
TEST_INSN( &AllMask, 16,cvtpd2ps) /* reads 16 */
//TEST_INSN( &AllMask, 0,cvtpi2pd)
TEST_INSN( &AllMask, 16,cvtps2dq) /* reads 16 */
TEST_INSN( &AllMask, 8,cvtps2pd) /* reads 8 */
//TEST_INSN( &AllMask, 0,cvtsd2si)
TEST_INSN( &AllMask, SD,cvtsd2ss) /* reads SD */
//TEST_INSN( &AllMask, 0,cvtsi2sd)
TEST_INSN( &AllMask, SS,cvtss2sd) /* reads SS */
TEST_INSN( &AllMask, 16,cvttpd2dq)
//TEST_INSN( &AllMask, 0,cvttpd2pi)
TEST_INSN( &AllMask, 16,cvttps2dq)
//TEST_INSN( &AllMask, 0,cvttsd2si)
TEST_INSN( &AllMask, PD,divpd)
TEST_INSN( &AllMask, SD,divsd)
TEST_INSN( &AllMask, PD,maxpd)
TEST_INSN( &AllMask, SD,maxsd)
TEST_INSN( &AllMask, PD,minpd)
TEST_INSN( &AllMask, SD,minsd)
TEST_INSN( &AllMask, PD,movapd)
//TEST_INSN( &AllMask, 8,movd)
//TEST_INSN( &AllMask, 0,movdq2q)
TEST_INSN( &AllMask, 16,movdqa)
TEST_INSN( &AllMask, 16,movdqu)
//TEST_INSN( &AllMask, 16,movhpd)
//TEST_INSN( &AllMask, 16,movlpd)
//TEST_INSN( &AllMask, 0,movmskpd)
//TEST_INSN( &AllMask, 0,movntdq)
//TEST_INSN( &AllMask, 0,movnti)
//TEST_INSN( &AllMask, 0,movntpd)
TEST_INSN( &AllMask, 8,movq)
//TEST_INSN( &AllMask, 0,movq2dq)
TEST_INSN( &AllMask, 8,movsd)
TEST_INSN( &AllMask, 16,movupd)
TEST_INSN( &AllMask, PD,mulpd)
TEST_INSN( &AllMask, SD,mulsd)
TEST_INSN( &AllMask, PD,orpd)
TEST_INSN( &AllMask, 16,packssdw)
TEST_INSN( &AllMask, 16,packsswb)
TEST_INSN( &AllMask, 16,packuswb)
TEST_INSN( &AllMask, 16,paddb)
TEST_INSN( &AllMask, 16,paddd)
TEST_INSN( &AllMask, 16,paddq)
TEST_INSN( &AllMask, 16,paddsb)
TEST_INSN( &AllMask, 16,paddsw)
TEST_INSN( &AllMask, 16,paddusb)
TEST_INSN( &AllMask, 16,paddusw)
TEST_INSN( &AllMask, 16,paddw)
TEST_INSN( &AllMask, 16,pand)
TEST_INSN( &AllMask, 16,pandn)
TEST_INSN( &AllMask, 16,pavgb)
TEST_INSN( &AllMask, 16,pavgw)
TEST_INSN( &AllMask, 16,pcmpeqb)
TEST_INSN( &AllMask, 16,pcmpeqd)
TEST_INSN( &AllMask, 16,pcmpeqw)
TEST_INSN( &AllMask, 16,pcmpgtb)
TEST_INSN( &AllMask, 16,pcmpgtd)
TEST_INSN( &AllMask, 16,pcmpgtw)
//TEST_INSN( &AllMask, 16,pextrw)
//TEST_INSN( &AllMask, 16,pinsrw)
TEST_INSN( &AllMask, 16,pmaxsw)
TEST_INSN( &AllMask, 16,pmaxub)
TEST_INSN( &AllMask, 16,pminsw)
TEST_INSN( &AllMask, 16,pminub)
//TEST_INSN( &AllMask, 0,pmovmskb)
TEST_INSN( &AllMask, 16,pmulhuw)
TEST_INSN( &AllMask, 16,pmulhw)
TEST_INSN( &AllMask, 16,pmullw)
TEST_INSN( &AllMask, 16,pmuludq)
TEST_INSN( &AllMask, 16,por)
//TEST_INSN( &AllMask, 16,pshufd)
//TEST_INSN( &AllMask, 16,pshufhw)
//TEST_INSN( &AllMask, 16,pshuflw)
TEST_INSN( &AllMask, 16,pslld)
//TEST_INSN( &AllMask, 16,pslldq)
TEST_INSN( &AllMask, 16,psllq)
TEST_INSN( &AllMask, 16,psllw)
TEST_INSN( &AllMask, 16,psrad)
TEST_INSN( &AllMask, 16,psraw)
TEST_INSN( &AllMask, 16,psrld)
//TEST_INSN( &AllMask, 16,psrldq)
TEST_INSN( &AllMask, 16,psrlq)
TEST_INSN( &AllMask, 16,psrlw)
TEST_INSN( &AllMask, 16,psubb)
TEST_INSN( &AllMask, 16,psubd)
TEST_INSN( &AllMask, 16,psubq)
TEST_INSN( &AllMask, 16,psubsb)
TEST_INSN( &AllMask, 16,psubsw)
TEST_INSN( &AllMask, 16,psubusb)
TEST_INSN( &AllMask, 16,psubusw)
TEST_INSN( &AllMask, 16,psubw)
TEST_INSN( &AllMask, 16,punpckhbw)
TEST_INSN( &AllMask, 16,punpckhdq)
TEST_INSN( &AllMask, 16,punpckhqdq)
TEST_INSN( &AllMask, 16,punpckhwd)
TEST_INSN( &AllMask, 16,punpcklbw)
TEST_INSN( &AllMask, 16,punpckldq)
TEST_INSN( &AllMask, 16,punpcklqdq)
TEST_INSN( &AllMask, 16,punpcklwd)
TEST_INSN( &AllMask, 16,pxor)
//TEST_INSN( &AllMask, PD,shufpd)
TEST_INSN( &AllMask, PD,sqrtpd)
TEST_INSN( &AllMask, SD,sqrtsd)
TEST_INSN( &AllMask, PD,subpd)
TEST_INSN( &AllMask, SD,subsd)
TEST_INSN( &AllMask, SD,ucomisd)
TEST_INSN( &AllMask, PD,unpckhpd)
TEST_INSN( &AllMask, PD,unpcklpd)
TEST_INSN( &AllMask, PD,xorpd)
int main ( int argc, char** argv )
{
Int sse1 = 0, sse2 = 0;
if (argc == 2 && 0==strcmp(argv[1], "sse1")) {
sse1 = 1;
}
else
if (argc == 2 && 0==strcmp(argv[1], "sse2")) {
sse2 = 1;
}
else
if (argc == 2 && 0==strcmp(argv[1], "all")) {
sse1 = sse2 = 1;
}
else {
fprintf(stderr, "usage: sse_memory [sse1|sse2|all]\n");
return 0;
}
/* ------------------------ SSE1 ------------------------ */
if (sse1) {
do_addps();
do_addss();
do_andnps();
do_andps();
do_cmpeqps();
do_cmpeqss();
do_cmpleps();
do_cmpless();
do_cmpltps();
do_cmpltss();
do_cmpneqps();
do_cmpneqss();
do_cmpnleps();
do_cmpnless();
do_cmpnltps();
do_cmpnltss();
do_cmpordps();
do_cmpordss();
do_cmpunordps();
do_cmpunordss();
do_comiss();
//TEST_INSN( &AllMask, 0,cvtpi2ps)
//TEST_INSN( &AllMask, 0,cvtps2pi)
//TEST_INSN( &AllMask, 0,cvtsi2ss)
//TEST_INSN( &AllMask, 0,cvtss2si)
//TEST_INSN( &AllMask, 0,cvttps2pi)
//TEST_INSN( &AllMask, 0,cvttss2si)
do_divps();
do_divss();
do_maxps();
do_maxss();
do_minps();
do_minss();
do_movaps();
//TEST_INSN( &AllMask, 0,movhlps)
//TEST_INSN( &AllMask, 0,movhps)
//TEST_INSN( &AllMask, 0,movlhps)
//TEST_INSN( &AllMask, 0,movlps)
//TEST_INSN( &AllMask, 0,movmskps)
//TEST_INSN( &AllMask, 0,movntps)
//TEST_INSN( &AllMask, 0,movntq)
do_movss();
do_movups();
do_mulps();
do_mulss();
do_orps();
//TEST_INSN( &AllMask, 0,pavgb) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pavgw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pextrw)
//TEST_INSN( &AllMask, 0,pinsrw)
//TEST_INSN( &AllMask, 0,pmaxsw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pmaxub) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pminsw) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pminub) -- dup with sse2?
//TEST_INSN( &AllMask, 0,pmovmskb)
//TEST_INSN( &AllMask, 0,pmulhuw) -- dup with sse2?
//do_psadbw(); -- XXXXXXXXXXXXXXXX sse2 (xmm variant) not implemented!
//TEST_INSN( &AllMask, 0,pshufw)
do_rcpps();
do_rcpss();
do_rsqrtps();
do_rsqrtss();
//TEST_INSN( &AllMask, PS,shufps)
do_sqrtps();
do_sqrtss();
do_subps();
do_subss();
do_ucomiss();
do_unpckhps();
do_unpcklps();
do_xorps();
}
/* ------------------------ SSE2 ------------------------ */
if (sse2) {
do_addpd();
do_addsd();
do_andnpd();
do_andpd();
do_cmpeqpd();
do_cmpeqsd();
do_cmplepd();
do_cmplesd();
do_cmpltpd();
do_cmpltsd();
do_cmpneqpd();
do_cmpneqsd();
do_cmpnlepd();
do_cmpnlesd();
do_cmpnltpd();
do_cmpnltsd();
do_cmpordpd();
do_cmpordsd();
do_cmpunordpd();
do_cmpunordsd();
do_comisd();
do_cvtdq2pd();
do_cvtdq2ps();
do_cvtpd2dq();
//TEST_INSN( &AllMask, 0,cvtpd2pi)
do_cvtpd2ps();
//TEST_INSN( &AllMask, 0,cvtpi2pd)
do_cvtps2dq();
do_cvtps2pd();
//TEST_INSN( &AllMask, 0,cvtsd2si)
do_cvtsd2ss();
//TEST_INSN( &AllMask, 0,cvtsi2sd)
do_cvtss2sd();
do_cvttpd2dq();
//TEST_INSN( &AllMask, 0,cvttpd2pi)
do_cvttps2dq();
//TEST_INSN( &AllMask, 0,cvttsd2si)
do_divpd();
do_divsd();
do_maxpd();
do_maxsd();
do_minpd();
do_minsd();
do_movapd();
//TEST_INSN( &AllMask, 8,movd)
//TEST_INSN( &AllMask, 0,movdq2q)
do_movdqa();
do_movdqu();
//TEST_INSN( &AllMask, 16,movhpd)
//TEST_INSN( &AllMask, 16,movlpd)
//TEST_INSN( &AllMask, 0,movmskpd)
//TEST_INSN( &AllMask, 0,movntdq)
//TEST_INSN( &AllMask, 0,movnti)
//TEST_INSN( &AllMask, 0,movntpd)
do_movq();
//TEST_INSN( &AllMask, 0,movq2dq)
do_movsd();
do_movupd();
do_mulpd();
do_mulsd();
do_orpd();
do_packssdw();
do_packsswb();
do_packuswb();
do_paddb();
do_paddd();
do_paddq();
do_paddsb();
do_paddsw();
do_paddusb();
do_paddusw();
do_paddw();
do_pand();
do_pandn();
do_pavgb();
do_pavgw();
do_pcmpeqb();
do_pcmpeqd();
do_pcmpeqw();
do_pcmpgtb();
do_pcmpgtd();
do_pcmpgtw();
//TEST_INSN( &AllMask, 16,pextrw)
//TEST_INSN( &AllMask, 16,pinsrw)
do_pmaxsw();
do_pmaxub();
do_pminsw();
do_pminub();
//TEST_INSN( &AllMask, 0,pmovmskb)
do_pmulhuw();
do_pmulhw();
do_pmullw();
do_pmuludq();
do_por();
//TEST_INSN( &AllMask, 16,pshufd)
//TEST_INSN( &AllMask, 16,pshufhw)
//TEST_INSN( &AllMask, 16,pshuflw)
do_pslld();
//TEST_INSN( &AllMask, 16,pslldq)
do_psllq();
do_psllw();
do_psrad();
do_psraw();
do_psrld();
//TEST_INSN( &AllMask, 16,psrldq)
do_psrlq();
do_psrlw();
do_psubb();
do_psubd();
do_psubq();
do_psubsb();
do_psubsw();
do_psubusb();
do_psubusw();
do_psubw();
do_punpckhbw();
do_punpckhdq();
do_punpckhqdq();
do_punpckhwd();
do_punpcklbw();
do_punpckldq();
do_punpcklqdq();
do_punpcklwd();
do_pxor();
//TEST_INSN( &AllMask, PD,shufpd)
do_sqrtpd();
do_sqrtsd();
do_subpd();
do_subsd();
do_ucomisd();
do_unpckhpd();
do_unpcklpd();
do_xorpd();
}
return 0;
}
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,3 @@
prog: sse_memory
vgopts: -q
args: all
@@ -0,0 +1,143 @@
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define JZ_NEXT ".byte 0x74,0x00" /* jz the-next-insn */
int main ( void )
{
char* junk = malloc(48);
assert(junk);
/* --- INTEGER --- */
printf("\nComplain int64\n");
__asm__ __volatile__(
"movq 0(%0), %%rax\n\t"
"movq 8(%0), %%r8\n\t"
"xorq %%r8, %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "r8", "rax", "cc"
);
printf("\nNo complain int64\n");
__asm__ __volatile__(
"movq 0(%0), %%rax\n\t"
"movq 8(%0), %%r8\n\t"
"xorq %%rax, %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "r8", "rax", "cc"
);
/* --- MMX --- */
printf("\nComplain mmx\n");
__asm__ __volatile__(
"emms\n\t"
"movq 0(%0), %%mm0\n\t"
"movq 8(%0), %%mm7\n\t"
"pxor %%mm7, %%mm0\n\t"
"movq %%mm0, 16(%0)\n\t"
"cmpq $0,16(%0)\n\t"
JZ_NEXT
: : "r"(junk) : "mm7", "mm0", "cc", "memory"
);
printf("\nNo complain mmx\n");
__asm__ __volatile__(
"emms\n\t"
"movq 0(%0), %%mm0\n\t"
"movq 8(%0), %%mm7\n\t"
"pxor %%mm0, %%mm0\n\t"
"movq %%mm0, 16(%0)\n\t"
"cmpq $0,16(%0)\n\t"
JZ_NEXT
: : "r"(junk) : "mm7", "mm0", "cc", "memory"
);
/* --- SSE1 --- */
printf("\nComplain sse xorps\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"xorps %%xmm8, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
printf("\nNo complain sse xorps\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"xorps %%xmm0, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
/* --- SSE2 --- */
printf("\nComplain sse2 pxor\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"pxor %%xmm8, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
printf("\nNo complain sse2 pxor\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"pxor %%xmm0, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
printf("\nComplain sse2 xorpd\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"xorpd %%xmm8, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
printf("\nNo complain sse2 xorpd\n");
__asm__ __volatile__(
"movups 0(%0), %%xmm0\n\t"
"movups 16(%0), %%xmm8\n\t"
"xorpd %%xmm0, %%xmm0\n\t"
"movups %%xmm0, 32(%0)\n\t"
"movq 32(%0), %%rax\n\t"
"addq 40(%0), %%rax\n\t"
JZ_NEXT
: : "r"(junk) : "rax", "xmm8", "xmm0", "cc", "memory"
);
free(junk);
return 0;
}
@@ -0,0 +1,15 @@
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (xor-undef-amd64.c:17)
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (xor-undef-amd64.c:38)
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (xor-undef-amd64.c:65)
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (xor-undef-amd64.c:92)
Conditional jump or move depends on uninitialised value(s)
at 0x........: main (xor-undef-amd64.c:117)
@@ -0,0 +1,20 @@
Complain int64
No complain int64
Complain mmx
No complain mmx
Complain sse xorps
No complain sse xorps
Complain sse2 pxor
No complain sse2 pxor
Complain sse2 xorpd
No complain sse2 xorpd
@@ -0,0 +1,2 @@
prog: xor-undef-amd64
vgopts: -q
@@ -0,0 +1,337 @@
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "tests/asm.h"
#include "tests/malloc.h"
#include <string.h>
#define XSAVE_AREA_SIZE 832
typedef unsigned char UChar;
typedef unsigned int UInt;
typedef unsigned long long int ULong;
typedef unsigned long int UWord;
typedef unsigned char Bool;
#define True ((Bool)1)
#define False ((Bool)0)
const unsigned int vec0[8]
= { 0x12345678, 0x11223344, 0x55667788, 0x87654321,
0x15263748, 0x91929394, 0x19293949, 0x48372615 };
const unsigned int vec1[8]
= { 0xABCDEF01, 0xAABBCCDD, 0xEEFF0011, 0x10FEDCBA,
0xBADCFE10, 0xFFEE9988, 0x11667722, 0x01EFCDAB };
const unsigned int vecZ[8]
= { 0, 0, 0, 0, 0, 0, 0, 0 };
/* A version of memset that doesn't use XMM or YMM registers. */
static __attribute__((noinline))
void* my_memset(void* s, int c, size_t n)
{
size_t i;
for (i = 0; i < n; i++) {
((unsigned char*)s)[i] = (unsigned char)(unsigned int)c;
/* Defeat any attempt at autovectorisation */
__asm__ __volatile__("" ::: "cc","memory");
}
return s;
}
/* Ditto for memcpy */
static __attribute__((noinline))
void* my_memcpy(void *dest, const void *src, size_t n)
{
size_t i;
for (i = 0; i < n; i++) {
((unsigned char*)dest)[i] = ((unsigned char*)src)[i];
__asm__ __volatile__("" ::: "cc","memory");
}
return dest;
}
static void* memalign_zeroed64(size_t size)
{
char* p = memalign64(size);
if (p && size > 0) {
my_memset(p, 0, size);
}
return p;
}
__attribute__((noinline))
static void do_xsave ( void* p, UInt rfbm )
{
assert(rfbm <= 7);
__asm__ __volatile__(
"movq %0, %%rax; xorq %%rdx, %%rdx; xsave (%1)"
: /*OUT*/ : /*IN*/ "r"((ULong)rfbm), "r"(p)
: /*TRASH*/ "memory", "rax", "rdx"
);
}
__attribute__((noinline))
static void do_xrstor ( void* p, UInt rfbm )
{
assert(rfbm <= 7);
__asm__ __volatile__(
"movq %0, %%rax; xorq %%rdx, %%rdx; xrstor (%1)"
: /*OUT*/ : /*IN*/ "r"((ULong)rfbm), "r"(p)
: /*TRASH*/ "rax", "rdx" /* FIXME plus all X87,SSE,AVX regs */
);
}
/* set up the FP, SSE and AVX state, and then dump it. */
static void do_setup_then_xsave ( void* p, UInt rfbm )
{
__asm__ __volatile__("finit");
__asm__ __volatile__("fldpi");
__asm__ __volatile__("fld1");
__asm__ __volatile__("fldln2");
__asm__ __volatile__("fldlg2");
__asm__ __volatile__("fld %st(3)");
__asm__ __volatile__("fld %st(3)");
__asm__ __volatile__("fld1");
__asm__ __volatile__("vmovups (%0), %%ymm0" : : "r"(&vec0[0]) : "xmm0" );
__asm__ __volatile__("vmovups (%0), %%ymm1" : : "r"(&vec1[0]) : "xmm1" );
__asm__ __volatile__("vxorps %ymm2, %ymm2, %ymm2");
__asm__ __volatile__("vmovaps %ymm0, %ymm3");
__asm__ __volatile__("vmovaps %ymm1, %ymm4");
__asm__ __volatile__("vmovaps %ymm2, %ymm5");
__asm__ __volatile__("vmovaps %ymm0, %ymm6");
__asm__ __volatile__("vmovaps %ymm1, %ymm7");
__asm__ __volatile__("vmovaps %ymm1, %ymm8");
__asm__ __volatile__("vmovaps %ymm2, %ymm9");
__asm__ __volatile__("vmovaps %ymm0, %ymm10");
__asm__ __volatile__("vmovaps %ymm1, %ymm11");
__asm__ __volatile__("vmovaps %ymm1, %ymm12");
__asm__ __volatile__("vmovaps %ymm2, %ymm13");
__asm__ __volatile__("vmovaps %ymm0, %ymm14");
__asm__ __volatile__("vmovaps %ymm1, %ymm15");
do_xsave(p, rfbm);
}
static int isFPLsbs ( int i )
{
int q;
q = 32; if (i == q || i == q+1) return 1;
q = 48; if (i == q || i == q+1) return 1;
q = 64; if (i == q || i == q+1) return 1;
q = 80; if (i == q || i == q+1) return 1;
q = 96; if (i == q || i == q+1) return 1;
q = 112; if (i == q || i == q+1) return 1;
q = 128; if (i == q || i == q+1) return 1;
q = 144; if (i == q || i == q+1) return 1;
return 0;
}
static void show ( unsigned char* buf, Bool hideBits64to79 )
{
int i;
for (i = 0; i < XSAVE_AREA_SIZE; i++) {
if ((i % 16) == 0)
fprintf(stderr, "%3d ", i);
if (hideBits64to79 && isFPLsbs(i))
fprintf(stderr, "xx ");
else
fprintf(stderr, "%02x ", buf[i]);
if (i > 0 && ((i % 16) == 15))
fprintf(stderr, "\n");
}
}
static void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx,
UInt index, UInt ecx_in )
{
UInt a,b,c,d;
asm volatile ("cpuid"
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
: "0" (index), "2"(ecx_in) );
*eax = a; *ebx = b; *ecx = c; *edx = d;
//fprintf(stderr, "%08x %08x -> %08x %08x %08x %08x\n",
// index,ecx_in, a,b,c,d );
}
static void xgetbv ( UInt* eax, UInt* edx, UInt ecx_in )
{
UInt a,d;
asm volatile ("xgetbv"
: "=a" (a), "=d" (d) \
: "c"(ecx_in) );
*eax = a; *edx = d;
}
static void check_for_xsave ( void )
{
UInt eax, ebx, ecx, edx;
Bool ok = True;
eax = ebx = ecx = edx = 0;
cpuid(&eax, &ebx, &ecx, &edx, 1,0);
//fprintf(stderr, "cpuid(1).ecx[26=xsave] = %u\n", (ecx >> 26) & 1);
ok = ok && (((ecx >> 26) & 1) == 1);
eax = ebx = ecx = edx = 0;
cpuid(&eax, &ebx, &ecx, &edx, 1,0);
//fprintf(stderr, "cpuid(1).ecx[27=osxsave] = %u\n", (ecx >> 27) & 1);
ok = ok && (((ecx >> 27) & 1) == 1);
eax = ebx = ecx = edx = 0;
xgetbv(&eax, &edx, 0);
//fprintf(stderr, "xgetbv(0) = %u:%u\n", edx, eax);
ok = ok && (edx == 0) && (eax == 7);
if (ok) return;
fprintf(stderr,
"This program must be run on a CPU that supports AVX and XSAVE.\n");
exit(1);
}
void test_xsave ( Bool hideBits64to79 )
{
/* Testing XSAVE:
For RBFM in 0 .. 7 (that is, all combinations): set the x87, SSE
and AVX registers with some values, do XSAVE to dump it, and
print the resulting buffer. */
UInt rfbm;
for (rfbm = 0; rfbm <= 7; rfbm++) {
UChar* saved_img = memalign_zeroed64(XSAVE_AREA_SIZE);
my_memset(saved_img, 0xAA, XSAVE_AREA_SIZE);
saved_img[512] = 0;
do_setup_then_xsave(saved_img, rfbm);
fprintf(stderr,
"------------------ XSAVE, rfbm = %u ------------------\n", rfbm);
show(saved_img, hideBits64to79);
fprintf(stderr, "\n");
free(saved_img);
}
}
void test_xrstor ( Bool hideBits64to79 )
{
/* Testing XRSTOR is more complex than testing XSAVE, because the
loaded value(s) depend not only on what bits are requested (by
RBFM) but also on what bits are actually present in the image
(defined by XSTATE_BV). So we have to test all 64 (8 x 8)
combinations.
The approach is to fill a memory buffer with data, do XRSTOR
from the buffer, them dump all components with XSAVE in a new
buffer, and print the result. This is complicated by the fact
that we need to be able to see which parts of the state (in
registers) are neither overwritten nor zeroed by the restore.
Hence the registers must be pre-filled with values which are
neither zero nor the data to be loaded. We choose to use 0x55
where possible. */
UChar* fives = memalign_zeroed64(XSAVE_AREA_SIZE);
my_memset(fives, 0x55, XSAVE_AREA_SIZE);
/* Set MXCSR so that the insn doesn't fault */
fives[24] = 0x80;
fives[25] = 0x1f;
fives[26] = 0;
fives[27] = 0;
/* Ditto for the XSAVE header area. Also set XSTATE_BV. */
fives[512] = 7;
UInt i;
for (i = 1; i <= 23; i++) fives[512+i] = 0;
/* Fill the x87 register values with something that VEX's
80-vs-64-bit kludging won't mess up -- an 80 bit number which is
representable also as 64 bit: 123456789.0123 */
for (i = 0; i <= 7; i++) {
UChar* p = &fives[32 + 16 * i];
p[0]=0x00; p[1]=0xf8; p[2]=0xc2; p[3]=0x64; p[4]=0xa0;
p[5]=0xa2; p[6]=0x79; p[7]=0xeb; p[8]=0x19; p[9]=0x40;
}
/* And mark the tags for all 8 dumped regs as "valid". */
fives[4/*FTW*/] = 0xFF;
/* (1) (see comment in loop below) */
UChar* standard_test_data = memalign_zeroed64(XSAVE_AREA_SIZE);
do_setup_then_xsave(standard_test_data, 7);
UInt xstate_bv, rfbm;
for (xstate_bv = 0; xstate_bv <= 7; xstate_bv++) {
for (rfbm = 0; rfbm <= 7; rfbm++) {
//{ xstate_bv = 7;
// { rfbm = 6;
/* 1. Copy the "standard test data" into registers, and dump
it with XSAVE. This gives us an image we can try
restoring from.
2. Set the register state to all-0x55s (as far as is
possible), so we can see which parts get overwritten
and which parts get zeroed on the test restore.
3. Do the restore from the image prepared in (1).
4. Dump the state with XSAVE and print it.
*/
/* (3a). We can't use |standard_test_data| directly, since we
need to put in the required |xstate_bv| value. So make a
copy and modify that instead. */
UChar* img_to_restore_from = memalign_zeroed64(XSAVE_AREA_SIZE);
my_memcpy(img_to_restore_from, standard_test_data, XSAVE_AREA_SIZE);
img_to_restore_from[512] = xstate_bv;
/* (4a) */
UChar* saved_img = memalign_zeroed64(XSAVE_AREA_SIZE);
my_memset(saved_img, 0xAA, XSAVE_AREA_SIZE);
saved_img[512] = 0;
/* (2) */
do_xrstor(fives, 7);
// X87, SSE, AVX state LIVE
/* (3b) */
/* and this is what we're actually trying to test */
do_xrstor(img_to_restore_from, rfbm);
// X87, SSE, AVX state LIVE
/* (4b) */
do_xsave(saved_img, 7);
fprintf(stderr,
"---------- XRSTOR, xstate_bv = %u, rfbm = %u ---------\n",
xstate_bv, rfbm);
show(saved_img, hideBits64to79);
fprintf(stderr, "\n");
free(saved_img);
free(img_to_restore_from);
}
}
}
int main ( int argc, char** argv )
{
Bool hideBits64to79 = argc > 1;
fprintf(stderr, "Re-run with any arg to suppress least-significant\n"
" 16 bits of 80-bit FP numbers\n");
check_for_xsave();
if (1)
test_xsave(hideBits64to79);
if (1)
test_xrstor(hideBits64to79);
return 0;
}
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,4 @@
prog: xsave-avx
prereq: test -x xsave-avx && ../../../tests/x86_amd64_features amd64-avx
vgopts: -q
args: x