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AVC LAN Theory
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AVC LAN Theory
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The AVC LAN bus is an implementation of the IEBus (mode 1) which is a
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The AVC LAN bus is an implementation of the IEBus (mode 1) which is a
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differential signal.
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differential signal; IEBus is electrically (but not logically) compatible with
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CAN bus.
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- Logical `1`: Potential difference between bus lines (BUS+ pin and BUS– pin)
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- Logical `1`: Potential difference between bus lines (BUS+ pin and BUS– pin)
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is 20 mV or lower (floating).
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is 20 mV or lower (floating).
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Driving (logical `0`) ╭──────────╮──────────╮
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Driving (logical `0`) ╭──────────╮──────────╮
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│ │ │
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│ │ │
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Floating (logical `1`) ─────────╯ ╰──────────╰─────────
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Floating (logical `1`) ─────────╯ ╰──────────╰─────────
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│ 7 μs │── 20 μs ─│─ 12 μs ──│
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│ 6 μs │── 19 μs ─│─ 13 μs ──│
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The logical value during the data period signifies the bit value, e.g. a bit
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The logical value during the data period signifies the bit value, e.g. a bit
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`0` continues the logical `0` (high potential difference between bus lines) of
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`0` continues the logical `0` (high potential difference between bus lines) of
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the sync period thru the data period, and a bit `1` has a logical `1`
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the sync period thru the data period, and a bit `1` has a logical `1`
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(low/floating potential between bus lines) during the data period.
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(low/floating potential between bus lines) during the data period. Using the
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TCB pulse-width and frequency measure mode, the total bit length differs for
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bit `1` and `0`; detailed bit timing can be found in "timing.h". The bus
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idles at low potential (floating).
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AVC LAN Frame Format
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AVC LAN Frame Format
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│ Bits │ Description
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│ Bits │ Description
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*repeat `n` times*
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*repeat `n` times*
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A start bit is nominally 166 us high followed by 19 us low.
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A start bit is nominally 169 us high followed by 20 us low.
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A bit `0` is dominant on the bus, which is a design choice that affects
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A bit `0` is dominant on the bus, which is a design choice that affects
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bit/interpretation:
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bit/interpretation:
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