mirror of
https://github.com/halleysfifthinc/Toyota-AVC-LAN
synced 2025-06-07 07:56:21 +00:00
Update signal measuring and apply new measurements to bit-timings
This commit is contained in:
Allen Hill
parent
bcd07d0ffb
commit
da6a3371fd
@ -8,7 +8,9 @@
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"generator": "Unix Makefiles",
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"binaryDir": "${sourceDir}/build",
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"cacheVariables": {
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"CMAKE_BUILD_TYPE": "Debug"
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"CMAKE_BUILD_TYPE": "Debug",
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"FREQSEL": "20MHz",
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"TCB_CLKSEL": "TCB_CLKSEL_CLKDIV1_gc"
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}
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},
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{
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@ -17,8 +19,11 @@
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"description": "Configure with RelWithDebInfo build settings",
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"generator": "Unix Makefiles",
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"binaryDir": "${sourceDir}/build",
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"inherits": "default",
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"cacheVariables": {
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"CMAKE_BUILD_TYPE": "RelWithDebInfo"
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"CMAKE_BUILD_TYPE": "RelWithDebInfo",
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"FREQSEL": "20MHz",
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"TCB_CLKSEL": "TCB_CLKSEL_CLKDIV1_gc"
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}
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}
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]
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135
src/avclandrv.c
135
src/avclandrv.c
@ -270,8 +270,14 @@ void AVCLAN_init() {
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EVSYS.ASYNCCH0 = EVSYS_ASYNCCH0_AC2_OUT_gc;
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EVSYS.ASYNCUSER0 = EVSYS_ASYNCUSER0_ASYNCCH0_gc; // USER0 is TCB0
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// TCB0 for read bit timing
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TCB0.CTRLB = TCB_CNTMODE_PW_gc;
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// TCB0 for read bit timing
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#ifdef SOFTWARE_DEBUG
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#define TCB_CNTMODE TCB_CNTMODE_FRQPW_gc
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#else
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#define TCB_CNTMODE TCB_CNTMODE_PW_gc
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#endif
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TCB0.CTRLB = TCB_CNTMODE;
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TCB0.INTCTRL = TCB_CAPT_bm;
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TCB0.EVCTRL = TCB_CAPTEI_bm;
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TCB0.CTRLA = TCB_CLKSEL | TCB_ENABLE_bm;
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@ -324,7 +330,7 @@ void AVCLAN_sendbit_ACK() {
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while (INPUT_IS_CLEAR) {
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// Wait for approx the length of a bit; any longer and something has clearly
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// gone wrong
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if (TCB1.CNT >= AVCLAN_BIT_LENGTH)
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if (TCB1.CNT >= AVCLAN_BIT_LENGTH_MAX)
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return;
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}
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@ -404,9 +410,22 @@ uint8_t AVCLAN_sendbyte(const uint8_t *byte) {
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#define READING_NBITS GPIOR2
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#define READING_PARITY GPIOR3
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#ifdef SOFTWARE_DEBUG
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uint8_t pulse_count = 0;
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uint16_t period = 0;
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#endif
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uint16_t pulsewidth = 0;
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ISR(TCB0_INT_vect) {
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#ifdef SOFTWARE_DEBUG
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pulse_count++;
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period = TCB0.CNT;
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#endif
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// If input was set for less than 26 us (a generous half period), bit was a 1
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if (TCB0.CCMP < (uint16_t)AVCLAN_READBIT_THRESHOLD) {
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pulsewidth = TCB0.CCMP;
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if (pulsewidth < (uint16_t)AVCLAN_READBIT_THRESHOLD) {
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READING_BYTE++;
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READING_PARITY++;
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}
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@ -431,8 +450,8 @@ uint8_t AVCLAN_readbitsi(uint8_t *bits, uint8_t len) {
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TCB1.CNT = 0;
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while (READING_NBITS != 0) {
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// Duration of `len` bits + 10%
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if (TCB1.CNT > (((uint16_t)AVCLAN_BIT_LENGTH * 11 * len) / 10)) {
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// 200% the duration of `len` bits
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if (TCB1.CNT > ((uint16_t)AVCLAN_BIT_LENGTH_MAX * 2 * len)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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@ -469,8 +488,8 @@ uint8_t AVCLAN_readbyte(uint8_t *byte) {
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TCB1.CNT = 0;
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while (READING_NBITS != 0) {
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// Duration of byte + 10%
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if (TCB1.CNT > (((uint16_t)AVCLAN_BIT_LENGTH * 11 * 8) / 10)) {
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// 200% the length of a byte
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if (TCB1.CNT > ((uint16_t)AVCLAN_BIT_LENGTH_MAX * 2 * 8)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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@ -494,7 +513,7 @@ uint8_t AVCLAN_readbit_ACK() {
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while (1) {
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if (INPUT_IS_SET && (TCB1.CNT > AVCLAN_READBIT_THRESHOLD))
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break; // ACK
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if (TCB1.CNT > AVCLAN_BIT_LENGTH)
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if (TCB1.CNT > AVCLAN_BIT_LENGTH_MAX)
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return 1; // NAK
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}
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@ -696,7 +715,7 @@ uint8_t AVCLAN_sendframe(const AVCLAN_frame_t *frame) {
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do {
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while (INPUT_IS_CLEAR) {
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// Wait for 120% of a bit length
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if (TCB1.CNT >= (uint16_t)(AVCLAN_BIT_LENGTH * 12 / 10))
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if (TCB1.CNT >= (uint16_t)(AVCLAN_BIT_LENGTH_MAX * 12 / 10))
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break;
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}
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if (TCB1.CNT > 864)
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@ -1008,94 +1027,40 @@ void AVCLAN_printframe(const AVCLAN_frame_t *frame) {
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}
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#ifdef SOFTWARE_DEBUG
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uint16_t temp_b[100];
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uint16_t pulses[100];
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uint16_t periods[100];
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void AVCLan_Measure() {
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STOPEvent;
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// uint16_t tmp, tmp1, tmp2, bit0, bit1;
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uint8_t n = 0;
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uint8_t tmp = 0;
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cbi(TCCR1B, CS12);
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TCCR1B = _BV(CS10);
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TCNT1 = 0;
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RS232_Print(
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"Timing config: F_CPU=" STR(F_CPU) ", TCB_CLKSEL=" STR(TCB_CLKSEL) "\n");
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RS232_Print("Sampling bit (pulse-width and period) timing...\n");
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char str[5];
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while (n < 100) {
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temp_b[n] = TCNT1;
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while (INPUT_IS_CLEAR) {}
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temp_b[n + 1] = TCNT1;
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while (INPUT_IS_SET) {}
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temp_b[n + 2] = TCNT1;
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while (INPUT_IS_CLEAR) {}
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temp_b[n + 3] = TCNT1;
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while (INPUT_IS_SET) {}
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temp_b[n + 4] = TCNT1;
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while (INPUT_IS_CLEAR) {}
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temp_b[n + 5] = TCNT1;
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while (INPUT_IS_SET) {}
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temp_b[n + 6] = TCNT1;
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while (INPUT_IS_CLEAR) {}
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temp_b[n + 7] = TCNT1;
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while (INPUT_IS_SET) {}
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temp_b[n + 8] = TCNT1;
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while (INPUT_IS_CLEAR) {}
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temp_b[n + 9] = TCNT1;
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while (INPUT_IS_SET) {}
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//
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// while (INPUT_IS_CLEAR) {}
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//
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// tmp1 = TCNT1;
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//
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// while (INPUT_IS_SET) {}
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//
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// tmp2 = TCNT1;
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//
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// bit0 = tmp1-tmp;
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// bit1 = tmp2-tmp1;
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//
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// RS232_Print("1,");
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// RS232_PrintDec(bit1);
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// RS232_Print("\n");
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//
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// RS232_Print("0,");
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// RS232_PrintDec(bit0);
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// RS232_Print("\n");
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n += 10;
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for (uint8_t n = 0; n < 100; n++) {
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while (pulse_count == tmp) {}
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pulses[n] = pulsewidth;
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periods[n] = period;
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tmp = pulse_count;
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}
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RS232_Print("Pulses:\n");
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for (uint8_t i = 0; i < 100; i++) {
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itoa(temp_b[i], str);
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if (i & 1) {
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RS232_Print("High,");
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} else {
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RS232_Print("Low,");
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}
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RS232_Print(str);
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RS232_PrintHex8(*(((uint8_t *)&pulses[i]) + 1));
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RS232_PrintHex8(*(((uint8_t *)&pulses[i]) + 0));
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RS232_Print("\n");
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}
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RS232_Print("Periods:\n");
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for (uint8_t i = 0; i < 100; i++) {
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RS232_PrintHex8(*(((uint8_t *)&periods[i]) + 1));
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RS232_PrintHex8(*(((uint8_t *)&periods[i]) + 0));
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RS232_Print("\n");
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}
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RS232_Print("\nDone.\n");
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cbi(TCCR1B, CS10);
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TCCR1B = _BV(CS12);
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STARTEvent;
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}
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#endif
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#ifdef HARDWARE_DEBUG
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void SetHighLow() {
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AVC_OUT_EN();
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sbi(TCCR1B, CS10);
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uint16_t n = 60000;
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TCNT1 = 0;
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AVC_SET_LOGICAL_1();
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while (TCNT1 < n) {}
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TCNT1 = 0;
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AVC_SET_LOGICAL_0();
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while (TCNT1 < n) {}
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cbi(TCCR1B, CS10);
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AVC_OUT_DIS();
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}
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#endif
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15
src/timing.h
15
src/timing.h
@ -49,17 +49,18 @@
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#error "Not implemented"
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#endif
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#define AVCLAN_STARTBIT_LOGIC_0 (166e3 / TCB_TICK)
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#define AVCLAN_STARTBIT_LOGIC_1 (19e3 / TCB_TICK)
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// Measured at ±0.02 μs @ F_CPU=20MHz, TCB_CLKSEL=TCB_CLKSEL_CLKDIV1_gc
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#define AVCLAN_STARTBIT_LOGIC_0 (169e3 / TCB_TICK)
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#define AVCLAN_STARTBIT_LOGIC_1 (20.6e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_0 (20.5e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_1 (19e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_0 (19.7e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_1 (18.1e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_0 (34e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_1 (5.5e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_0 (32.85e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_1 (6.2e3 / TCB_TICK)
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#define AVCLAN_READBIT_THRESHOLD (26e3 / TCB_TICK)
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#define AVCLAN_BIT_LENGTH (39.5e3 / TCB_TICK)
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#define AVCLAN_BIT_LENGTH_MAX (39.1e3 / TCB_TICK)
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#endif
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