diff --git a/vendor/jnk0le-AVR-UART-lib/LICENSE b/vendor/jnk0le-AVR-UART-lib/LICENSE
new file mode 100644
index 0000000..b7043e9
--- /dev/null
+++ b/vendor/jnk0le-AVR-UART-lib/LICENSE
@@ -0,0 +1,22 @@
+The MIT License (MIT)
+
+Copyright (c) 2015 jnk0le
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
diff --git a/vendor/jnk0le-AVR-UART-lib/README.md b/vendor/jnk0le-AVR-UART-lib/README.md
new file mode 100644
index 0000000..f3771ca
--- /dev/null
+++ b/vendor/jnk0le-AVR-UART-lib/README.md
@@ -0,0 +1,80 @@
+# AVR-UART-lib
+An interrupt-driven USART (RS232) library for AVR microcontrollers, with support for multiple hardware UARTs, using ring
+buffers for receive/transmit. Designed especially for real-time or high throughput applications, with narrow resource limits.
+
+## Features
+- selectable support for up to 4 USART's
+- up to 255 byte FIFOs
+- only 2 (+1 wasted slot) byte memory footprint except actual buffer for every implemented RX or TX path
+- no dynamic memory allocations
+- extremly light interrupts
+- software(RTS/CTS) and hardware flow control support (DCE naming)
+- RS 485 compatibility
+- MPCM master and slave mode support
+- printf()/scanf() streams compatibility
+- V-USB compatibility (25 cycle ISR restriction)
+- optimized as much as possible to reduce code size and execution times
+
+## Notes
+- Lot of terminals sends only CR character as a newline terminator, instead of CRLF or even unix style LF
+(BTW PuTTY doesn't allow to change this) but in return requires CRLF terminator to show not broken text.
+This behaviour can be covered by RX_NEWLINE_MODE macro, by default set to CRLF.
+
+	- 0 - CR
+	- 1 - LF
+	- 2 - CRLF (default)
+
+- In order to reinitialize uart baudrate after any traffic was occurring, function uart_reinit() have to be used. (memory FIFO buffers will not be flushed)
+
+- Any used IO pin have to be accessible from bottom IO address space. (eg. few ports on mega2560 cannot be used as a control IO) 
+
+- In half duplex (RS485) transmission modes, the application code is responsible of starting transmission only when bus is idle.
+If RE and DE are shorted together additional pullup on RX pin is required.
+Pin used as a RS485 control line have to be kept in low state during boot process via a pulldown resistor or at least not driving it high even by an internall pull-up. (especially on multi node buses)
+
+- In MPCM mode first received byte is address by which device was called (own or general call), application is also responsible of restoring into "idle listening" state withing described bus silence time after receiving entire packet.
+
+- uart_putc() function is not thread/interrupt-safe nor reentrant. It shouldn't be called from within atomic blocks or interrupt handlers since it re-enables interrupt flag on exit or even hangs in infinite loop waiting for execution of UDRE interrupt.
+
+- this library is written in c99/gnu99 dialect standard.
+
+## Flow control
+
+This library provides a software implementation of CTS/RTS control lines (DTR/DSR respectively) to signal whether buffer is full (not an 80' style handshaking).
+It should be used, in order to achieve stable bidirectional >100kbps transmissions, especially when using non deterministic usb-serial converters (ft232, ch340 etc).
+The legendary "noise" that causes losing blocks of characters (not damaging) can also be fixed by that.
+
+### Config
+- soft CTS pins have to be configured as an input, and both edge interrupt source (INT/PCINT), before entering uart_init().
+The application code should call cts_isr_handlers from interrupts corresponding to used pins. (see [example](example(flow control).c))
+If CTS line goes high during transmission (before UDRE interrupt is fired), only one additional byte will be transmitted. (due to 2 level transmit register)
+
+- soft RTS pins have to be configured as input without pullup or output in low state, before entering uart_init().
+If interrupts are not missed, the receiver can accept up to 2 additional bytes after buffer is filled, one from next or ongoing transmission 
+and another one if transmitter misses RTS signal (last one is stored in shift register).
+
+- Any used IO pin have to be accessible from bottom IO address space. (eg. few ports on mega2560 cannot be used as a flow control IO) 
+
+- For proper operation of hardware RTS, USART_EXTEND_RX_BUFFER have to be defined.
+
+## ISR timmings (cycles)
+
+| ISR case | attiny2313 | atmega8 | atmega328 | atmega2560 | lgt8f88A | 
+| --- | --- | --- | --- | --- | --- |
+| **TX best** | 37 | 40 | 40 | 42 | 30 |
+| **TX worst** | 38 | 41 | 44 | 46 | 35 |
+| **RX best** | 36 | 36 | 37 | 39 | 27 |
+| **RX worst** | 40 | 42 | 43 | 45 | 32 |
+| **RX rts full** | 41 | 41 | 44 | 46 | 32 |
+| **RX rts normal** | 40 | 42 | 43 | 45 | 32 |
+| **BUFFER_SIZE = 256** | x | -1 | -1 | -1 | -1 |
+| **G_SREG_SAVE** | -4 | -4 | -4 | -4 | -2 |
+| **G_Z_SAVE** | -6 | -6 | -6 | -6 | -2 |
+
+- TX best case - send byte from buffer
+- TX worst case - send byte from buffer and disable UDRIE interrupt (will not generate double shot)
+- RX best case - load byte and do nothing (buffer full)
+- RX worst case - load byte and put it into buffer
+- RX rts full - rise RTS line and disable RXCIE interrupt
+- RX rts normal - load byte and put it into buffer if there is available space
+
diff --git a/vendor/jnk0le-AVR-UART-lib/usart.c b/vendor/jnk0le-AVR-UART-lib/usart.c
new file mode 100644
index 0000000..a183c2e
--- /dev/null
+++ b/vendor/jnk0le-AVR-UART-lib/usart.c
@@ -0,0 +1,6074 @@
+/*!
+ * \brief
+ *
+ * \author Jan Oleksiewicz <jnk0le@hotmail.com>
+ * \license SPDX-License-Identifier: MIT
+ */
+
+#include <avr/io.h>
+#include <util/delay.h>
+#include <util/atomic.h>
+#include <avr/pgmspace.h>
+#include <avr/interrupt.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "usart.h"
+
+#ifndef NO_TX0_INTERRUPT
+	volatile uint8_t tx0_Tail, tx0_Head;
+	char tx0_buffer[TX0_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_RX0_INTERRUPT
+	volatile uint8_t rx0_Tail, rx0_Head;
+	char rx0_buffer[RX0_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_TX1_INTERRUPT
+	volatile uint8_t tx1_Tail, tx1_Head;
+	char tx1_buffer[TX1_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_RX1_INTERRUPT
+	volatile uint8_t rx1_Tail, rx1_Head;
+	char rx1_buffer[RX1_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_TX2_INTERRUPT
+	volatile uint8_t tx2_Tail, tx2_Head;
+	char tx2_buffer[TX2_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_RX2_INTERRUPT
+	volatile uint8_t rx2_Tail, rx2_Head;
+	char rx2_buffer[RX2_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_TX3_INTERRUPT
+	volatile uint8_t tx3_Tail, tx3_Head;
+	char tx3_buffer[TX3_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifndef NO_RX3_INTERRUPT
+	volatile uint8_t rx3_Tail, rx3_Head;
+	char rx3_buffer[RX3_BUFFER_SIZE] __attribute__ ((used));
+#endif
+
+#ifdef USART_NO_LOCAL_BUFFERS
+	extern char u_tmp_buff[];
+#endif
+
+#ifdef USE_USART0
+/*
+	void uart_init(uint16_t ubrr_value)
+	{
+	#ifdef USART0_RS485_MODE
+		RS485_CONTROL0_DDR |= (1<<RS485_CONTROL0_IONUM); // default pin state is low
+	#endif
+		
+		UBRR0L_REGISTER = (uint8_t) ubrr_value;
+		UBRR0H_REGISTER = (ubrr_value>>8);
+		
+	#ifdef USART0_U2X_SPEED
+		#ifdef USART0_MPCM_MODE
+			UCSR0A_REGISTER = (1<<U2X0_BIT)|(1<<MPCM0_BIT);
+		#else
+			UCSR0A_REGISTER = (1<<U2X0_BIT); // enable double speed
+		#endif
+	#elif defined(USART0_MPCM_MODE)
+		UCSR0A_REGISTER |= (1<<MPCM0_BIT);
+	#endif
+		
+		UCSR0B_REGISTER = USART0_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART0_USE_SOFT_RTS
+		RTS0_DDR |= (1<<RTS0_IONUM);
+	#endif
+	}
+*/
+
+//******************************************************************
+//Function  : To reinitialize USART interface (runtime speed changing).
+//Arguments : Calculated UBRR value to initialize equal speed.
+//Return    : none
+//Note      : Use BAUD_CALC(speed) macro to calculate UBRR value.
+//          : All data inside UDR shift register will be lost.
+//          : U2X bit is cleared if USARTn_U2X_SPEED is not defined.
+//******************************************************************
+	void uart0_reinit(uint16_t ubrr_value)
+	{
+	#ifdef USART0_USE_SOFT_RTS
+		RTS0_PORT |= (1<<RTS0_IONUM);
+	#endif
+		
+	#ifdef USART0_RS485_MODE
+		RS485_CONTROL0_PORT &= ~(1<<RS485_CONTROL0_IONUM); //set low
+		RS485_CONTROL0_DDR |= (1<<RS485_CONTROL0_IONUM);
+	#endif
+		
+		UCSR0B_REGISTER = 0; //flush all hardware buffers
+		
+		//(writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed
+		
+		UBRR0L_REGISTER = (uint8_t) ubrr_value;
+		UBRR0H_REGISTER = (ubrr_value>>8);
+
+	#ifdef USART0_U2X_SPEED
+		#ifdef USART0_MPCM_MODE
+			UCSR0A_REGISTER = (1<<U2X0_BIT)|(1<<MPCM0_BIT);
+		#else
+			UCSR0A_REGISTER = (1<<U2X0_BIT); // enable double speed
+		#endif
+	#elif defined(USART0_MPCM_MODE)
+		UCSR0A_REGISTER = (1<<MPCM0_BIT);
+	#endif
+	
+		UCSR0B_REGISTER = USART0_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART0_USE_SOFT_RTS
+		RTS0_DDR |= (1<<RTS0_IONUM);
+		RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+	}
+#endif // USE_USART0
+
+#ifdef USE_USART1
+	void uart1_reinit(uint16_t ubrr_value)
+	{
+	#ifdef USART1_USE_SOFT_RTS
+		RTS1_PORT |= (1<<RTS1_IONUM);
+	#endif
+	
+	#ifdef USART1_RS485_MODE
+		RS485_CONTROL1_PORT &= ~(1<<RS485_CONTROL1_IONUM); //set low
+		RS485_CONTROL1_DDR |= (1<<RS485_CONTROL1_IONUM);
+	#endif
+		
+		UCSR1B_REGISTER = 0; //flush all hardware buffers
+		
+		//(writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed
+		
+		UBRR1L_REGISTER = (uint8_t) ubrr_value;
+		UBRR1H_REGISTER = (ubrr_value>>8);
+
+	#ifdef USART1_U2X_SPEED
+		#ifdef USART1_MPCM_MODE
+			UCSR1A_REGISTER = (1<<U2X1_BIT)|(1<<MPCM1_BIT);
+		#else
+			UCSR1A_REGISTER = (1<<U2X1_BIT); // enable double speed
+		#endif
+	#elif defined(USART1_MPCM_MODE)
+		UCSR1A_REGISTER = (1<<MPCM1_BIT);
+	#endif
+	
+		UCSR1B_REGISTER = USART1_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART1_USE_SOFT_RTS
+		RTS1_DDR |= (1<<RTS1_IONUM);
+		RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+	}
+#endif // USE_USART1
+
+#ifdef USE_USART2
+	void uart2_reinit(uint16_t ubrr_value)
+	{
+	#ifdef USART2_USE_SOFT_RTS
+		RTS2_PORT |= (1<<RTS2_IONUM);
+	#endif
+	
+	#ifdef USART2_RS485_MODE
+		RS485_CONTROL2_PORT &= ~(1<<RS485_CONTROL2_IONUM); //set low
+		RS485_CONTROL2_DDR |= (1<<RS485_CONTROL2_IONUM);
+	#endif
+		
+		UCSR2B_REGISTER = 0; //flush all hardware buffers
+		
+		//(writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed
+
+		UBRR2L_REGISTER = (uint8_t) ubrr_value;
+		UBRR2H_REGISTER = (ubrr_value>>8);
+
+	#ifdef USART2_U2X_SPEED
+		#ifdef USART2_MPCM_MODE
+			UCSR2A_REGISTER = (1<<U2X2_BIT)|(1<<MPCM2_BIT);
+		#else
+			UCSR2A_REGISTER = (1<<U2X2_BIT); // enable double speed
+		#endif
+	#elif defined(USART2_MPCM_MODE)
+		UCSR2A_REGISTER = (1<<MPCM2_BIT);
+	#endif
+	
+		UCSR2B_REGISTER = USART2_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART2_USE_SOFT_RTS
+		RTS2_DDR |= (1<<RTS2_IONUM);
+		RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+	}
+#endif // USE_USART2
+
+#ifdef USE_USART3
+	void uart3_reinit(uint16_t ubrr_value)
+	{
+	#ifdef USART3_USE_SOFT_RTS
+		RTS3_PORT |= (1<<RTS3_IONUM);
+	#endif
+	
+	#ifdef USART3_RS485_MODE
+		RS485_CONTROL3_PORT &= ~(1<<RS485_CONTROL3_IONUM); //set low
+		RS485_CONTROL3_DDR |= (1<<RS485_CONTROL3_IONUM);
+	#endif
+		
+		UCSR3B_REGISTER = 0; //flush all hardware buffers
+		
+		UBRR3L_REGISTER = (uint8_t) ubrr_value;
+		UBRR3H_REGISTER = (ubrr_value>>8);
+
+	#ifdef USART3_U2X_SPEED
+		#ifdef USART3_MPCM_MODE
+			UCSR3A_REGISTER = (1<<U2X3_BIT)|(1<<MPCM3_BIT);
+		#else
+			UCSR3A_REGISTER = (1<<U2X3_BIT); // enable double speed
+		#endif
+	#elif defined(USART3_MPCM_MODE)
+		UCSR3A_REGISTER = (1<<MPCM3_BIT);
+	#endif
+	
+		UCSR3B_REGISTER = USART3_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART3_USE_SOFT_RTS
+		RTS3_DDR |= (1<<RTS3_IONUM);
+		RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+	}
+#endif // USE_USART3
+
+#ifndef NO_USART_TX
+
+#ifndef NO_TX0_INTERRUPT
+//******************************************************************
+//Function  : Send single character/byte.
+//Arguments : Character/byte to send.
+//Return    : none
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putc(char data)
+	{
+	#ifdef PUTC0_CONVERT_LF_TO_CRLF
+		if (data == '\n')
+			uart0_putc('\r');
+	#endif
+		
+	#ifdef USART0_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx0_Head;
+		register uint8_t tmp_tx_Tail = tx0_Tail;
+		
+	#ifdef USART0_USE_SOFT_CTS
+		if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR0A_REGISTER & UDRE0_BIT))
+		{
+			UDR0_REGISTER = data;
+			return;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX0_BUFFER_MASK;
+		
+		while(tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer
+		{
+			tmp_tx_Tail = tx0_Tail; // for faster pass through, results in a little bigger code
+		}
+	#else
+		register uint8_t tmp_tx_Head = (tx0_Head + 1) & TX0_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		while(tx0_Tail == tmp_tx_Head); // wait for free space in buffer
+	#endif
+		
+		tx0_buffer[tmp_tx_Head] = data;
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx0_Head = tmp_tx_Head;
+			
+		#ifdef USART0_RS485_MODE
+			RS485_CONTROL0_PORT |= (1<<RS485_CONTROL0_IONUM); //set high
+		#endif
+			
+		#ifdef USART0_USE_SOFT_CTS
+			if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+		#endif
+			{
+				UCSR0B_REGISTER |= (1<<UDRIE0_BIT); // enable UDRE interrupt
+			}
+		}
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putc(char data)
+	{
+		register uint8_t tmp_tx_Head asm("r25");
+		
+	#ifdef PUTC0_CONVERT_LF_TO_CRLF
+		asm volatile("\n\t"
+			"cpi %[dat], '\n' \n\t"
+			"brne skip_recursive_%=\n\t"
+			"push %[dat] \n\t"
+			"ldi %[dat], '\r' \n\t"
+			"rcall uart0_putc \n\t"
+			"pop %[dat] \n\t"
+		"skip_recursive_%=:"
+			: // outputs
+			[dat]  "+r" (data) // will be used later, do not let the compiler to do anything weird
+			: // inputs
+			: // clobbers
+		);
+	#endif
+		
+	#ifdef USART0_PUTC_FAST_INSERTIONS
+		
+		asm volatile("\n\t"
+			"lds %[head], (tx0_Head) \n\t"
+			
+		#ifdef USART0_USE_SOFT_CTS
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"rjmp normal_insert_%= \n\t"  
+		#endif
+				
+			"lds r27, (tx0_Tail) \n\t"
+			"cpse r27, %[head] \n\t"
+			"rjmp normal_insert_%= \n\t"
+				
+		#ifdef USART0_IN_IO_ADDRESS_SPACE
+			"sbis %M[UCSRA_reg_IO], %M[udre_bit] \n\t"
+		#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+			"in r26, %M[UCSRA_reg_IO] \n\t"
+			"sbrs r26, %M[udre_bit] \n\t"
+		#else
+			"lds r26, %M[UCSRA_reg] \n\t"
+			"sbrs r26, %M[udre_bit] \n\t"
+		#endif
+			"rjmp normal_insert_%= \n\t"
+				
+		#ifdef USART0_IN_IO_ADDRESS_SPACE
+			"out %M[UDR_reg], %[dat] \n\t"
+		#else
+			"sts %M[UDR_reg], %[dat] \n\t"
+		#endif
+			"ret \n\t"
+			
+		"normal_insert_%=:"
+			"inc %[head] \n\t"
+			
+		#if (TX0_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx0_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head),
+			[dat]  "+r" (data) // will be used later, do not let the compiler to do anything weird
+			: // inputs
+		#ifdef USART0_USE_SOFT_CTS
+			[cts_port]      "M" (_SFR_IO_ADDR(CTS0_PORT)),
+			[cts_pin]       "M" (CTS0_IONUM),
+		#endif
+			[mask]          "M" (TX0_BUFFER_MASK),
+			[UCSRA_reg]     "n" (_SFR_MEM_ADDR(UCSR0A_REGISTER)),
+			[UCSRA_reg_IO]  "M" (_SFR_IO_ADDR(UCSR0A_REGISTER)),
+			[UDR_reg]	    "n" (_SFR_MEM_ADDR(UDR0_REGISTER)),
+			[UDR_reg_IO]    "M" (_SFR_IO_ADDR(UDR0_REGISTER)),
+			[udre_bit]      "M"	(UDRE0_BIT)
+			: // clobbers
+			"r26","r27"
+		);
+	#else
+		asm volatile("\n\t"
+			"lds %[head], (tx0_Head) \n\t"
+			"inc %[head] \n\t"
+			
+		#if (TX0_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx0_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head)
+			: // inputs
+			[mask] "M" (TX0_BUFFER_MASK)
+			: // clobbers
+			"r27"
+		);
+	#endif
+		
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+		
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__) // on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r27, 0x00 \n\t"
+		#endif
+			"subi r26, lo8(-(tx0_buffer)) \n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r27, hi8(-(tx0_buffer)) \n\t"
+		#endif
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head), // will be used later, do not let the compiler to do anything weird
+			[dat]   "+r" (data) // not modified, so reduce register moves if inlined
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+	
+		cli();
+		{
+			tx0_Head = tmp_tx_Head;
+		
+		#ifdef USART0_RS485_MODE
+			RS485_CONTROL0_PORT |= (1<<RS485_CONTROL0_IONUM); // start transmitting
+		#endif
+		
+		#ifdef USART0_USE_SOFT_CTS
+			if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+		#endif
+			{
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				UCSR0B_REGISTER |= (1<<UDRIE0_BIT); // enable UDRE interrupt
+			#else
+				asm volatile("\n\t"
+				#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
+					"in r25, %M[control_reg_IO] \n\t"
+					"ori r25, (1<<%M[udrie_bit]) \n\t"
+					"out %M[control_reg_IO], r25\n\t"
+				#else 
+					"lds r25, %M[control_reg] \n\t"
+					"ori r25, (1<<%M[udrie_bit]) \n\t"
+					"sts %M[control_reg], r25 \n\t"
+				#endif
+					: // outputs
+					: // inputs
+					[control_reg] "n" (_SFR_MEM_ADDR(UCSR0B_REGISTER)),
+					[udrie_bit]   "M" (UDRIE0_BIT)
+					: // clobbers
+					"r25"
+				);
+			#endif
+			}
+		}
+	
+		reti();
+		asm volatile("\n\t"::"r" (data):); // data was passed in r24 and will be returned in the same register, make sure it is not affected by the compiler 
+	}
+	
+	char uart0_putc_(char data) __attribute__ ((alias ("uart0_putc"))); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Send single character/byte.
+//Arguments : Character/byte to send.
+//Return    : Status value: 0 = BUFFER_FULL, 1 = COMPLETED.
+//Note      : If character cannot be sent due to full transmit buffer, function will abort transmitting character
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart0_putc_noblock(char data)
+	{
+	#ifdef USART0_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx0_Head;
+		register uint8_t tmp_tx_Tail = tx0_Tail;
+	
+	#ifdef USART0_USE_SOFT_CTS
+		if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR0A_REGISTER & UDRE0_BIT))
+		{
+			UDR0_REGISTER = data;
+			return COMPLETED;
+		}
+	
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX0_BUFFER_MASK;
+	
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx0_Head + 1) & TX0_BUFFER_MASK; // calculate new position of TX head in buffer
+	
+		if(tx0_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		tx0_buffer[tmp_tx_Head] = data;
+	
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx0_Head = tmp_tx_Head;
+		
+		#ifdef USART0_RS485_MODE
+			RS485_CONTROL0_PORT |= (1<<RS485_CONTROL0_IONUM); //set high
+		#endif
+		
+		#ifdef USART0_USE_SOFT_CTS
+			if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+		#endif
+			{
+				UCSR0B_REGISTER |= (1<<UDRIE0_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#else //!USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart0_putc_noblock(char data)
+	{
+	#ifdef USART0_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx0_Head;
+		register uint8_t tmp_tx_Tail = tx0_Tail;
+		
+	#ifdef USART0_USE_SOFT_CTS
+		if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR0A_REGISTER & UDRE0_BIT))
+		{
+			UDR0_REGISTER = data;
+			return COMPLETED;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX0_BUFFER_MASK;
+		
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx0_Head + 1) & TX0_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		if(tx0_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+		
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__) // on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r27, 0x00 \n\t"
+		#endif
+			"subi r26, lo8(-(tx0_buffer)) \n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r27, hi8(-(tx0_buffer)) \n\t"
+		#endif
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head), // will be used later, do not let the compiler to do anything weird
+			[dat]   "+r" (data) // not modified, so reduce register moves if inlined
+			: // inputs
+			: // clobbers
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__)
+			"r27",
+		#endif
+			"r26"
+		);
+		
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx0_Head = tmp_tx_Head;
+			
+		#ifdef USART0_RS485_MODE
+			RS485_CONTROL0_PORT |= (1<<RS485_CONTROL0_IONUM); // start transmitting
+		#endif
+			
+		#ifdef USART0_USE_SOFT_CTS
+			if(!(CTS0_PIN & (1<<CTS0_IONUM)))
+		#endif
+			{
+				UCSR0B_REGISTER |= (1<<UDRIE0_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#endif
+
+//******************************************************************
+//Function  : Send string array.
+//Arguments : Pointer to string array terminated by NULL.
+//Return    : none
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putstr(char *string)
+	{
+		char c;
+		while ((c = *string++)) uart0_putc(c);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putstr(char *string)
+	{
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"ld r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart0_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Send string not terminated by NULL or part of the string array.
+//Arguments : 1. Pointer to string array.
+//          : 2. Number of characters/bytes to send.
+//Return    :    none
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		while(BytesToWrite--)
+			uart0_putc(*string++);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		asm volatile("\n\t"
+			"add %[counter], r30 \n\t" // add ZL to a counter to compare against current pointer (8 bit length, doesn't care if overflow)
+		"load_loop_%=:"
+			"cp %[counter], r30\n\t"
+			"breq skip_loop_%= \n\t"
+			"ld r24, Z+ \n\t"
+			"rcall uart0_putc \n\t" // counter and Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			[counter] "r" (BytesToWrite),
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Send string from flash memory.
+//Arguments : Pointer to string placed in flash memory.
+//Return    : none
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_puts_p(const __flash char *string)
+	{
+	#ifndef USART0_NOT_ACCESIBLE_FROM_CBI // tiny 102/104
+		register char c;
+		while ( (c = *string++) ) uart0_putc(c); 
+	#endif
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_puts_p(const __flash char *string)
+	{
+	#if !defined(__AVR_ATtiny102__)||!defined(__AVR_ATtiny104__)
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"lpm r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart0_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	#endif
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Send integer formated into ASCI string (base 10).
+//Arguments : int16_t data value.
+//Return    : none
+//******************************************************************
+	void uart0_putint(int16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		itoa(data, u_tmp_buff, 10);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send integer formated into ASCI string.
+//Arguments : 1. uint16_t data value.
+//          : 2. Base value (DEC, HEX, OCT, BIN, etc.).
+//Return    :    none
+//******************************************************************
+	void uart0_putintr(int16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		itoa(data, u_tmp_buff, radix);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send unsigned integer formated into ASCI string (base 10).
+//Arguments : uint16_t data value.
+//Return    : none
+//******************************************************************
+	void uart0_putuint(uint16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		utoa(data, u_tmp_buff, 10);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send unsigned integer formated into ASCI string.
+//Arguments : 1. uint16_t data value.
+//          : 2. Base value (DEC, HEX, OCT, BIN, etc.).
+//Return    :    none
+//******************************************************************
+	void uart0_putuintr(uint16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		utoa(data, u_tmp_buff, radix);
+		uart0_putstr(u_tmp_buff);
+	}
+
+//******************************************************************
+//Function  : Send unsigned integer formated into ASCI string (base 16)
+//Arguments : uint16_t data value.
+//Return    : none
+//******************************************************************
+	void uart0_puthex(uint8_t data)
+	{
+		uint8_t tmp; 
+		
+		tmp = (data >> 4) & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart0_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart0_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+		
+		tmp = data & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart0_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart0_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+	}
+
+//******************************************************************
+//Function  : Send long integer formated into ASCI string (base 10).
+//Arguments : int32_t data value.
+//Return    : none
+//******************************************************************
+	void uart0_putlong(int32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, 10);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send long integer formated into ASCI string.
+//Arguments : 1. int32_t data value.
+//          : 2. Base value (DEC, HEX, OCT, BIN, etc.).
+//Return    :    none
+//******************************************************************
+	void uart0_putlongr(int32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, radix);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send unsigned long integer formated into ASCI string (base 10).
+//Arguments : uint32_t data value.
+//Return    : none
+//******************************************************************
+	void uart0_putulong(uint32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, 10);
+		uart0_putstr(u_tmp_buff);
+	}
+	
+//******************************************************************
+//Function  : Send unsigned long integer formated into ASCI string.
+//Arguments : 1. uint32_t data value.
+//          : 2. Base value (DEC, HEX, OCT, BIN, etc.).
+//Return    :    none
+//******************************************************************
+	void uart0_putulongr(uint32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, radix);
+		uart0_putstr(u_tmp_buff);
+	}
+
+//******************************************************************
+//Function  : Send floating point value formated into ASCI string.
+//Arguments : float data value.
+//Return    : none
+//******************************************************************
+	void uart0_putfloat(float data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, 6, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart0_putstr(p);
+	}
+
+//******************************************************************
+//Function  : Send floating point integer formated into ASCI string.
+//Arguments : 1. Float data value.
+//          : 2. Number of displayed digits after the dot.
+//Return    :    none
+//******************************************************************
+	void uart0_fputfloat(float data, uint8_t precision)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, precision, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart0_putstr(p);
+	}
+	
+//******************************************************************
+//Function  : Wait until all data in TX buffer are flushed.
+//Arguments : none
+//Return    : none
+//******************************************************************	
+	void uart0_flush(void)
+	{
+	#ifdef USART0_RS485_MODE // flush UDR buffer
+		while (RS485_CONTROL0_PORT & (1<<RS485_CONTROL0_IONUM));
+	#else
+		while(tx0_Tail != tx0_Head); // just flush the ring buffer
+	#endif
+	}
+	
+//******************************************************************
+//Function  : To check how many bytes are waiting in the transmitter buffer.
+//Arguments : none
+//Return    : Number of bytes waiting in transmitter buffer.
+//******************************************************************
+//uint8_t uart0_BytesToSend(void)
+//	{
+//		return (tx0_Head - tx0_Tail) & TX0_BUFFER_MASK;
+//	}
+
+//******************************************************************
+//Function  : Transmit address of selected slave in MPCM mode.
+//Arguments : Address of selected slave.
+//Return    : none
+//******************************************************************
+#ifdef USART0_MPCM_MODE
+	void uart0_mpcm_transmit_addres_Frame(uint8_t dat)
+	{
+		while(tx0_Tail != tx0_Head);
+		UCSR0B_REGISTER |= (1<<TXB80_BIT);
+		uart_putc(dat);
+		while(tx0_Tail != tx0_Head);
+		UCSR0B_REGISTER &= ~(1<<TXB80_BIT); // not sure if necessary
+	}
+#endif
+#endif // NO_TX0_INTERRUPT
+
+#ifndef NO_TX1_INTERRUPT
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putc(char data)
+	{
+	#ifdef PUTC1_CONVERT_LF_TO_CRLF
+		if (data == '\n')
+			uart1_putc('\r');
+	#endif
+		
+	#ifdef USART1_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx1_Head;
+		register uint8_t tmp_tx_Tail = tx1_Tail;
+		
+	#ifdef USART1_USE_SOFT_CTS
+		if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR1A_REGISTER & UDRE1_BIT))
+		{
+			UDR1_REGISTER = data;
+			return;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX1_BUFFER_MASK;
+		
+		while(tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer
+		{
+			tmp_tx_Tail = tx1_Tail; // for faster pass through, results in a little bigger code
+		}
+	#else
+		register uint8_t tmp_tx_Head = (tx1_Head + 1) & TX1_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		while(tx1_Tail == tmp_tx_Head); // wait for free space in buffer
+	#endif
+		
+		tx1_buffer[tmp_tx_Head] = data;
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx1_Head = tmp_tx_Head;
+			
+		#ifdef USART1_RS485_MODE
+			RS485_CONTROL1_PORT |= (1<<RS485_CONTROL1_IONUM); //set high
+		#endif
+			
+		#ifdef USART1_USE_SOFT_CTS
+			if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+		#endif
+			{
+				UCSR1B_REGISTER |= (1<<UDRIE1_BIT); // enable UDRE interrupt
+			}
+		}
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putc(char data)
+	{
+		register uint8_t tmp_tx_Head asm("r25");
+		
+	#ifdef PUTC1_CONVERT_LF_TO_CRLF
+		asm volatile("\n\t"
+			"cpi %[dat], '\n' \n\t"
+			"brne skip_recursive_%=\n\t"
+			"push %[dat] \n\t"
+			"ldi %[dat], '\r' \n\t"
+			"rcall uart1_putc \n\t"
+			"pop %[dat] \n\t"
+		"skip_recursive_%=:"
+			: // outputs
+			[dat]  "+r" (data) // will be used later, do not let the compiler to do anything weird
+			: // inputs
+			: // clobbers
+		);
+	#endif
+		
+	#ifdef USART1_PUTC_FAST_INSERTIONS
+		
+		asm volatile("\n\t"
+			"lds %[head], (tx1_Head) \n\t"
+			
+		#ifdef USART1_USE_SOFT_CTS
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"rjmp normal_insert_%= \n\t"  
+		#endif
+				
+			"lds r27, (tx1_Tail) \n\t"
+			"cpse r27, %[head] \n\t"
+			"rjmp normal_insert_%= \n\t"
+				
+		#ifdef USART1_IN_IO_ADDRESS_SPACE
+			"sbis %M[UCSRA_reg_IO], %M[udre_bit] \n\t"
+		#else
+			"lds r26, %M[UCSRA_reg] \n\t"
+			"sbrs r26, %M[udre_bit] \n\t"
+		#endif
+			"rjmp normal_insert_%= \n\t"
+				
+		#ifdef USART1_IN_IO_ADDRESS_SPACE
+			"out %M[UDR_reg], %[dat] \n\t"
+		#else
+			"sts %M[UDR_reg], %[dat] \n\t"
+		#endif
+			"ret \n\t"
+				
+		"normal_insert_%=:"
+			"inc %[head] \n\t"
+			
+		#if (TX1_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx1_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head),
+			[dat]  "+r" (data)
+			: // inputs
+		#ifdef USART1_USE_SOFT_CTS
+			[cts_port]      "M" (_SFR_IO_ADDR(CTS1_PORT)),
+			[cts_pin]       "M" (CTS1_IONUM),
+		#endif
+			[mask]          "M" (TX1_BUFFER_MASK),
+			[UCSRA_reg]     "n" (_SFR_MEM_ADDR(UCSR1A_REGISTER)),
+			[UCSRA_reg_IO]  "M" (_SFR_IO_ADDR(UCSR1A_REGISTER)),
+			[UDR_reg]	    "n" (_SFR_MEM_ADDR(UDR1_REGISTER)),
+			[UDR_reg_IO]    "M" (_SFR_IO_ADDR(UDR1_REGISTER)),
+			[udre_bit]      "M"	(UDRE1_BIT)
+			: // clobbers
+			"r26","r27"
+		);
+	#else
+		asm volatile("\n\t"
+			"lds %[head], (tx1_Head) \n\t"
+			"inc %[head] \n\t"
+			
+		#if (TX1_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx1_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head)
+			: // inputs
+			[mask] "M" (TX1_BUFFER_MASK)
+			: // clobbers
+			"r27"
+		);
+	#endif
+		
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx1_buffer)) \n\t"
+			"sbci r27, hi8(-(tx1_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		cli();
+		{
+			tx1_Head = tmp_tx_Head;
+		
+		#ifdef USART1_RS485_MODE
+			RS485_CONTROL1_PORT |= (1<<RS485_CONTROL1_IONUM); // start transmitting
+		#endif
+	
+		#ifdef USART1_USE_SOFT_CTS
+			if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+		#endif
+			{
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				UCSR1B_REGISTER |= (1<<UDRIE1_BIT); // enable UDRE interrupt
+			#else
+				asm volatile("\n\t"
+					"lds r25, %M[control_reg] \n\t"
+					"ori r25, (1<<%M[udrie_bit]) \n\t"
+					"sts %M[control_reg], r25 \n\t"
+					: // outputs
+					: // inputs
+					[control_reg] "n" (_SFR_MEM_ADDR(UCSR1B_REGISTER)),
+					[udrie_bit]   "M" (UDRIE1_BIT)
+					: // clobbers
+					"r25"
+				);
+			#endif
+			}
+		}
+	
+		reti();
+		
+		asm volatile("\n\t"::"r" (data):); // data was passed in r24 and will be returned in the same register, make sure it is not affected by the compiler 
+	}
+	
+	char uart1_putc_(char data) __attribute__ ((alias ("uart1_putc"))); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart1_putc_noblock(char data)
+	{
+	#ifdef USART1_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx1_Head;
+		register uint8_t tmp_tx_Tail = tx1_Tail;
+	
+	#ifdef USART1_USE_SOFT_CTS
+		if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR1A_REGISTER & UDRE1_BIT))
+		{
+			UDR1_REGISTER = data;
+			return COMPLETED;
+		}
+	
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX1_BUFFER_MASK;
+	
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx1_Head + 1) & TX1_BUFFER_MASK; // calculate new position of TX head in buffer
+	
+		if(tx1_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		tx1_buffer[tmp_tx_Head] = data;
+	
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx1_Head = tmp_tx_Head;
+		
+		#ifdef USART1_RS485_MODE
+			RS485_CONTROL1_PORT |= (1<<RS485_CONTROL1_IONUM); //set high
+		#endif
+		
+		#ifdef USART1_USE_SOFT_CTS
+			if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+		#endif
+			{
+				UCSR1B_REGISTER |= (1<<UDRIE1_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#else //!USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart1_putc_noblock(char data)
+	{
+	#ifdef USART1_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx1_Head;
+		register uint8_t tmp_tx_Tail = tx1_Tail;
+		
+	#ifdef USART1_USE_SOFT_CTS
+		if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR1A_REGISTER & UDRE1_BIT))
+		{
+			UDR1_REGISTER = data;
+			return COMPLETED;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX1_BUFFER_MASK;
+		
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx1_Head + 1) & TX1_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		if(tx1_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx1_buffer)) \n\t"
+			"sbci r27, hi8(-(tx1_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data) 
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx1_Head = tmp_tx_Head;
+			
+		#ifdef USART1_RS485_MODE
+			RS485_CONTROL1_PORT |= (1<<RS485_CONTROL1_IONUM); // start transmitting
+		#endif
+			
+		#ifdef USART1_USE_SOFT_CTS
+			if(!(CTS1_PIN & (1<<CTS1_IONUM)))
+		#endif
+			{
+				UCSR1B_REGISTER |= (1<<UDRIE1_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putstr(char *string)
+	{
+		char c;
+		while ((c = *string++)) uart1_putc(c);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putstr(char *string)
+	{
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"ld r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart1_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		while(BytesToWrite--)
+			uart1_putc(*string++);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		asm volatile("\n\t"
+			"add %[counter], r30 \n\t" // add ZL to a counter to compare against current pointer (8 bit length, doesn't care if overflow)
+		"load_loop_%=:"
+			"cp %[counter], r30\n\t"
+			"breq skip_loop_%= \n\t"
+			"ld r24, Z+ \n\t"
+			"rcall uart1_putc \n\t" // counter and Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			[counter] "r" (BytesToWrite),
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_puts_p(const __flash char *string)
+	{
+		register char c;
+		while ( (c = *string++) ) uart1_putc(c); 
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_puts_p(const __flash char *string)
+	{
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"lpm r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart1_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+	
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	void uart1_putint(int16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		itoa(data, u_tmp_buff, 10);
+		uart1_putstr(u_tmp_buff);
+	}
+
+	void uart1_putintr(int16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		itoa(data, u_tmp_buff, radix);
+		uart1_putstr(u_tmp_buff);
+	}
+
+	void uart1_putuint(uint16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		utoa(data, u_tmp_buff, 10);
+		uart1_putstr(u_tmp_buff);
+	}
+	
+	void uart1_putuintr(uint16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		utoa(data, u_tmp_buff, radix);
+		uart1_putstr(u_tmp_buff);
+	}
+
+	void uart1_puthex(uint8_t data)
+	{
+		uint8_t tmp; 
+		
+		tmp = (data >> 4) & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart1_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart1_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+		
+		tmp = data & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart1_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart1_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+	}
+
+	void uart1_putlong(int32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, 10);
+		uart1_putstr(u_tmp_buff);
+	}
+	
+	void uart1_putlongr(int32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, radix);
+		uart1_putstr(u_tmp_buff);
+	}
+	
+	void uart1_putulong(uint32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, 10);
+		uart1_putstr(u_tmp_buff);
+	}
+	
+	void uart1_putulongr(uint32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, radix);
+		uart1_putstr(u_tmp_buff);
+	}
+
+	void uart1_putfloat(float data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, 6, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart1_putstr(p);
+	}
+
+	void uart1_fputfloat(float data, uint8_t precision)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, precision, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart1_putstr(p);
+	}
+	
+	void uart1_flush(void)
+	{
+	#ifdef USART1_RS485_MODE // flush UDR buffer
+		while (RS485_CONTROL1_PORT & (1<<RS485_CONTROL1_IONUM));
+	#else	
+		while(tx1_Tail != tx1_Head); // just flush the ring buffer 
+	#endif
+	}
+
+#ifdef USART1_MPCM_MODE
+	void uart1_mpcm_transmit_addres_Frame(uint8_t dat)
+	{
+		while(tx1_Tail != tx1_Head);
+		UCSR1B_REGISTER |= (1<<TXB81_BIT);
+		uart1_putc(dat);
+		while(tx1_Tail != tx1_Head);
+		UCSR1B_REGISTER &= ~(1<<TXB81_BIT); // not sure if necessary
+	}
+#endif
+#endif // NO_TX1_INTERRUPT
+
+#ifndef NO_TX2_INTERRUPT
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putc(char data)
+	{
+	#ifdef PUTC2_CONVERT_LF_TO_CRLF
+		if (data == '\n')
+			uart2_putc('\r');
+	#endif
+		
+	#ifdef USART2_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx2_Head;
+		register uint8_t tmp_tx_Tail = tx2_Tail;
+		
+	#ifdef USART2_USE_SOFT_CTS
+		if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR2A_REGISTER & UDRE2_BIT))
+		{
+			UDR2_REGISTER = data;
+			return;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX2_BUFFER_MASK;
+		
+		while(tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer
+		{
+			tmp_tx_Tail = tx2_Tail; // for faster pass through, results in a little bigger code
+		}
+	#else
+		register uint8_t tmp_tx_Head = (tx2_Head + 1) & TX2_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		while(tx2_Tail == tmp_tx_Head); // wait for free space in buffer
+	#endif
+		
+		tx2_buffer[tmp_tx_Head] = data;
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx2_Head = tmp_tx_Head;
+			
+		#ifdef USART2_RS485_MODE
+			RS485_CONTROL2_PORT |= (1<<RS485_CONTROL2_IONUM); //set high
+		#endif
+			
+		#ifdef USART2_USE_SOFT_CTS
+			if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+		#endif
+			{
+				UCSR2B_REGISTER |= (1<<UDRIE2_BIT); // enable UDRE interrupt
+			}
+		}
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putc(char data)
+	{
+		register uint8_t tmp_tx_Head asm("r25");
+		
+	#ifdef PUTC2_CONVERT_LF_TO_CRLF
+		asm volatile("\n\t"
+			"cpi %[dat], '\n' \n\t"
+			"brne skip_recursive_%=\n\t"
+			"push %[dat] \n\t"
+			"ldi %[dat], '\r' \n\t"
+			"rcall uart2_putc \n\t"
+			"pop %[dat] \n\t"
+		"skip_recursive_%=:"
+			: // outputs
+			[dat]  "+r" (data) // will be used later, do not let the compiler to do anything weird
+			: // inputs
+			: // clobbers
+		);
+	#endif
+		
+	#ifdef USART2_PUTC_FAST_INSERTIONS
+			
+		asm volatile("\n\t"
+			"lds %[head], (tx2_Head) \n\t"
+			
+		#ifdef USART2_USE_SOFT_CTS
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"rjmp normal_insert_%= \n\t"  
+		#endif
+				
+			"lds r27, (tx2_Tail) \n\t"
+			"cpse r27, %[head] \n\t"
+			"rjmp normal_insert_%= \n\t"
+			
+			"lds r26, %M[UCSRA_reg] \n\t"
+			"sbrs r26, %M[udre_bit] \n\t"
+			"rjmp normal_insert_%= \n\t"
+				
+			"sts %M[UDR_reg], %[dat] \n\t"
+			"ret \n\t"
+				
+		"normal_insert_%=:"
+			"inc %[head] \n\t"
+			
+		#if (TX2_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx2_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head),
+			[dat]  "+r" (data)
+			: // inputs
+		#ifdef USART2_USE_SOFT_CTS
+			[cts_port]      "M"    (_SFR_IO_ADDR(CTS2_PORT)),
+			[cts_pin]       "M"    (CTS2_IONUM),
+		#endif
+			[mask]          "M" (TX2_BUFFER_MASK),
+			[UCSRA_reg]     "n" (_SFR_MEM_ADDR(UCSR2A_REGISTER)),
+			[UCSRA_reg_IO]  "M" (_SFR_IO_ADDR(UCSR2A_REGISTER)),
+			[UDR_reg]	    "n" (_SFR_MEM_ADDR(UDR2_REGISTER)),
+			[UDR_reg_IO]    "M" (_SFR_IO_ADDR(UDR2_REGISTER)),
+			[udre_bit]      "M"	(UDRE2_BIT)
+			: // clobbers
+			"r26","r27"
+		);
+	#else
+		asm volatile("\n\t"
+			"lds %[head], (tx2_Head) \n\t"
+			"inc %[head] \n\t"
+			
+		#if (TX2_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx2_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head)
+			: // inputs
+			[mask] "M" (TX2_BUFFER_MASK)
+			: // clobbers
+			"r27"
+		);
+	#endif
+		
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx2_buffer)) \n\t"
+			"sbci r27, hi8(-(tx2_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		cli();
+		{
+			tx2_Head = tmp_tx_Head;
+		
+		#ifdef USART2_RS485_MODE
+			RS485_CONTROL2_PORT |= (1<<RS485_CONTROL2_IONUM); // start transmitting
+		#endif
+		
+		#ifdef USART2_USE_SOFT_CTS
+			if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+		#endif
+			{
+				asm volatile("\n\t"
+					"lds r25, %M[control_reg] \n\t"
+					"ori r25, (1<<%M[udrie_bit]) \n\t"
+					"sts %M[control_reg], r25 \n\t"
+					: // outputs
+					: // inputs
+					[control_reg] "n" (_SFR_MEM_ADDR(UCSR2B_REGISTER)),
+					[udrie_bit]   "M" (UDRIE2_BIT)
+					: // clobbers
+					"r25"
+				);
+			}
+		}
+	
+		reti();
+		asm volatile("\n\t"::"r" (data):); // data was passed in r24 and will be returned in the same register, make sure it is not affected by the compiler 
+	}
+	
+	char uart2_putc_(char data) __attribute__ ((alias ("uart2_putc"))); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart2_putc_noblock(char data)
+	{
+	#ifdef USART2_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx2_Head;
+		register uint8_t tmp_tx_Tail = tx2_Tail;
+	
+	#ifdef USART2_USE_SOFT_CTS
+		if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR2A_REGISTER & UDRE2_BIT))
+		{
+			UDR2_REGISTER = data;
+			return COMPLETED;
+		}
+	
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX2_BUFFER_MASK;
+	
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx2_Head + 1) & TX2_BUFFER_MASK; // calculate new position of TX head in buffer
+	
+		if(tx2_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		tx2_buffer[tmp_tx_Head] = data;
+	
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx2_Head = tmp_tx_Head;
+		
+		#ifdef USART2_RS485_MODE
+			RS485_CONTROL2_PORT |= (1<<RS485_CONTROL2_IONUM); //set high
+		#endif
+		
+		#ifdef USART2_USE_SOFT_CTS
+			if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+		#endif
+			{
+				UCSR2B_REGISTER |= (1<<UDRIE2_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart2_putc_noblock(char data)
+	{
+	#ifdef USART2_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx2_Head;
+		register uint8_t tmp_tx_Tail = tx2_Tail;
+		
+	#ifdef USART2_USE_SOFT_CTS
+		if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR2A_REGISTER & UDRE2_BIT))
+		{
+			UDR2_REGISTER = data;
+			return COMPLETED;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX2_BUFFER_MASK;
+		
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx2_Head + 1) & TX2_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		if(tx2_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx2_buffer)) \n\t"
+			"sbci r27, hi8(-(tx2_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx2_Head = tmp_tx_Head;
+			
+		#ifdef USART2_RS485_MODE
+			RS485_CONTROL2_PORT |= (1<<RS485_CONTROL2_IONUM); // start transmitting
+		#endif
+			
+		#ifdef USART2_USE_SOFT_CTS
+			if(!(CTS2_PIN & (1<<CTS2_IONUM)))
+		#endif
+			{
+				UCSR2B_REGISTER |= (1<<UDRIE2_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+	
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putstr(char *string)
+	{
+		char c;
+		while ((c = *string++)) uart2_putc(c);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putstr(char *string)
+	{
+		asm volatile("\n\t"
+			
+		"load_loop_%=:"
+			"ld r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart2_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		while(BytesToWrite--)
+			uart2_putc(*string++);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		asm volatile("\n\t"
+			"add %[counter], r30 \n\t" // add ZL to a counter to compare against current pointer (8 bit length, doesn't care if overflow)
+		"load_loop_%=:"
+			"cp %[counter], r30\n\t"
+			"breq skip_loop_%= \n\t"
+			"ld r24, Z+ \n\t"
+			"rcall uart2_putc \n\t" // counter and Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			[counter] "r" (BytesToWrite),
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_puts_p(const __flash char *string)
+	{
+		register char c;
+		while ( (c = *string++) ) uart2_putc(c);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_puts_p(const __flash char *string)
+	{
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"lpm r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart2_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+	
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	void uart2_putint(int16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		itoa(data, u_tmp_buff, 10);
+		uart2_putstr(u_tmp_buff);
+	}
+
+	void uart2_putintr(int16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		itoa(data, u_tmp_buff, radix);
+		uart2_putstr(u_tmp_buff);
+	}
+
+	void uart2_putuint(uint16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		utoa(data, u_tmp_buff, 10);
+		uart2_putstr(u_tmp_buff);
+	}
+	
+	void uart2_putuintr(uint16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		utoa(data, u_tmp_buff, radix);
+		uart2_putstr(u_tmp_buff);
+	}
+
+	void uart2_puthex(uint8_t data)
+	{
+		uint8_t tmp; 
+		
+		tmp = (data >> 4) & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart2_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart2_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+		
+		tmp = data & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart2_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart2_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+	}
+
+	void uart2_putlong(int32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, 10);
+		uart2_putstr(u_tmp_buff);
+	}
+	
+	void uart2_putlongr(int32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, radix);
+		uart2_putstr(u_tmp_buff);
+	}
+	
+	void uart2_putulong(uint32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, 10);
+		uart2_putstr(u_tmp_buff);
+	}
+	
+	void uart2_putulongr(uint32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, radix);
+		uart2_putstr(u_tmp_buff);
+	}
+
+	void uart2_putfloat(float data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, 6, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart2_putstr(p);
+	}
+
+	void uart2_fputfloat(float data, uint8_t precision)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, precision, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart2_putstr(p);
+	}
+	
+	void uart2_flush(void)
+	{
+	#ifdef USART2_RS485_MODE // flush UDR buffer
+		while (RS485_CONTROL2_PORT & (1<<RS485_CONTROL2_IONUM));
+	#else	
+		while(tx2_Tail != tx2_Head); // just flush the ring buffer 
+	#endif
+	}
+
+#ifdef USART2_MPCM_MODE
+	void uart2_mpcm_transmit_addres_Frame(uint8_t dat)
+	{
+		while(tx2_Tail != tx2_Head);
+		UCSR2B_REGISTER |= (1<<TXB82_BIT);
+		uart2_putc(dat);
+		while(tx2_Tail != tx2_Head);
+		UCSR2B_REGISTER &= ~(1<<TXB82_BIT); // not sure if necessary
+	}
+#endif
+#endif // NO_TX2_INTERRUPT
+
+#ifndef NO_TX3_INTERRUPT
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putc(char data)
+	{
+	#ifdef PUTC3_CONVERT_LF_TO_CRLF
+		if (data == '\n')
+			uart3_putc('\r');
+	#endif
+		
+	#ifdef USART3_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx3_Head;
+		register uint8_t tmp_tx_Tail = tx3_Tail;
+		
+	#ifdef USART3_USE_SOFT_CTS
+		if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR3A_REGISTER & UDRE3_BIT))
+		{
+			UDR3_REGISTER = data;
+			return;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX3_BUFFER_MASK;
+		
+		while(tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer
+		{
+			tmp_tx_Tail = tx3_Tail; // for faster pass through, results in a little bigger code
+		}
+	#else
+		register uint8_t tmp_tx_Head = (tx3_Head + 1) & TX3_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		while(tx3_Tail == tmp_tx_Head); // wait for free space in buffer
+	#endif
+		
+		tx3_buffer[tmp_tx_Head] = data;
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx3_Head = tmp_tx_Head;
+			
+		#ifdef USART3_RS485_MODE
+			RS485_CONTROL3_PORT |= (1<<RS485_CONTROL3_IONUM); //set high
+		#endif
+			
+		#ifdef USART3_USE_SOFT_CTS
+			if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+		#endif
+			{
+				UCSR3B_REGISTER |= (1<<UDRIE3_BIT); // enable UDRE interrupt
+			}
+		}
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putc(char data)
+	{
+		register uint8_t tmp_tx_Head asm("r25");
+		
+	#ifdef PUTC3_CONVERT_LF_TO_CRLF
+		asm volatile("\n\t"
+			"cpi %[dat], '\n' \n\t"
+			"brne skip_recursive_%=\n\t"
+			"push %[dat] \n\t"
+			"ldi %[dat], '\r' \n\t"
+			"rcall uart3_putc \n\t"
+			"pop %[dat] \n\t"
+		"skip_recursive_%=:"
+			: // outputs
+			[dat]  "+r" (data) // will be used later, do not let the compiler to do anything weird
+			: // inputs
+			: // clobbers
+		);
+	#endif
+		
+	#ifdef USART3_PUTC_FAST_INSERTIONS
+		
+		asm volatile("\n\t"
+			"lds %[head], (tx3_Head) \n\t"
+			
+		#ifdef USART3_USE_SOFT_CTS
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"rjmp normal_insert_%= \n\t"  
+		#endif
+				
+			"lds r27, (tx3_Tail) \n\t"
+			"cpse r27, %[head] \n\t"
+			"rjmp normal_insert_%= \n\t"
+			
+			"lds r26, %M[UCSRA_reg] \n\t"
+			"sbrs r26, %M[udre_bit] \n\t"
+			"rjmp normal_insert_%= \n\t"
+				
+			"sts %M[UDR_reg], %[dat] \n\t"
+			"ret \n\t"
+				
+		"normal_insert_%=:"
+			"inc %[head] \n\t"
+			
+		#if (TX3_BUFFER_MASK != 0xff)
+			"andi %[head], %M[mask] \n\t"
+		#endif
+				
+		"waitforspace_%=:"
+			"lds r27, (tx3_Tail) \n\t"
+			"cp r27, %[head] \n\t"
+			"breq waitforspace_%= \n\t"
+				
+			: // outputs
+			[head] "=r" (tmp_tx_Head),
+			[dat]  "+r" (data)
+			: // inputs
+		#ifdef USART3_USE_SOFT_CTS
+			[cts_port]      "M"    (_SFR_IO_ADDR(CTS3_PORT)),
+			[cts_pin]       "M"    (CTS3_IONUM),
+		#endif
+			[mask]          "M" (TX2_BUFFER_MASK),
+			[UCSRA_reg]     "n" (_SFR_MEM_ADDR(UCSR3A_REGISTER)),
+			[UCSRA_reg_IO]  "M" (_SFR_IO_ADDR(UCSR3A_REGISTER)),
+			[UDR_reg]	    "n" (_SFR_MEM_ADDR(UDR3_REGISTER)),
+			[UDR_reg_IO]    "M" (_SFR_IO_ADDR(UDR3_REGISTER)),
+			[udre_bit]      "M"	(UDRE3_BIT)
+			: // clobbers
+			"r26","r27"
+		);
+	#else
+			asm volatile("\n\t"
+				"lds %[head], (tx3_Head) \n\t"
+				"inc %[head] \n\t"
+			
+			#if (TX3_BUFFER_MASK != 0xff)
+				"andi %[head], %M[mask] \n\t"
+			#endif
+				
+			"waitforspace_%=:"
+				"lds r27, (tx3_Tail) \n\t"
+				"cp r27, %[head] \n\t"
+				"breq waitforspace_%= \n\t"
+				
+				: // outputs
+				[head] "=r" (tmp_tx_Head)
+				: // inputs
+				[mask] "M" (TX3_BUFFER_MASK)
+				: // clobbers
+				"r27"
+			);
+	#endif
+		
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx3_buffer)) \n\t"
+			"sbci r27, hi8(-(tx3_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		cli();
+		{
+			tx3_Head = tmp_tx_Head;
+		
+		#ifdef USART3_RS485_MODE
+			RS485_CONTROL3_PORT |= (1<<RS485_CONTROL3_IONUM); // start transmitting
+		#endif
+		
+		#ifdef USART3_USE_SOFT_CTS
+			if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+		#endif
+			{
+				asm volatile("\n\t"
+					"lds r25, %M[control_reg] \n\t"
+					"ori r25, (1<<%M[udrie_bit]) \n\t"
+					"sts %M[control_reg], r25 \n\t"
+					: // outputs
+					: // inputs
+					[control_reg] "n" (_SFR_MEM_ADDR(UCSR3B_REGISTER)),
+					[udrie_bit]   "M" (UDRIE3_BIT)
+					: // clobbers
+					"r25"
+				);
+			}
+		}
+	
+		reti();
+		
+		asm volatile("\n\t"::"r" (data):); // data was passed in r24 and will be returned in the same register, make sure it is not affected by the compiler 
+	}
+	
+	char uart3_putc_(char data) __attribute__ ((alias ("uart3_putc"))); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart3_putc_noblock(char data)
+	{
+	#ifdef USART3_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx3_Head;
+		register uint8_t tmp_tx_Tail = tx3_Tail;
+	
+	#ifdef USART3_USE_SOFT_CTS
+		if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR3A_REGISTER & UDRE3_BIT))
+		{
+			UDR3_REGISTER = data;
+			return COMPLETED;
+		}
+	
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX3_BUFFER_MASK;
+	
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx3_Head + 1) & TX3_BUFFER_MASK; // calculate new position of TX head in buffer
+	
+		if(tx3_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		tx3_buffer[tmp_tx_Head] = data;
+	
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx3_Head = tmp_tx_Head;
+		
+		#ifdef USART3_RS485_MODE
+			RS485_CONTROL3_PORT |= (1<<RS485_CONTROL3_IONUM); //set high
+		#endif
+		
+		#ifdef USART3_USE_SOFT_CTS
+			if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+		#endif
+			{
+				UCSR3B_REGISTER |= (1<<UDRIE3_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#else //!USART_NO_ABI_BREAKING_PREMATURES
+	uint8_t uart3_putc_noblock(char data)
+	{
+	#ifdef USART3_PUTC_FAST_INSERTIONS
+		register uint8_t tmp_tx_Head = tx3_Head;
+		register uint8_t tmp_tx_Tail = tx3_Tail;
+		
+	#ifdef USART3_USE_SOFT_CTS
+		if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+	#endif
+		if(tmp_tx_Tail == tmp_tx_Head && (UCSR3A_REGISTER & UDRE3_BIT))
+		{
+			UDR3_REGISTER = data;
+			return COMPLETED;
+		}
+		
+		tmp_tx_Head = (tmp_tx_Head + 1) & TX3_BUFFER_MASK;
+		
+		if(tmp_tx_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#else
+		register uint8_t tmp_tx_Head = (tx3_Head + 1) & TX3_BUFFER_MASK; // calculate new position of TX head in buffer
+		
+		if(tx3_Tail == tmp_tx_Head)
+			return BUFFER_FULL;
+	#endif
+	
+		asm volatile("\n\t"
+			"mov r26, %[index]  \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(tx3_buffer)) \n\t"
+			"sbci r27, hi8(-(tx3_buffer)) \n\t"
+			"st X, %[dat] \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_tx_Head),
+			[dat]   "+r" (data)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
+		{
+			tx3_Head = tmp_tx_Head;
+			
+		#ifdef USART3_RS485_MODE
+			RS485_CONTROL3_PORT |= (1<<RS485_CONTROL3_IONUM); // start transmitting
+		#endif
+			
+		#ifdef USART3_USE_SOFT_CTS
+			if(!(CTS3_PIN & (1<<CTS3_IONUM)))
+		#endif
+			{
+				UCSR3B_REGISTER |= (1<<UDRIE3_BIT); // enable UDRE interrupt
+			}
+		}
+		return COMPLETED;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putstr(char *string)
+	{
+		char c;
+		while ((c = *string++)) uart3_putc(c);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putstr(char *string)
+	{
+		asm volatile("\n\t"
+		
+		"load_loop_%=:"
+			"ld r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart3_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		while(BytesToWrite--)
+			uart3_putc(*string++);
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_putstrl(char *string, uint8_t BytesToWrite)
+	{
+		asm volatile("\n\t"
+			"add %[counter], r30 \n\t" // add ZL to a counter to compare against current pointer (8 bit length, doesn't care if overflow)
+		"load_loop_%=:"
+			"cp %[counter], r30\n\t"
+			"breq skip_loop_%= \n\t"
+			"ld r24, Z+ \n\t"
+			"rcall uart3_putc \n\t" // counter and Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+		
+			: // outputs
+			: // inputs
+			[counter] "r" (BytesToWrite),
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_puts_p(const __flash char *string)
+	{
+		register char c;
+		while ( (c = *string++) ) uart3_putc(c); 
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_puts_p(const __flash char *string)
+	{
+		asm volatile("\n\t"
+			
+		"load_loop_%=:"
+			"lpm r24, Z+ \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq skip_loop_%= \n\t"
+			"rcall uart3_putc \n\t" // Z pointer will not be affected in uart_putc()
+			"rjmp load_loop_%= \n\t"
+		"skip_loop_%=:"
+	
+			: // outputs
+			: // inputs
+			"z" (string)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_putc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	void uart3_putint(int16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		itoa(data, u_tmp_buff, 10);
+		uart3_putstr(u_tmp_buff);
+	}
+
+	void uart3_putintr(int16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		itoa(data, u_tmp_buff, radix);
+		uart3_putstr(u_tmp_buff);
+	}
+
+	void uart3_putuint(uint16_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		utoa(data, u_tmp_buff, 10);
+		uart3_putstr(u_tmp_buff);
+	}
+	
+	void uart3_putuintr(uint16_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		utoa(data, u_tmp_buff, radix);
+		uart3_putstr(u_tmp_buff);
+	}
+
+	void uart3_puthex(uint8_t data)
+	{
+		uint8_t tmp; 
+		
+		tmp = (data >> 4) & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart3_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart3_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+		
+		tmp = data & 0x0f;
+	#ifdef USART_PUTHEX_IN_UPPERCASE
+		uart3_putc( (tmp <= 9 ? '0' + tmp : 'A' - 10 + tmp));
+	#else
+		uart3_putc( (tmp <= 9 ? '0' + tmp : 'a' - 10 + tmp));
+	#endif
+	}
+
+	void uart3_putlong(int32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, 10);
+		uart3_putstr(u_tmp_buff);
+	}
+	
+	void uart3_putlongr(int32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ltoa(data, u_tmp_buff, radix);
+		uart3_putstr(u_tmp_buff);
+	}
+	
+	void uart3_putulong(uint32_t data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, 10);
+		uart3_putstr(u_tmp_buff);
+	}
+	
+	void uart3_putulongr(uint32_t data, uint8_t radix)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[17]; // heading, 15 digit bytes, NULL
+	#endif
+		
+		ultoa(data, u_tmp_buff, radix);
+		uart3_putstr(u_tmp_buff);
+	}
+
+	void uart3_putfloat(float data)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, 6, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart3_putstr(p);
+	}
+
+	void uart3_fputfloat(float data, uint8_t precision)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[16];
+	#endif
+		
+		dtostrf(data, 15, precision, u_tmp_buff);
+		
+		char *p = u_tmp_buff;
+		while(*p == ' ') // remove all unwanted spaces
+			p++;
+		
+		uart3_putstr(p);
+	}
+	
+	void uart3_flush(void)
+	{
+	#ifdef USART3_RS485_MODE // flush UDR buffer
+		while (RS485_CONTROL3_PORT & (1<<RS485_CONTROL3_IONUM));
+	#else	
+		while(tx3_Tail != tx3_Head); // just flush the ring buffer 
+	#endif
+	}
+
+#ifdef USART3_MPCM_MODE
+	void uart3_mpcm_transmit_addres_Frame(uint8_t dat)
+	{
+		while(tx3_Tail != tx3_Head);
+		UCSR3B_REGISTER |= (1<<TXB83_BIT);
+		uart3_putc(dat);
+		while(tx3_Tail != tx3_Head);
+		UCSR3B_REGISTER &= ~(1<<TXB83_BIT); // not sure if necessary
+	}
+#endif
+#endif // NO_TX3_INTERRUPT
+
+#endif // NO_USART_TX
+
+#ifndef NO_USART_RX
+
+#ifndef NO_RX0_INTERRUPT
+//******************************************************************
+//Function  : To receive single character/byte.
+//Arguments : none
+//Return    : Received character or NULL if buffer is empty.
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	char uart0_getc(void)
+	{
+		register uint8_t tmp_rx_Tail = rx0_Tail;
+		char tmp;
+		
+		if(tmp_rx_Tail == rx0_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX0_BUFFER_MASK;
+		tmp = rx0_buffer[tmp_rx_Tail];
+		
+		rx0_Tail = tmp_rx_Tail;
+		
+	#ifdef USART0_EXTEND_RX_BUFFER
+		UCSR0B_REGISTER |= (1<<RXCIE0_BIT);
+	#endif
+		
+	#ifdef USART0_USE_SOFT_RTS
+		if (RTS0_PORT & (1<<RTS0_IONUM))
+			if (!(UCSR0A_REGISTER & (1<<RXC0_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)
+				RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+		
+	#ifdef RX0_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart0_putc('\r');
+		#endif
+		
+		tmp = uart0_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r')
+				uart0_putc('\n');
+		#endif
+	#endif // RX0_GETC_ECHO
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	char uart0_getc(void)
+	{
+		register uint8_t tmp_rx_Tail asm("r25");
+		char tmp;
+		
+		tmp_rx_Tail = rx0_Tail;
+		
+		if(tmp_rx_Tail == rx0_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX0_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+		
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__) // on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r27, 0x00 \n\t"
+		#endif
+			"subi r26, lo8(-(rx0_buffer)) \n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r27, hi8(-(rx0_buffer)) \n\t"
+		#endif
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp]  "=r" (tmp)
+			: // inputs
+			: // clobbers
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__)
+			"r27",
+		#endif
+			"r26"
+		);
+	
+		rx0_Tail = tmp_rx_Tail;
+	
+	#ifdef USART0_EXTEND_RX_BUFFER
+		UCSR0B_REGISTER |= (1<<RXCIE0_BIT);
+	#endif
+	
+	#ifdef USART0_USE_SOFT_RTS
+		if (RTS0_PORT & (1<<RTS0_IONUM))
+			if (!(UCSR0A_REGISTER & (1<<RXC0_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)		
+				RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+	
+	#ifdef RX0_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart0_putc('\r');
+		#endif
+		
+		tmp = uart0_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r')
+				uart0_putc('\n');
+		#endif
+	#endif // RX0_GETC_ECHO
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Reads actual string from receiver buffer.
+//Arguments : Pointer to array to fill with received string.
+//Return    : none
+//Note      : Received string will be terminated by NULL.
+//          : OBSOLETE - possibility of buffer overflows
+//******************************************************************
+//	void uart0_getBuffer(char *buffer)
+//	{
+//		do *buffer = uart_getc();
+//		while(*buffer++);
+//	}
+	
+//******************************************************************
+//Function  : Reads string from receiver buffer
+//Arguments : 1. Pointer to array to fill with received string.
+//          : 2. Limit for receiving string size (array size)
+//Return    :    none
+//Note      : Received string will be terminated by NULL positioned at bufferlimit-1
+//          : or at the end of the string if it's shorter than bufferlimit-1
+//			: terminators CR LF will not be cut
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_gets(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			*buffer = uart0_getc();
+			if(*buffer++ == 0)
+				break;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_gets(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+			"rcall uart0_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"st Z+, r24 \n\t"
+			"cpse r24, __zero_reg__ \n\t"
+			"rjmp loop_%= \n\t"
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Reads one line from the receiver buffer. (waits for EOL terminator)
+//Arguments : 1. Pointer to array to fill with received string.
+//          : 2. Limit for receiving string size (array size)
+//Return    :    none
+//Note      : Received string will be terminated by NULL positioned at bufferlimit-1
+//          : or at the end of the string if it's shorter than bufferlimit-1
+//          : CR and LF terminators will be cut. 
+//          : Function will return if bufferlimit is reached without waiting for newline terminator
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_getln(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart0_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart0_getc()) );
+			#endif
+				break;
+			}
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_getln(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart0_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq wait_loop2_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_RN
+		"wait_loop2_%=:"
+			"rcall uart0_getc \n\t"
+			"and r24, r24 \n\t"
+			"breq wait_loop2_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24"
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : Reads burst of characters until first whitespace (waits for EOL terminator or first whitespace)
+//Arguments : 1. Pointer to array to fill with received string.
+//          : 2. Limit for receiving string size (array size)
+//Return    :    none
+//Note      : Received string will be terminated by NULL positioned at bufferlimit-1
+//          : or at the end of the string if it's shorter than bufferlimit-1
+//          : CR and LF terminators will be cut.
+//          : Function will return if bufferlimit is reached without waiting for newline terminator
+//          : Function will cut all whitespaces before first nonspace character
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		do{
+			*buffer = uart0_getc();
+		}while(*buffer <= 32);
+		
+		buffer++;
+		bufferlimit--;
+		
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart0_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else 
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart0_getc()) );
+			#endif
+				break;
+			}
+			else if(*buffer <= 32)
+				break; // string reading is done, we will exit
+
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart0_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"skip_whitespaces_loop_%=:"
+			"rcall uart0_getc \n\t" // counter and Z pointer will not be affected in uart0_getc()
+			"cpi r24, 0x21\n\t" // if(tmp <= 32)
+			"brcs skip_whitespaces_loop_%= \n\t" // skip all received whitespaces
+			"st Z+, r24 \n\t"
+			"dec %[limit] \n\t"
+		
+		"loop_%=:"	
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart0_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+		
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq exit_wait_loop_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"cpi r24, 0x21 \n\t" // if(tmp <= 32)
+			"brcs store_NULL_%= \n\t" // whitespace means end of this function, quit loop
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%=\n\t"
+			
+		#ifdef RX_NEWLINE_MODE_RN
+		"exit_wait_loop_%=:"
+			"rcall uart0_getc \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq exit_wait_loop_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : To skip all incoming whitespace characters until first nonspace character.
+//Arguments : none
+//Return    : First received nonspace character.
+//Note      : First nonspace character is cut from receiver buffer.
+//******************************************************************
+// 	char uart0_skipWhiteSpaces(void)
+// 	{
+// 		register char c;
+// 		
+// 		do{
+//			c = uart0_getc();
+//		}while(c <= 32);
+// 		
+// 		return c;
+// 	}
+
+//******************************************************************
+//Function  : Read 16bit integer value from the input stream.
+//Arguments : none
+//Return    : Received 16bit integer value.
+//******************************************************************
+	int16_t uart0_getint(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		uart0_getlnToFirstWhiteSpace(u_tmp_buff, 7);
+		
+		return atoi(u_tmp_buff);
+	}
+
+//******************************************************************
+//Function  : Read 32bit integer value from the input stream.
+//Arguments : none
+//Return    : Received 32bit integer value
+//******************************************************************
+	int32_t uart0_getlong(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+	
+		uart0_getlnToFirstWhiteSpace(u_tmp_buff, 12);
+		
+		return atol(u_tmp_buff);
+	}
+
+//******************************************************************
+//Function  : Read floating point value from the input stream.
+//Arguments : none
+//Return    : Received float value.
+//******************************************************************
+	float uart0_getfloat(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[32];
+	#endif
+	
+		uart0_getlnToFirstWhiteSpace(u_tmp_buff, 32);
+		
+		return atof(u_tmp_buff);
+	}
+
+//******************************************************************
+//Function  : To receive single byte in binary transmission.
+//Arguments : none
+//Return    : Signed 16 bit integer containing data in lower 8 bits 
+//Note      : This function doesn't cut CR, LF, NULL terminators
+//          : If receiver buffer is empty, return value is negative 
+//          : so only sign bit have to be checked (x < 0 // x >= 0)
+//******************************************************************
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart0_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx0_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx0_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX0_BUFFER_MASK;
+		tmp = rx0_buffer[tmp_rx_Tail];
+		rx0_Tail = tmp_rx_Tail;
+		
+	#ifdef USART0_EXTEND_RX_BUFFER
+		UCSR0B_REGISTER |= (1<<RXCIE0_BIT);
+	#endif
+	
+	#ifdef USART0_USE_SOFT_RTS
+		if (RTS0_PORT & (1<<RTS0_IONUM))
+			if (!(UCSR0A_REGISTER & (1<<RXC0_BIT)))
+				RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart0_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx0_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx0_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX0_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+		
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__) // on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r27, 0x00 \n\t"
+		#endif
+			"subi r26, lo8(-(rx0_buffer)) \n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r27, hi8(-(rx0_buffer)) \n\t"
+		#endif
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp]  "=r" (tmp)
+			: // inputs
+			: // clobbers
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__)	
+			"r27",
+		#endif
+			"r26"
+		);
+		
+		rx0_Tail = tmp_rx_Tail;
+		
+	#ifdef USART0_EXTEND_RX_BUFFER
+		UCSR0B_REGISTER |= (1<<RXCIE0_BIT);
+	#endif
+	
+	#ifdef USART0_USE_SOFT_RTS
+		if (RTS0_PORT & (1<<RTS0_IONUM))
+			if (!(UCSR0A_REGISTER & (1<<RXC0_BIT)))
+				RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+//******************************************************************
+//Function  : To receive single byte in binary transmission.
+//Arguments : Pointer to byte which have to be filed by incoming data.
+//Return    : Status value: 0 = BUFFER_EMPTY, 1 = COMPLETED.
+//Note      : This function doesn't cut CR, LF, NULL terminators
+//          : If receiver buffer is empty return status = BUFFER_EMPTY instead of returning NULL (as in getc).
+//******************************************************************
+	uint8_t uart0_LoadData(uint8_t *data)
+	{
+		register uint8_t tmp_rx_Tail = rx0_Tail;
+		
+		if(tmp_rx_Tail == rx0_Head) return BUFFER_EMPTY; // result = 0
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX0_BUFFER_MASK;
+		*data = rx0_buffer[tmp_rx_Tail];
+		
+		rx0_Tail = tmp_rx_Tail;
+		
+	#ifdef USART0_EXTEND_RX_BUFFER
+		UCSR0B_REGISTER |= (1<<RXCIE0_BIT);
+	#endif
+	
+	#ifdef USART0_USE_SOFT_RTS
+		if (RTS0_PORT & (1<<RTS0_IONUM))
+			if (!(UCSR0A_REGISTER & (1<<RXC0_BIT)))	
+				RTS0_PORT &= ~(1<<RTS0_IONUM);
+	#endif
+		
+		return COMPLETED; // result = 1
+	}
+
+//******************************************************************
+//Function  : To check how many bytes are waiting in the receiver buffer.
+//Arguments : none
+//Return    : Number of bytes waiting in receiver buffer.
+//******************************************************************
+//	uint8_t uart0_AvailableBytes(void)
+//	{
+//		return (rx0_Head - rx0_Tail) & RX0_BUFFER_MASK;
+//	}
+	
+//******************************************************************
+//Function  : Peek at the next byte in buffer.
+//Arguments : none
+//Return    : Next byte in buffer.
+//******************************************************************
+	uint8_t uart0_peek(void)
+	{
+		return rx0_buffer[(rx0_Tail+1) & RX0_BUFFER_MASK];
+	}
+#endif // NO_RX0_INTERRUPT
+
+#ifndef NO_RX1_INTERRUPT
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	char uart1_getc(void)
+	{
+		register uint8_t tmp_rx_Tail = rx1_Tail;
+		char tmp;
+		
+		if(tmp_rx_Tail == rx1_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX1_BUFFER_MASK;
+		tmp = rx1_buffer[tmp_rx_Tail];
+		
+		rx1_Tail = tmp_rx_Tail;
+		
+	#ifdef USART1_EXTEND_RX_BUFFER
+		UCSR1B_REGISTER |= (1<<RXCIE1_BIT);
+	#endif
+		
+	#ifdef USART1_USE_SOFT_RTS
+		if (RTS1_PORT & (1<<RTS1_IONUM))
+			if (!(UCSR1A_REGISTER & (1<<RXC1_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)
+				RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+		
+	#ifdef RX1_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart1_putc('\r');
+		#endif
+		
+		tmp = uart1_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r')
+				uart1_putc('\n');
+		#endif
+	#endif // RX1_GETC_ECHO
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	char uart1_getc(void)
+	{
+		register uint8_t tmp_rx_Tail asm("r25");
+		char tmp;
+		
+		tmp_rx_Tail = rx1_Tail;
+		
+		if(tmp_rx_Tail == rx1_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX1_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx1_buffer)) \n\t"
+			"sbci r27, hi8(-(rx1_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp] "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+	
+		rx1_Tail = tmp_rx_Tail;
+	
+	#ifdef USART1_EXTEND_RX_BUFFER
+		UCSR1B_REGISTER |= (1<<RXCIE1_BIT);
+	#endif
+	
+	#ifdef USART1_USE_SOFT_RTS
+		if (RTS1_PORT & (1<<RTS1_IONUM))
+			if (!(UCSR1A_REGISTER & (1<<RXC1_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)		
+				RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+	
+	#ifdef RX1_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart1_putc('\r');
+		#endif
+		
+		tmp = uart1_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r') 
+				uart1_putc('\n');
+		#endif
+	#endif // RX1_GETC_ECHO
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_gets(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			*buffer = uart1_getc();
+			if(*buffer++ == 0)
+				break;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_gets(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+			"rcall uart1_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"st Z+, r24 \n\t"
+			"cpse r24, __zero_reg__ \n\t"
+			"rjmp loop_%= \n\t"
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+	
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_getln(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart1_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart1_getc()) );
+			#endif
+				break;
+			}
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_getln(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart1_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq wait_loop2_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_RN
+		"wait_loop2_%=:"
+			"rcall uart1_getc \n\t"
+			"and r24, r24 \n\t"
+			"breq wait_loop2_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		do{
+			*buffer = uart1_getc();
+		}while(*buffer <= 32);
+		
+		buffer++;
+		bufferlimit--;
+		
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart1_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else //RX_NEWLINE_MODE_R
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart1_getc()) );
+			#endif
+				break;
+			}
+			else if(*buffer <= 32)
+				break; // string reading is done, we will exit
+
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart1_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+			
+		"skip_whitespaces_loop_%=:"
+			"rcall uart1_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"cpi r24, 0x21\n\t" // if(tmp <= 32)
+			"brcs skip_whitespaces_loop_%= \n\t" // skip all received whitespaces
+			"st Z+, r24 \n\t"
+			"dec %[limit] \n\t"
+		
+		"loop_%=:"	
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart1_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+		
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq exit_wait_loop_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"cpi r24, 0x21 \n\t" // if(tmp <= 32)
+			"brcs store_NULL_%= \n\t" // whitespace means end of this function, quit loop
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%=\n\t"
+			
+		#ifdef RX_NEWLINE_MODE_RN
+		"exit_wait_loop_%=:"
+			"rcall uart1_getc \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq exit_wait_loop_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	int16_t uart1_getint(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		uart1_getlnToFirstWhiteSpace(u_tmp_buff, 7);
+		
+		return atoi(u_tmp_buff);
+	}
+
+	int32_t uart1_getlong(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+	
+		uart1_getlnToFirstWhiteSpace(u_tmp_buff, 12);
+		
+		return atol(u_tmp_buff);
+	}
+
+	float uart1_getfloat(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[32];
+	#endif
+	
+		uart1_getlnToFirstWhiteSpace(u_tmp_buff, 32);
+		
+		return atof(u_tmp_buff);
+	}
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart1_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx1_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx1_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX1_BUFFER_MASK;
+		tmp = rx1_buffer[tmp_rx_Tail];
+		rx1_Tail = tmp_rx_Tail;
+		
+	#ifdef USART1_EXTEND_RX_BUFFER
+		UCSR1B_REGISTER |= (1<<RXCIE1_BIT);
+	#endif
+	
+	#ifdef USART1_USE_SOFT_RTS
+		if (RTS1_PORT & (1<<RTS1_IONUM))
+			if (!(UCSR1A_REGISTER & (1<<RXC1_BIT)))
+				RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart1_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx1_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx1_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX1_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx1_buffer)) \n\t"
+			"sbci r27, hi8(-(rx1_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp]  "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		rx1_Tail = tmp_rx_Tail;
+		
+	#ifdef USART1_EXTEND_RX_BUFFER
+		UCSR1B_REGISTER |= (1<<RXCIE1_BIT);
+	#endif
+	
+	#ifdef USART1_USE_SOFT_RTS
+		if (RTS1_PORT & (1<<RTS1_IONUM))
+			if (!(UCSR1A_REGISTER & (1<<RXC1_BIT)))
+				RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	uint8_t uart1_LoadData(uint8_t *data)
+	{
+		register uint8_t tmp_rx_Tail = rx1_Tail;
+		
+		if(tmp_rx_Tail == rx1_Head) return BUFFER_EMPTY; // result = 0
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX1_BUFFER_MASK;
+		*data = rx1_buffer[tmp_rx_Tail];
+		
+		rx1_Tail = tmp_rx_Tail;
+		
+	#ifdef USART1_EXTEND_RX_BUFFER
+		UCSR1B_REGISTER |= (1<<RXCIE1_BIT);
+	#endif
+	
+	#ifdef USART1_USE_SOFT_RTS
+		if (RTS1_PORT & (1<<RTS1_IONUM))
+			if (!(UCSR1A_REGISTER & (1<<RXC1_BIT)))
+				RTS1_PORT &= ~(1<<RTS1_IONUM);
+	#endif
+		
+		return COMPLETED; // result = 1
+	}
+
+	//uint8_t uart1_AvailableBytes(void)
+	//{
+	//	return (rx1_Head - rx1_Tail) & RX1_BUFFER_MASK;
+	//}
+	
+	uint8_t uart1_peek(void)
+	{
+		return rx1_buffer[(rx1_Tail+1) & RX1_BUFFER_MASK];
+	}
+#endif // NO_RX1_INTERRUPT
+
+#ifndef NO_RX2_INTERRUPT
+	
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	char uart2_getc(void)
+	{
+		register uint8_t tmp_rx_Tail = rx2_Tail;
+		char tmp;
+		
+		if(tmp_rx_Tail == rx2_Head)
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX2_BUFFER_MASK;
+		tmp = rx2_buffer[tmp_rx_Tail];
+		
+		rx2_Tail = tmp_rx_Tail;
+		
+	#ifdef USART2_EXTEND_RX_BUFFER
+		UCSR2B_REGISTER |= (1<<RXCIE2_BIT);
+	#endif
+		
+	#ifdef USART2_USE_SOFT_RTS
+		if (RTS2_PORT & (1<<RTS2_IONUM))
+			if (!(UCSR2A_REGISTER & (1<<RXC2_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)
+				RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+		
+	#ifdef RX2_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart2_putc('\r');
+		#endif
+		
+		tmp = uart2_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r')
+				uart2_putc('\n');
+		#endif
+	#endif // RX2_GETC_ECHO
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	char uart2_getc(void)
+	{
+		register uint8_t tmp_rx_Tail asm("r25");
+		char tmp;
+		
+		tmp_rx_Tail = rx2_Tail;
+		
+		if(tmp_rx_Tail == rx2_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX2_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx2_buffer)) \n\t"
+			"sbci r27, hi8(-(rx2_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp]  "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+	
+		rx2_Tail = tmp_rx_Tail;
+	
+	#ifdef USART2_EXTEND_RX_BUFFER
+		UCSR2B_REGISTER |= (1<<RXCIE2_BIT);
+	#endif
+	
+	#ifdef USART2_USE_SOFT_RTS
+		if (RTS2_PORT & (1<<RTS2_IONUM))
+			if (!(UCSR2A_REGISTER & (1<<RXC2_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)		
+				RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+	
+	#ifdef RX2_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart2_putc('\r');
+		#endif
+		
+		tmp = uart2_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r') 
+				uart2_putc('\n');
+		#endif
+	#endif // RX2_GETC_ECHO
+		
+		return tmp;
+	}
+#endif
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_gets(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			*buffer = uart2_getc();
+			if(*buffer++ == 0)
+				break;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_gets(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+			"rcall uart2_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"st Z+, r24 \n\t"
+			"cpse r24, __zero_reg__ \n\t"
+			"rjmp loop_%= \n\t"
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+	
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_getln(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart2_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart2_getc()) );
+			#endif
+				break;
+			}
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_getln(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+			
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart2_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq wait_loop2_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_RN
+		"wait_loop2_%=:"
+			"rcall uart2_getc \n\t"
+			"and r24, r24 \n\t"
+			"breq wait_loop2_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		do{
+			*buffer = uart2_getc();
+		}while(*buffer <= 32);
+		
+		buffer++;
+		bufferlimit--;
+		
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart2_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else //RX_NEWLINE_MODE_R
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart2_getc()) );
+			#endif
+				break;
+			}
+			else if(*buffer <= 32)
+				break; // string reading is done, we will exit
+
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart2_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+			
+		"skip_whitespaces_loop_%=:"
+			"rcall uart2_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"cpi r24, 0x21\n\t" // if(tmp <= 32)
+			"brcs skip_whitespaces_loop_%= \n\t" // skip all received whitespaces
+			"st Z+, r24 \n\t"
+			"dec %[limit] \n\t"
+		
+		"loop_%=:"	
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart2_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+		
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq exit_wait_loop_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"cpi r24, 0x21 \n\t" // if(tmp <= 32)
+			"brcs store_NULL_%= \n\t" // whitespace means end of this function, quit loop
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%=\n\t"
+			
+		#ifdef RX_NEWLINE_MODE_RN
+		"exit_wait_loop_%=:"
+			"rcall uart2_getc \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq exit_wait_loop_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	int16_t uart2_getint(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		uart2_getlnToFirstWhiteSpace(u_tmp_buff, 7);
+		
+		return atoi(u_tmp_buff);
+	}
+
+	int32_t uart2_getlong(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+	
+		uart2_getlnToFirstWhiteSpace(u_tmp_buff, 12);
+		
+		return atol(u_tmp_buff);
+	}
+
+	float uart2_getfloat(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[32];
+	#endif
+	
+		uart2_getlnToFirstWhiteSpace(u_tmp_buff, 32);
+		
+		return atof(u_tmp_buff);
+	}
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart2_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx2_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx2_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX2_BUFFER_MASK;
+		tmp = rx2_buffer[tmp_rx_Tail];
+		rx2_Tail = tmp_rx_Tail;
+		
+	#ifdef USART2_EXTEND_RX_BUFFER
+		UCSR2B_REGISTER |= (1<<RXCIE2_BIT);
+	#endif
+	
+	#ifdef USART2_USE_SOFT_RTS
+		if (RTS2_PORT & (1<<RTS2_IONUM))
+			if (!(UCSR2A_REGISTER & (1<<RXC2_BIT)))
+				RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+
+	int16_t uart2_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx2_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx2_Head)
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX2_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx2_buffer)) \n\t"
+			"sbci r27, hi8(-(rx2_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp] "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		rx2_Tail = tmp_rx_Tail;
+		
+	#ifdef USART2_EXTEND_RX_BUFFER
+		UCSR2B_REGISTER |= (1<<RXCIE2_BIT);
+	#endif
+	
+	#ifdef USART2_USE_SOFT_RTS
+		if (RTS2_PORT & (1<<RTS2_IONUM))
+			if (!(UCSR2A_REGISTER & (1<<RXC2_BIT)))
+				RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	uint8_t uart2_LoadData(uint8_t *data)
+	{
+		register uint8_t tmp_rx_Tail = rx2_Tail;
+		
+		if(tmp_rx_Tail == rx2_Head) return BUFFER_EMPTY; // result = 0
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX2_BUFFER_MASK;
+		*data = rx2_buffer[tmp_rx_Tail];
+		
+		rx2_Tail = tmp_rx_Tail;
+		
+	#ifdef USART2_EXTEND_RX_BUFFER
+		UCSR2B_REGISTER |= (1<<RXCIE2_BIT);
+	#endif
+	
+	#ifdef USART2_USE_SOFT_RTS
+		if (RTS2_PORT & (1<<RTS2_IONUM))
+			if (!(UCSR2A_REGISTER & (1<<RXC2_BIT)))
+				RTS2_PORT &= ~(1<<RTS2_IONUM);
+	#endif
+		
+		return COMPLETED; // result = 1
+	}
+
+	//uint8_t uart2_AvailableBytes(void)
+	//{
+	//	return (rx2_Head - rx2_Tail) & RX2_BUFFER_MASK;
+	//}
+	
+	uint8_t uart2_peek(void)
+	{
+		return rx2_buffer[(rx2_Tail+1) & RX2_BUFFER_MASK];
+	}
+#endif // NO_RX2_INTERRUPT
+
+#ifndef NO_RX3_INTERRUPT
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	char uart3_getc(void)
+	{
+		register uint8_t tmp_rx_Tail = rx3_Tail;
+		char tmp;
+		
+		if(tmp_rx_Tail == rx3_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX3_BUFFER_MASK;
+		tmp = rx3_buffer[tmp_rx_Tail];
+		
+		rx3_Tail = tmp_rx_Tail;
+		
+	#ifdef USART3_EXTEND_RX_BUFFER
+		UCSR3B_REGISTER |= (1<<RXCIE3_BIT);
+	#endif
+		
+	#ifdef USART3_USE_SOFT_RTS
+		if (RTS3_PORT & (1<<RTS3_IONUM))
+			if (!(UCSR3A_REGISTER & (1<<RXC3_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)
+				RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+		
+	#ifdef RX3_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart3_putc('\r');
+		#endif
+		
+		tmp = uart3_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r')
+				uart3_putc('\n');
+		#endif
+	#endif // RX3_GETC_ECHO
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	char uart3_getc(void)
+	{
+		register uint8_t tmp_rx_Tail asm("r25");
+		char tmp;
+		
+		tmp_rx_Tail = rx3_Tail;
+		
+		if(tmp_rx_Tail == rx3_Head) 
+			return 0;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX3_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx3_buffer)) \n\t"
+			"sbci r27, hi8(-(rx3_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp]  "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+	
+		rx3_Tail = tmp_rx_Tail;
+	
+	#ifdef USART3_EXTEND_RX_BUFFER
+		UCSR3B_REGISTER |= (1<<RXCIE3_BIT);
+	#endif
+	
+	#ifdef USART3_USE_SOFT_RTS
+		if (RTS3_PORT & (1<<RTS3_IONUM))
+			if (!(UCSR3A_REGISTER & (1<<RXC3_BIT))) // isr has fired so check if there is no unread data in UDR (if missed then next read will release RTS line)		
+				RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+	
+	#ifdef RX3_GETC_ECHO
+		#ifdef RX_NEWLINE_MODE_N
+			if(tmp == '\n')
+				uart3_putc('\r');
+		#endif
+		
+		tmp = uart3_putc_(tmp);
+		
+		#ifdef RX_NEWLINE_MODE_R
+			if(tmp == '\r') 
+				uart3_putc('\n');
+		#endif
+	#endif // RX3_GETC_ECHO
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_gets(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			*buffer = uart3_getc();
+			if(*buffer++ == 0)
+				break;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_gets(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+		
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+			"rcall uart3_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"st Z+, r24 \n\t"
+			"cpse r24, __zero_reg__ \n\t"
+			"rjmp loop_%= \n\t"
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_getln(char *buffer, uint8_t bufferlimit)
+	{
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart3_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart3_getc()) );
+			#endif
+				break;
+			}
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_getln(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+			
+		"loop_%=:"
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart3_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq wait_loop2_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_RN
+		"wait_loop2_%=:"
+			"rcall uart3_getc \n\t"
+			"and r24, r24 \n\t"
+			"breq wait_loop2_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		do{
+			*buffer = uart3_getc();
+		}while(*buffer <= 32);
+		
+		buffer++;
+		bufferlimit--;
+		
+		while(--bufferlimit)
+		{
+			do{
+				*buffer = uart3_getc();
+			}while(*buffer == 0);
+			
+		#ifdef RX_NEWLINE_MODE_N
+			if(*buffer == '\n')
+		#else //RX_NEWLINE_MODE_R
+			if(*buffer == '\r')
+		#endif
+			{
+			#ifdef RX_NEWLINE_MODE_RN
+				while( !(uart3_getc()) );
+			#endif
+				break;
+			}
+			else if(*buffer <= 32)
+				break; // string reading is done, we will exit
+
+			buffer++;
+		}
+		*buffer = 0;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	void uart3_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit)
+	{
+		asm volatile("\n\t"
+			
+		"skip_whitespaces_loop_%=:"
+			"rcall uart3_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"cpi r24, 0x21\n\t" // if(tmp <= 32)
+			"brcs skip_whitespaces_loop_%= \n\t" // skip all received whitespaces
+			"st Z+, r24 \n\t"
+			"dec %[limit] \n\t"
+		
+		"loop_%=:"	
+			"dec %[limit] \n\t"
+			"breq store_NULL_%= \n\t" // buffer limit hit, quit loop
+		"wait_loop_%=:"
+			"rcall uart3_getc \n\t" // counter and Z pointer will not be affected in uart_getc()
+			"and r24, r24 \n\t" // test for NULL
+			"breq wait_loop_%= \n\t"
+		
+		#ifdef RX_NEWLINE_MODE_N
+			"cpi r24, '\n' \n\t"
+		#else
+			"cpi r24, '\r' \n\t"
+		#endif
+		
+		#ifdef RX_NEWLINE_MODE_RN
+			"breq exit_wait_loop_%= \n\t"
+		#else
+			"breq store_NULL_%= \n\t"
+		#endif
+			
+			"cpi r24, 0x21 \n\t" // if(tmp <= 32)
+			"brcs store_NULL_%= \n\t" // whitespace means end of this function, quit loop
+			
+			"st Z+, r24 \n\t"
+			"rjmp loop_%=\n\t"
+			
+		#ifdef RX_NEWLINE_MODE_RN
+		"exit_wait_loop_%=:"
+			"rcall uart3_getc \n\t"
+			"and r24, r24 \n\t" // test for NULL
+			"breq exit_wait_loop_%= \n\t"
+		#endif
+		
+		"store_NULL_%=:"
+			"st Z, __zero_reg__ \n\t"
+		
+			: // outputs
+			: // inputs
+			"z" (buffer),
+			[limit] "r" (bufferlimit)
+			: // clobbers
+			"r24",
+			"r25","r26","r27" // uart_getc()
+		);
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	int16_t uart3_getint(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[7]; // heading, 5 digit bytes, NULL
+	#endif
+	
+		uart3_getlnToFirstWhiteSpace(u_tmp_buff, 7);
+		
+		return atoi(u_tmp_buff);
+	}
+
+	int32_t uart3_getlong(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[12]; // heading, 10 digit bytes, NULL
+	#endif
+	
+		uart3_getlnToFirstWhiteSpace(u_tmp_buff, 12);
+		
+		return atol(u_tmp_buff);
+	}
+
+	float uart3_getfloat(void)
+	{
+	#ifndef USART_NO_LOCAL_BUFFERS
+		char u_tmp_buff[32];
+	#endif
+	
+		uart3_getlnToFirstWhiteSpace(u_tmp_buff, 32);
+		
+		return atof(u_tmp_buff);
+	}
+
+#ifdef USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart3_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx3_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx3_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX3_BUFFER_MASK;
+		tmp = rx3_buffer[tmp_rx_Tail];
+		rx3_Tail = tmp_rx_Tail;
+		
+	#ifdef USART3_EXTEND_RX_BUFFER
+		UCSR3B_REGISTER |= (1<<RXCIE3_BIT);
+	#endif
+	
+	#ifdef USART3_USE_SOFT_RTS
+		if (RTS3_PORT & (1<<RTS3_IONUM))
+			if (!(UCSR3A_REGISTER & (1<<RXC3_BIT)))
+				RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#else // !USART_NO_ABI_BREAKING_PREMATURES
+	int16_t uart3_getData(void)
+	{
+		register uint8_t tmp_rx_Tail = rx3_Tail;
+		uint8_t tmp;
+		
+		if(tmp_rx_Tail == rx3_Head) 
+			return -1;
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX3_BUFFER_MASK;
+	
+		asm volatile("\n\t"
+			"mov r26, %[index] \n\t"
+			"ldi r27, 0x00 \n\t"
+			"subi r26, lo8(-(rx3_buffer)) \n\t"
+			"sbci r27, hi8(-(rx3_buffer)) \n\t"
+			"ld %[temp], X \n\t"
+			
+			: // outputs
+			[index] "+r" (tmp_rx_Tail),
+			[temp] "=r" (tmp)
+			: // inputs
+			: // clobbers
+			"r26","r27"
+		);
+		
+		rx3_Tail = tmp_rx_Tail;
+		
+	#ifdef USART3_EXTEND_RX_BUFFER
+		UCSR3B_REGISTER |= (1<<RXCIE3_BIT);
+	#endif
+	
+	#ifdef USART3_USE_SOFT_RTS
+		if (RTS3_PORT & (1<<RTS3_IONUM))
+			if (!(UCSR3A_REGISTER & (1<<RXC3_BIT)))
+				RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+		
+		return tmp;
+	}
+#endif // USART_NO_ABI_BREAKING_PREMATURES
+
+	uint8_t uart3_LoadData(uint8_t *data)
+	{
+		register uint8_t tmp_rx_Tail = rx3_Tail;
+		
+		if(tmp_rx_Tail == rx3_Head) return BUFFER_EMPTY; // result = 0
+		
+		tmp_rx_Tail = (tmp_rx_Tail+1) & RX3_BUFFER_MASK;
+		*data = rx3_buffer[tmp_rx_Tail];
+		
+		rx3_Tail = tmp_rx_Tail;
+		
+	#ifdef USART3_EXTEND_RX_BUFFER
+		UCSR3B_REGISTER |= (1<<RXCIE3_BIT);
+	#endif
+	
+	#ifdef USART3_USE_SOFT_RTS
+		if (RTS3_PORT & (1<<RTS3_IONUM))
+			if (!(UCSR3A_REGISTER & (1<<RXC3_BIT)))
+				RTS3_PORT &= ~(1<<RTS3_IONUM);
+	#endif
+		
+		return COMPLETED; // result = 1
+	}
+
+	//uint8_t uart3_AvailableBytes(void)
+	//{
+	//	return (rx3_Head - rx3_Tail) & RX3_BUFFER_MASK;
+	//}
+	
+	uint8_t uart3_peek(void)
+	{
+		return rx3_buffer[(rx3_Tail+1) & RX3_BUFFER_MASK];
+	}
+#endif // NO_RX3_INTERRUPT
+
+#endif // NO_USART_RX
+
+/************************************************************************************
+ *                           stdio.h stuff                                          *
+ ************************************************************************************/
+
+#if defined(USE_USART1)||defined(USE_USART2)||defined(USE_USART3)
+
+	#ifndef NO_USART_TX
+		
+		int uart_putchar(char data, FILE *stream)
+		{
+			switch((uint16_t) stream -> udata)
+			{
+				default:
+			#ifndef NO_TX0_INTERRUPT
+				case 0: 
+					if (data == '\n') 
+						uart0_putc('\r'); 
+					uart0_putc(data); break;
+			#endif
+			#ifndef NO_TX1_INTERRUPT
+				case 1: 
+					if (data == '\n')
+						uart1_putc('\r');
+					uart1_putc(data); break;
+			#endif
+			#ifndef NO_TX2_INTERRUPT
+				case 2: 
+					if (data == '\n')
+						uart2_putc('\r');
+					uart2_putc(data); break;
+			#endif
+			#ifndef NO_TX3_INTERRUPT
+				case 3: 
+					if (data == '\n')
+						uart3_putc('\r');
+					uart3_putc(data); break;
+			#endif
+			}
+			return 0;
+		}
+		
+	#endif // NO_USART_TX
+
+	#ifndef NO_USART_RX
+		
+		int uart_getchar(FILE *stream)
+		{
+			int16_t tmp;
+			
+			switch((uint16_t) stream -> udata)
+			{
+				default:
+			#ifndef NO_RX0_INTERRUPT
+				case 0: 
+					while ( (tmp = uart0_getData()) < 0 );
+						
+				#ifdef RX_STDIO_GETCHAR_ECHO
+					tmp = uart0_putc_((uint8_t)tmp);
+				#endif
+					break;
+			#endif
+			#ifndef NO_RX1_INTERRUPT
+				case 1: 
+					while ( (tmp = uart1_getData()) < 0 );
+						
+				#ifdef RX_STDIO_GETCHAR_ECHO
+					tmp = uart1_putc_((uint8_t)tmp);
+				#endif
+					break;
+			#endif
+			#ifndef NO_RX2_INTERRUPT
+				case 2: 
+					while ( (tmp = uart2_getData()) < 0 );
+						
+				#ifdef RX_STDIO_GETCHAR_ECHO
+					tmp = uart2_putc_((uint8_t)tmp);
+				#endif
+					break;
+			#endif
+			#ifndef NO_RX3_INTERRUPT
+				case 3: 
+					while ( (tmp = uart3_getData()) < 0 );
+						
+				#ifdef RX_STDIO_GETCHAR_ECHO
+					tmp = uart3_putc_((uint8_t)tmp);
+				#endif
+					break;
+			#endif
+			}
+			
+			return (uint8_t)tmp;
+		}
+		
+	#endif // NO_USART_RX
+
+	#ifdef USE_USART0
+	
+		#if defined(NO_RX0_INTERRUPT)
+			FILE uart0_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)0);
+	
+		#elif defined(NO_TX0_INTERRUPT)
+			FILE uart0_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)0);
+		#else
+			FILE uart0_io = FDEV_SETUP_STREAM_U(uart_putchar, uart_getchar, _FDEV_SETUP_RW, (void*)0);
+			FILE uart0_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)0);
+			FILE uart0_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)0);
+		#endif
+	
+	#endif // USE_USART0
+	
+	#ifdef USE_USART1
+	
+		#if defined(NO_RX1_INTERRUPT)
+			FILE uart1_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)1);
+	
+		#elif defined(NO_TX1_INTERRUPT)
+			FILE uart1_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)1);
+		#else
+			FILE uart1_io = FDEV_SETUP_STREAM_U(uart_putchar, uart_getchar, _FDEV_SETUP_RW, (void*)1);
+			FILE uart1_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)1);
+			FILE uart1_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)1);
+		#endif
+	
+	#endif // USE_USART1
+	
+	#ifdef USE_USART2
+	
+		#if defined(NO_RX2_INTERRUPT)
+			FILE uart2_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)2);
+	
+		#elif defined(NO_TX2_INTERRUPT)
+			FILE uart2_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)2);
+		#else
+			FILE uart2_io = FDEV_SETUP_STREAM_U(uart_putchar, uart_getchar, _FDEV_SETUP_RW, (void*)2);
+			FILE uart2_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)2);
+			FILE uart2_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)2);
+		#endif
+	
+	#endif // USE_USART2
+	
+	#ifdef USE_USART3
+	
+		#if defined(NO_RX3_INTERRUPT)
+			FILE uart3_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)3);
+	
+		#elif defined(NO_TX3_INTERRUPT)
+			FILE uart3_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)3);
+		#else
+			FILE uart3_io = FDEV_SETUP_STREAM_U(uart_putchar, uart_getchar, _FDEV_SETUP_RW, (void*)3);
+			FILE uart3_in = FDEV_SETUP_STREAM_U(NULL, uart_getchar, _FDEV_SETUP_READ, (void*)3);
+			FILE uart3_out = FDEV_SETUP_STREAM_U(uart_putchar, NULL, _FDEV_SETUP_WRITE, (void*)3);
+		#endif
+	
+	#endif // USE_USART3
+
+#else // single USART mcu
+
+	#ifndef NO_TX0_INTERRUPT
+		
+		int uart_putchar(char data, FILE *stream)
+		{
+			if (data == '\n') uart0_putc('\r');
+		
+			uart_putc(data);
+			return 0;
+		}
+	#endif // NO_TX0_INTERRUPT
+
+	#ifndef NO_RX0_INTERRUPT
+		
+		int uart_getchar(FILE *stream)
+		{
+			int16_t tmp;
+			
+			while ( (tmp = uart0_getData()) < 0 );
+		
+		#ifdef RX_STDIO_GETCHAR_ECHO
+			tmp = uart0_putc_((uint8_t)tmp);
+		#endif
+		
+			return (uint8_t)tmp;
+		}
+	#endif //NO_RX0_INTERRUPT
+	
+	#if defined(NO_RX0_INTERRUPT)
+		FILE uart0_out = FDEV_SETUP_STREAM(uart_putchar, NULL, _FDEV_SETUP_WRITE);
+		
+	#elif defined(NO_TX0_INTERRUPT)
+		FILE uart0_in = FDEV_SETUP_STREAM(NULL, uart_getchar, _FDEV_SETUP_READ);
+	#else
+		FILE uart0_io = FDEV_SETUP_STREAM(uart_putchar, uart_getchar, _FDEV_SETUP_RW);
+		FILE uart0_in = FDEV_SETUP_STREAM(NULL, uart_getchar, _FDEV_SETUP_READ);
+		FILE uart0_out = FDEV_SETUP_STREAM(uart_putchar, NULL, _FDEV_SETUP_WRITE);
+	#endif
+
+#endif // single/multi USART
+
+//******************************************************************
+//ISR prototypes
+//******************************************************************
+/*
+	ISR(TXn_INTERRUPT) // do it in a little weird way
+	{
+		register uint8_t tmp_tx_Tail = (txn_Tail + 1) & TXn_BUFFER_MASK;
+		
+		if(tmp_tx_Tail == txn_Head)
+			UCSRnB_REGISTER &= ~(1<<UDRIEn_BIT); // may be racing with putc insertions
+			
+		txn_Tail = tmp_tx_Tail; // it would create race condition if not used in isr
+		UDRn_REGISTER = txn_buffer[tmp_tx_Tail]; // transmit character from the buffer
+	}
+	
+	ISR(TXn_INTERRUPT) // non racing one // not used anymore
+	{
+		register uint8_t tmp_tx_Tail = txn_Tail;
+		
+		if(tmp_tx_Tail != txn_Head)
+		{
+			tmp_tx_Tail = (tmp_tx_Tail + 1) & TXn_BUFFER_MASK;
+			txn_Tail = tmp_tx_Tail; // it would create race condition if not used in isr
+			UDRn_REGISTER = txn_buffer[tmp_tx_Tail]; // transmit character from the buffer
+		}
+		else
+			UCSRnB_REGISTER &= ~(1<<UDRIEn_BIT);
+	}
+
+	ISR(RXn_INTERRUPT)
+	{
+		register uint8_t tmp_rx_Head = (rxn_Head + 1) & RXn_BUFFER_MASK;
+		register uint8_t tmp = UDRn_REGISTER;
+		
+	#if defined(USART0_MPCM_MODE)&&!defined(MPCM0_MASTER_ONLY)
+		if(UCSRnA & (1<<MPCMn))
+		{
+			if(tmp == MPCMn_ADDRESS || tmp == MPCMn_GCALL_ADDRESS)
+				UCSRnA &= ~(1<<MPCMn);
+			else
+				return;
+		}
+	#endif
+
+		if(rxn_Tail != tmp_rx_Head)
+		{
+			rxn_Head = tmp_rx_Head; // it would create race condition if not used in isr
+			rxn_buffer[tmp_rx_Head] = tmp;
+		}
+		
+	}
+*/
+
+#ifndef NO_TX0_INTERRUPT
+
+	ISR(UDRE0_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r30 \n\t"
+			"push r31 \n\t"
+		#else
+			#ifdef __AVR_HAVE_MOVW__
+				"movw %[z_save], r30 \n\t"
+			#else // in this case only 4 cycles are prematured out
+				"mov %A[z_save], r30 \n\t"
+				"mov %B[z_save], r31 \n\t"
+			#endif
+		#endif
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+				"in r31, %M[control_reg_IO] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+			"sei \n\t"
+		#endif
+		
+			TX0_EVERYCAL_EVENT
+		
+			"lds r30, (tx0_Tail) \n\t"
+			"lds r31, (tx0_Head) \n\t"
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cp r30, r31 \n\t"
+			"breq USART0_TX_EXIT \n\t"
+		#endif
+		
+			"inc r30 \n\t"
+	
+		#if (TX0_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_TX_INTERRUPT
+			"cpse r30, r31 \n\t"
+			"rjmp USART0_TX_CONTINUE \n\t"
+			
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+				"in r31, %M[control_reg_IO] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+		"USART0_TX_CONTINUE: "
+		#endif
+			
+			"sts (tx0_Tail), r30 \n\t"
+	
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__) // on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r31, 0x00 \n\t"
+		#endif
+			"subi r30, lo8(-(tx0_buffer)) \n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r31, hi8(-(tx0_buffer)) \n\t"
+		#endif
+			"ld r30, Z \n\t"
+		
+		#ifdef USART0_IN_IO_ADDRESS_SPACE
+			"out %M[UDR_reg_IO], r30 \n\t"
+		#else
+			"sts %M[UDR_reg], r30 \n\t"
+		#endif
+			
+			TX0_TRANSMIT_EVENT
+			
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cli \n\t"
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"sbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)	
+				"in r31, %M[control_reg_IO] \n\t"
+				"ori r31, (1<<%M[udrie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"ori r31, (1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		#endif
+			
+		"USART0_TX_EXIT: "
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			#ifdef __AVR_HAVE_MOVW__
+				"movw r30, %[z_save] \n\t"
+			#else
+				"mov r31, %B[z_save] \n\t"
+				"mov r30, %A[z_save] \n\t"
+			#endif
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+		
+			"reti \n\t"
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			TX0_INPUT_OPERAND_LIST
+			[UDR_reg_IO]     "M" (_SFR_IO_ADDR(UDR0_REGISTER)),
+			[UDR_reg]        "n" (_SFR_MEM_ADDR(UDR0_REGISTER)),
+			[control_reg_IO] "M" (_SFR_IO_ADDR(UCSR0B_REGISTER)),
+			[control_reg]    "n" (_SFR_MEM_ADDR(UCSR0B_REGISTER)),
+			[udrie_bit]      "M" (UDRIE0_BIT),
+			[mask]           "M" (TX0_BUFFER_MASK)
+		
+			// no clobbers
+		);
+	}	
+	
+#if defined(USART0_USE_TXC_INTERRUPT)
+	
+#ifdef USATR0_NO_NAKED_TXC_INTERRUPT
+	ISR(TXC0_INTERRUPT)
+#else
+	ISR(TXC0_INTERRUPT, ISR_NAKED) // ISR is compiled to only one cbi instruction - no need for large prologue/epilogue
+#endif	
+	{
+	#ifdef USART0_RS485_MODE
+		RS485_CONTROL0_PORT &= ~(1<<RS485_CONTROL0_IONUM); // set low after completed transaction
+	#endif
+	
+		TXC0_interrupt_event();
+	
+	#ifndef USATR0_NO_NAKED_TXC_INTERRUPT
+		reti();
+	#endif
+	}
+	
+#endif
+	
+#endif // NO_TX0_INTERRUPT
+
+#ifndef NO_RX0_INTERRUPT
+
+	ISR(RX0_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+		
+			"push r25 \n\t"
+			
+		#ifdef USART0_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				#ifdef __AVR_HAVE_MOVW__
+					"movw %[z_save], r30 \n\t"
+				#else // in this case only 4 cycles are prematured out
+					"mov %A[z_save], r30\n\t"
+					"mov %B[z_save], r31\n\t"
+				#endif
+			#endif
+		#endif
+			
+		#ifndef USART0_EXTEND_RX_BUFFER
+			RX0_FRAMING_EVENT
+			
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"in r25, %M[UDR_reg_IO] \n\t"
+			#else
+				"lds r25, %M[UDR_reg] \n\t"
+			#endif
+		#endif
+			
+		#ifndef USART0_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				#ifdef __AVR_HAVE_MOVW__
+					"movw %[z_save], r30 \n\t"
+				#else // in this case only 4 cycles are prematured out
+					"mov %A[z_save], r30\n\t"
+					"mov %B[z_save], r31\n\t"
+				#endif
+			#endif
+		#endif
+		
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+				"in r31, %M[control_reg_IO] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+			"sei \n\t"
+		#endif
+	
+			RX0_EVERYCALL_EVENT
+	
+			"lds r30, (rx0_Head) \n\t"
+			"lds r31, (rx0_Tail) \n\t"
+		
+			"inc r30 \n\t"
+		
+		#if (RX0_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+			"cp r31, r30 \n\t"
+		#if defined(USART0_USE_SOFT_RTS)||(defined(USART0_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+			"breq USART0_DISABLE_RXCIE \n\t"
+		#elif defined(USART0_EXTEND_RX_BUFFER)&&defined(USART_UNSAFE_RX_INTERRUPT)
+			"breq USART0_RX_EXIT_SKIP \n\t"
+		#else
+			"breq USART0_RX_EXIT \n\t"
+		#endif
+		
+		#ifdef USART0_EXTEND_RX_BUFFER
+			RX0_FRAMING_EVENT
+			
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"in r25, %M[UDR_reg_IO] \n\t"
+			#else
+				"lds r25, %M[UDR_reg] \n\t"
+			#endif
+		#endif
+		
+		RX0_EARLY_RECEIVE_EVENT
+		
+		#if defined(USART0_MPCM_MODE)&&!defined(MPCM0_MASTER_ONLY)
+
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"in r31, %M[UCSRA_reg_IO] \n\t"
+			#else
+				"lds r31, %M[UCSRA_reg] \n\t"
+			#endif
+
+				"sbrs r31, %M[mpcm_bit] \n\t"
+				"rjmp USART0_RX_CONTINUE \n\t"
+				"cpi r25, %M[mpcm_address] \n\t"
+			#ifdef MPCM0_GCALL_ADDRESS
+				"breq p_%= \n\t"
+				"cpi r25, %M[mpcm_gcall_address] \n\t"
+			#endif
+				"brne USART0_RX_EXIT \n\t"
+			"p_%=: "
+				"andi r31, ~(1<<%M[mpcm_bit]) \n\t"
+
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"out %M[UCSRA_reg_IO], r31 \n\t"
+			#else
+				"sts %M[UCSRA_reg], r31 \n\t"
+			#endif
+
+		"USART0_RX_CONTINUE: "
+		#endif
+			
+			"sts (rx0_Head), r30 \n\t"
+		
+		#if !defined(__AVR_ATtiny2313__)&&!defined(__AVR_ATtiny2313A__)	// on ATtiny2313 upper byte in pointer pair is ignored
+			"ldi r31, 0x00 \n\t"
+		#endif
+			"subi r30, lo8(-(rx0_buffer))\n\t"
+		
+		#ifndef USART_USE_TINY_MEMORY_MODEL
+			"sbci r31, hi8(-(rx0_buffer))\n\t"
+		#endif	
+			"st Z, r25 \n\t"
+		
+			RX0_LATE_RECEIVE_EVENT
+			
+		"USART0_RX_EXIT: "
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"cli \n\t"
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"sbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+				"in r31, %M[control_reg_IO] \n\t"
+				"ori r31, (1<<%M[rxcie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"ori r31, (1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+		"USART0_RX_EXIT_SKIP: "
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			#ifdef __AVR_HAVE_MOVW__
+				"movw r30, %[z_save] \n\t"
+			#else
+				"mov r31, %B[z_save] \n\t"
+				"mov r30, %A[z_save] \n\t"
+			#endif
+		#endif
+		
+			"pop r25 \n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+		
+		#if defined(USART0_USE_SOFT_RTS)||(defined(USART0_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+		"USART0_DISABLE_RXCIE: "
+		
+		#ifdef USART0_USE_SOFT_RTS
+			"sbi %M[rts_port], %M[rts_pin] \n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_RX_INTERRUPT
+			#ifdef USART0_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
+				"in r31, %M[control_reg_IO] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"out %M[control_reg_IO], r31\n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		#endif
+			
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"rjmp USART0_RX_EXIT_SKIP \n\t"
+		#else
+			"rjmp USART0_RX_EXIT \n\t"
+		#endif
+		#endif
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			RX0_INPUT_OPERAND_LIST
+			[UDR_reg_IO]         "M" (_SFR_IO_ADDR(UDR0_REGISTER)),
+			[UDR_reg]            "n" (_SFR_MEM_ADDR(UDR0_REGISTER)),
+			[mask]               "M" (RX0_BUFFER_MASK),
+			[mpcm_address]       "M" (MPCM0_ADDRESS),
+		#ifdef MPCM0_GCALL_ADDRESS
+			[mpcm_gcall_address] "M" (MPCM0_GCALL_ADDRESS),
+		#endif
+			[mpcm_bit]           "M" (MPCM0_BIT),
+		#ifdef USART0_USE_SOFT_RTS
+			[rts_port]           "M" (_SFR_IO_ADDR(RTS0_PORT)),
+			[rts_pin]            "M" (RTS0_IONUM),
+		#endif
+			[UCSRA_reg]          "n" (_SFR_MEM_ADDR(UCSR0A_REGISTER)),
+			[UCSRA_reg_IO]       "M" (_SFR_IO_ADDR(UCSR0A_REGISTER)),
+			[control_reg_IO]     "M" (_SFR_IO_ADDR(UCSR0B_REGISTER)),
+			[control_reg]        "n" (_SFR_MEM_ADDR(UCSR0B_REGISTER)),
+			[rxcie_bit]          "M" (RXCIE0_BIT)
+		
+			// no clobbers
+		);
+		
+	}
+
+#endif // NO_RX0_INTERRUPT
+
+#ifndef NO_TX1_INTERRUPT
+
+	ISR(UDRE1_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r30 \n\t"
+			"push r31 \n\t"
+		#else
+			"movw %[z_save], r30 \n\t"
+		#endif
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		
+			"sei \n\t"
+		#endif
+			
+			TX1_EVERYCAL_EVENT
+			
+			"lds r30, (tx1_Tail) \n\t"
+			"lds r31, (tx1_Head) \n\t"
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cp r30, r31 \n\t"
+			"breq USART1_TX_EXIT \n\t"
+		#endif
+		
+			"inc r30 \n\t"
+		
+		#if (TX1_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_TX_INTERRUPT
+			"cpse r30, r31 \n\t"
+			"rjmp USART1_TX_CONTINUE \n\t"
+			
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+		"USART1_TX_CONTINUE: "
+		#endif
+		
+			"sts (tx1_Tail), r30 \n\t"
+		
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(tx1_buffer)) \n\t"
+			"sbci r31, hi8(-(tx1_buffer)) \n\t"
+			
+			"ld r30, Z \n\t"
+		
+		#ifdef USART1_IN_IO_ADDRESS_SPACE
+			"out %M[UDR_reg_IO], r30 \n\t"
+		#else
+			"sts %M[UDR_reg], r30 \n\t"
+		#endif
+		
+			TX1_TRANSMIT_EVENT
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cli \n\t"
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"sbi %M[control_reg_IO], %M[udrie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"ori r31, (1<<%M[udrie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		#endif
+		
+		"USART1_TX_EXIT: "
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			TX1_INPUT_OPERAND_LIST
+			[UDR_reg_IO]     "M" (_SFR_IO_ADDR(UDR1_REGISTER)),
+			[UDR_reg]        "n" (_SFR_MEM_ADDR(UDR1_REGISTER)),
+			[control_reg_IO] "M" (_SFR_IO_ADDR(UCSR1B_REGISTER)),
+			[control_reg]    "n" (_SFR_MEM_ADDR(UCSR1B_REGISTER)),
+			[udrie_bit]      "M" (UDRIE1_BIT),
+			[mask]           "M" (TX1_BUFFER_MASK)
+		
+			// no clobbers
+		);
+		
+	}
+
+#if defined(USART1_USE_TXC_INTERRUPT)
+
+#ifdef USATR1_NO_NAKED_TXC_INTERRUPT
+	ISR(TXC1_INTERRUPT)
+#else
+	ISR(TXC1_INTERRUPT, ISR_NAKED) // ISR is compiled to only one cbi instruction - no need for large prologue/epilogue
+#endif
+	{
+	#ifdef USART1_RS485_MODE
+		RS485_CONTROL1_PORT &= ~(1<<RS485_CONTROL1_IONUM); // set low after completed transaction
+	#endif
+	
+		TXC1_interrupt_event();
+	
+	#ifndef USATR1_NO_NAKED_TXC_INTERRUPT
+		reti();
+	#endif
+	}
+
+#endif // USART1_RS485_MODE
+
+#endif // NO_TX1_INTERRUPT
+
+#ifndef NO_RX1_INTERRUPT
+	
+	ISR(RX1_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+	
+			"push r25 \n\t"
+		
+		#ifdef USART1_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif
+		
+		#ifndef USART1_EXTEND_RX_BUFFER
+			RX1_FRAMING_EVENT
+		
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"in r25, %M[UDR_reg_IO] \n\t"
+			#else
+				"lds r25, %M[UDR_reg] \n\t"
+			#endif
+		#endif
+			
+		#ifndef USART1_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif
+		
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		
+			"sei \n\t"
+		#endif
+			
+			RX1_EVERYCALL_EVENT
+			
+			"lds r30, (rx1_Head) \n\t"
+			"lds r31, (rx1_Tail) \n\t"
+		
+			"inc r30 \n\t"
+		
+		#if (RX1_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+			"cp r31, r30 \n\t"
+		#if defined(USART1_USE_SOFT_RTS)||(defined(USART1_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+			"breq USART1_DISABLE_RXCIE \n\t"           
+		#elif defined(USART1_EXTEND_RX_BUFFER)&&defined(USART_UNSAFE_RX_INTERRUPT)
+			"breq USART1_RX_EXIT_SKIP \n\t"          
+		#else
+			"breq USART1_RX_EXIT \n\t"           
+		#endif
+			
+		#ifdef USART1_EXTEND_RX_BUFFER
+			RX1_FRAMING_EVENT
+			
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"in r25, %M[UDR_reg_IO] \n\t"
+			#else
+				"lds r25, %M[UDR_reg] \n\t"
+			#endif
+		#endif
+			
+		RX1_EARLY_RECEIVE_EVENT
+			
+		#if defined(USART1_MPCM_MODE)&&!defined(MPCM1_MASTER_ONLY)
+		
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"in r31, %M[UCSRA_reg_IO] \n\t"
+			#else
+				"lds r31, %M[UCSRA_reg] \n\t"
+			#endif
+		
+				"sbrs r31, %M[mpcm_bit] \n\t"
+				"rjmp USART1_RX_CONTINUE \n\t"
+				"cpi r25, %M[mpcm_address] \n\t"
+			#ifdef MPCM1_GCALL_ADDRESS
+				"breq p_%= \n\t"
+				"cpi r25, %M[mpcm_gcall_address] \n\t"
+			#endif
+				"brne USART1_RX_EXIT \n\t"
+			"p_%=: "
+				"andi r31, ~(1<<%M[mpcm_bit]) \n\t"
+		
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"out %M[UCSRA_reg_IO], r31 \n\t"
+			#else
+				"sts %M[UCSRA_reg], r31 \n\t"
+			#endif
+		
+		"USART1_RX_CONTINUE: "
+		#endif
+			
+			"sts (rx1_Head), r30 \n\t"
+		
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(rx1_buffer))\n\t"
+			"sbci r31, hi8(-(rx1_buffer))\n\t"
+			"st Z, r25 \n\t"
+		
+			RX1_LATE_RECEIVE_EVENT
+		
+		"USART1_RX_EXIT: "
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"cli \n\t"
+			
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"sbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"ori r31, (1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+			
+		"USART1_RX_EXIT_SKIP: "
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+		
+			"pop r25 \n\t"
+
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+		
+		#if defined(USART1_USE_SOFT_RTS)||(defined(USART1_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+		"USART1_DISABLE_RXCIE: "
+		
+		#ifdef USART1_USE_SOFT_RTS
+			"sbi %M[rts_port], %M[rts_pin] \n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_RX_INTERRUPT
+			#ifdef USART1_IN_IO_ADDRESS_SPACE
+				"cbi %M[control_reg_IO], %M[rxcie_bit] \n\t"
+			#else
+				"lds r31, %M[control_reg] \n\t"
+				"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+				"sts %M[control_reg], r31 \n\t"
+			#endif
+		#endif
+			
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"rjmp USART1_RX_EXIT_SKIP \n\t"
+		#else
+			"rjmp USART1_RX_EXIT \n\t"
+		#endif
+		#endif
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			RX1_INPUT_OPERAND_LIST
+			[UDR_reg_IO]         "M" (_SFR_IO_ADDR(UDR1_REGISTER)),
+			[UDR_reg]            "n" (_SFR_MEM_ADDR(UDR1_REGISTER)),
+			[mask]               "M" (RX1_BUFFER_MASK),
+			[mpcm_address]       "M" (MPCM1_ADDRESS),
+		#ifdef MPCM1_GCALL_ADDRESS
+			[mpcm_gcall_address] "M" (MPCM1_GCALL_ADDRESS),
+		#endif
+			[mpcm_bit]           "M" (MPCM1_BIT),
+		#ifdef USART1_USE_SOFT_RTS
+			[rts_port]           "M" (_SFR_IO_ADDR(RTS1_PORT)),
+			[rts_pin]            "M" (RTS1_IONUM),
+		#endif
+			[UCSRA_reg]          "n" (_SFR_MEM_ADDR(UCSR1A_REGISTER)),
+			[UCSRA_reg_IO]       "M" (_SFR_IO_ADDR(UCSR1A_REGISTER)),
+			[control_reg_IO]     "M" (_SFR_IO_ADDR(UCSR1B_REGISTER)),
+			[control_reg]        "n" (_SFR_MEM_ADDR(UCSR1B_REGISTER)),
+			[rxcie_bit]          "M" (RXCIE1_BIT)
+		
+			// no clobbers
+		);
+		
+	}
+
+#endif // NO_RX1_INTERRUPT
+
+#ifndef NO_TX2_INTERRUPT
+
+	ISR(UDRE2_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r30 \n\t"
+			"push r31 \n\t"
+		#else
+			"movw %[z_save], r30 \n\t"
+		#endif
+	
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		
+			"sei \n\t"
+		#endif
+		
+			TX2_EVERYCAL_EVENT
+		
+			"lds r30, (tx2_Tail) \n\t"
+			"lds r31, (tx2_Head) \n\t"
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cp r30, r31 \n\t"
+			"breq USART2_TX_EXIT \n\t"
+		#endif
+		
+			"inc r30 \n\t"
+		
+		#if (TX2_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_TX_INTERRUPT
+			"cpse r30, r31 \n\t"
+			"rjmp USART2_TX_CONTINUE \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+			
+		"USART2_TX_CONTINUE: "
+		#endif
+			
+			"sts (tx2_Tail), r30 \n\t"
+			
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(tx2_buffer)) \n\t"
+			"sbci r31, hi8(-(tx2_buffer)) \n\t"
+			
+			"ld r30, Z \n\t"
+			
+			"sts %M[UDR_reg], r30 \n\t"
+
+			TX2_TRANSMIT_EVENT
+
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cli \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"ori r31, (1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		#endif
+
+		"USART2_TX_EXIT: "
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			TX2_INPUT_OPERAND_LIST
+			[UDR_reg]     "n" (_SFR_MEM_ADDR(UDR2_REGISTER)),
+			[control_reg] "n" (_SFR_MEM_ADDR(UCSR2B_REGISTER)),
+			[udrie_bit]   "M" (UDRIE2_BIT),
+			[mask]        "M" (TX2_BUFFER_MASK)
+		
+			// no clobbers
+		);
+		
+	}
+
+#if defined(USART2_USE_TXC_INTERRUPT)
+
+#ifdef USATR2_NO_NAKED_TXC_INTERRUPT
+	ISR(TXC2_INTERRUPT)
+#else
+	ISR(TXC2_INTERRUPT, ISR_NAKED) // ISR is compiled to only one cbi instruction - no need for large prologue/epilogue
+#endif
+	{
+	#ifdef USART2_RS485_MODE
+		RS485_CONTROL2_PORT &= ~(1<<RS485_CONTROL2_IONUM); // set low after completed transaction
+	#endif
+	
+		TXC2_interrupt_event();
+	
+	#ifndef USATR2_NO_NAKED_TXC_INTERRUPT
+		reti();
+	#endif
+	}
+
+#endif // USART2_RS485_MODE
+
+#endif // NO_TX2_INTERRUPT
+
+#ifndef NO_RX2_INTERRUPT
+
+	ISR(RX2_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+
+			"push r25 \n\t"
+			
+		#ifdef USART2_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif	
+			
+		#ifndef USART2_EXTEND_RX_BUFFER
+			RX2_FRAMING_EVENT
+			"lds r25, %M[UDR_reg] \n\t"
+		#endif
+			
+		#ifndef USART2_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif
+		
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+			
+			"sei \n\t"
+		#endif
+		
+			RX2_EVERYCALL_EVENT
+		
+			"lds r30, (rx2_Head) \n\t"
+			"lds r31, (rx2_Tail) \n\t"
+		
+			"inc r30 \n\t"
+		
+		#if (RX2_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+			"cp r31, r30 \n\t"
+		#if defined(USART2_USE_SOFT_RTS)||(defined(USART2_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+			"breq USART2_DISABLE_RXCIE \n\t"           
+		#elif defined(USART2_EXTEND_RX_BUFFER)&&defined(USART_UNSAFE_RX_INTERRUPT)
+			"breq USART2_RX_EXIT_SKIP \n\t"          
+		#else
+			"breq USART2_RX_EXIT \n\t"           
+		#endif
+		
+		#ifdef USART2_EXTEND_RX_BUFFER
+			RX2_FRAMING_EVENT
+			"lds r25, %M[UDR_reg] \n\t"
+		#endif
+		
+			RX2_EARLY_RECEIVE_EVENT
+		
+		#if defined(USART2_MPCM_MODE)&&!defined(MPCM2_MASTER_ONLY)
+			"lds r31, %M[UCSRA_reg] \n\t"
+		
+			"sbrs r31, %M[mpcm_bit] \n\t"
+			"rjmp USART2_RX_CONTINUE \n\t"
+			"cpi r25, %M[mpcm_address] \n\t"
+		#ifdef MPCM2_GCALL_ADDRESS
+			"breq p_%= \n\t"
+			"cpi r25, %M[mpcm_gcall_address] \n\t"
+		#endif
+			"brne USART2_RX_EXIT \n\t"
+		"p_%=: "
+			"andi r31, ~(1<<%M[mpcm_bit]) \n\t"
+		
+			"sts %M[UCSRA_reg], r31 \n\t"
+		
+		"USART2_RX_CONTINUE: "
+		#endif
+			
+			"sts (rx2_Head), r30 \n\t"
+		
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(rx2_buffer))\n\t"
+			"sbci r31, hi8(-(rx2_buffer))\n\t"
+			"st Z, r25 \n\t"
+		
+			RX2_LATE_RECEIVE_EVENT
+		
+		"USART2_RX_EXIT: "
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"cli \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"ori r31, (1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		
+		"USART2_RX_EXIT_SKIP: "
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+			
+			"pop r25 \n\t"
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+		
+		#if defined(USART2_USE_SOFT_RTS)||(defined(USART2_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+		"USART2_DISABLE_RXCIE: "
+		
+		#ifdef USART3_USE_SOFT_RTS
+			"sbi %M[rts_port], %M[rts_pin] \n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_RX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		#endif
+			
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"rjmp USART2_RX_EXIT_SKIP \n\t"
+		#else
+			"rjmp USART2_RX_EXIT \n\t"
+		#endif
+		#endif
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			RX2_INPUT_OPERAND_LIST
+			[UDR_reg]            "n" (_SFR_MEM_ADDR(UDR2_REGISTER)),
+			[mask]               "M" (RX2_BUFFER_MASK),
+			[mpcm_address]       "M" (MPCM2_ADDRESS),
+		#ifdef MPCM2_GCALL_ADDRESS
+			[mpcm_gcall_address] "M" (MPCM2_GCALL_ADDRESS),
+		#endif
+			[mpcm_bit]           "M" (MPCM2_BIT),
+		#ifdef USART2_USE_SOFT_RTS
+			[rts_port]           "M" (_SFR_IO_ADDR(RTS2_PORT)),
+			[rts_pin]            "M" (RTS2_IONUM),
+		#endif
+			[UCSRA_reg]          "n" (_SFR_MEM_ADDR(UCSR2A_REGISTER)),
+			[control_reg]        "n" (_SFR_MEM_ADDR(UCSR2B_REGISTER)),
+			[rxcie_bit]          "M" (RXCIE2_BIT)
+		
+			// no clobbers
+		);
+		
+	}
+	
+#endif // NO_RX2_INTERRUPT
+
+#ifndef NO_TX3_INTERRUPT
+
+	ISR(UDRE3_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r30 \n\t"
+			"push r31 \n\t"
+		#else
+			"movw %[z_save], r30 \n\t"
+		#endif
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		
+			"sei \n\t"
+		#endif
+			
+			TX3_EVERYCAL_EVENT
+			
+			"lds r30, (tx3_Tail) \n\t"
+			"lds r31, (tx3_Head) \n\t"
+		
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cp r30, r31 \n\t"
+			"breq USART3_TX_EXIT \n\t"
+		#endif
+		
+			"inc r30 \n\t"
+		
+		#if (TX3_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_TX_INTERRUPT
+			"cpse r30, r31 \n\t"
+			"rjmp USART3_TX_CONTINUE \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		
+		"USART3_TX_CONTINUE: "
+		#endif
+		
+			"sts (tx3_Tail), r30 \n\t"
+		
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(tx3_buffer)) \n\t"
+			"sbci r31, hi8(-(tx3_buffer)) \n\t"
+			
+			"ld r30, Z \n\t"
+		
+			"sts %M[UDR_reg], r30 \n\t"
+			
+			TX3_TRANSMIT_EVENT
+			
+		#ifdef USART_UNSAFE_TX_INTERRUPT
+			"cli \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"ori r31, (1<<%M[udrie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		#endif
+			
+		"USART3_TX_EXIT: "
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			TX3_INPUT_OPERAND_LIST
+			[UDR_reg]     "n" (_SFR_MEM_ADDR(UDR3_REGISTER)),
+			[control_reg] "n" (_SFR_MEM_ADDR(UCSR3B_REGISTER)),
+			[udrie_bit]   "M" (UDRIE3_BIT),
+			[mask]        "M" (TX3_BUFFER_MASK)
+		
+			// no clobbers
+		);
+		
+	}
+	
+#if defined(USART3_USE_TXC_INTERRUPT)
+
+#ifdef USATR3_NO_NAKED_TXC_INTERRUPT
+	ISR(TXC3_INTERRUPT)
+#else
+	ISR(TXC3_INTERRUPT, ISR_NAKED) // ISR is compiled to only one cbi instruction - no need for large prologue/epilogue
+#endif
+	{
+	#ifdef USART3_RS485_MODE
+		RS485_CONTROL3_PORT &= ~(1<<RS485_CONTROL3_IONUM); // set low after completed transaction
+	#endif
+	
+		TXC3_interrupt_event();
+	
+	#ifndef USATR3_NO_NAKED_TXC_INTERRUPT
+		reti();
+	#endif
+	}
+
+#endif // USART0_RS485_MODE	
+	
+#endif // NO_TX3_INTERRUPT
+
+#ifndef NO_RX3_INTERRUPT
+
+	ISR(RX3_INTERRUPT, ISR_NAKED)
+	{
+		asm volatile("\n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"push r16 \n\t"
+			"in r16, __SREG__ \n\t"
+		#else
+			"in %[sreg_save], __SREG__ \n\t"
+		#endif
+	
+			"push r25 \n\t"
+		
+		#ifdef USART3_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif
+				
+		#ifndef USART3_EXTEND_RX_BUFFER
+			RX3_FRAMING_EVENT
+			"lds r25, %M[UDR_reg] \n\t"
+		#endif
+			
+		#ifndef USART3_PUSH_BEFORE_RX
+			#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+				"push r30 \n\t"
+				"push r31 \n\t"
+			#else
+				"movw %[z_save], r30 \n\t"
+			#endif
+		#endif
+		
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		
+			"sei \n\t"
+		#endif
+		
+			RX3_EVERYCALL_EVENT
+		
+			"lds r30, (rx3_Head) \n\t"
+			"lds r31, (rx3_Tail) \n\t"
+		
+			"inc r30 \n\t"
+		
+		#if (RX3_BUFFER_MASK != 0xff)
+			"andi r30, %M[mask]\n\t"
+		#endif
+		
+			"cp r31, r30 \n\t"
+		#if defined(USART3_USE_SOFT_RTS)||(defined(USART3_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+			"breq USART3_DISABLE_RXCIE \n\t"
+		#elif defined(USART3_EXTEND_RX_BUFFER)&&defined(USART_UNSAFE_RX_INTERRUPT)
+			"breq USART3_RX_EXIT_SKIP \n\t"
+		#else
+			"breq USART3_RX_EXIT \n\t"
+		#endif
+		
+		#ifdef USART3_EXTEND_RX_BUFFER
+			RX3_FRAMING_EVENT
+			"lds r25, %M[UDR_reg] \n\t"
+		#endif
+			
+			RX3_EARLY_RECEIVE_EVENT
+			
+		#if defined(USART3_MPCM_MODE)&&!defined(MPCM3_MASTER_ONLY)
+			"lds r31, %M[UCSRA_reg] \n\t"
+
+			"sbrs r31, %M[mpcm_bit] \n\t"
+			"rjmp USART3_RX_CONTINUE \n\t"
+			"cpi r25, %M[mpcm_address] \n\t"
+		#ifdef MPCM3_GCALL_ADDRESS
+			"breq p_%= \n\t"
+			"cpi r25, %M[mpcm_gcall_address] \n\t"
+		#endif
+			"brne USART3_RX_EXIT \n\t"
+		"p_%=: "
+			"andi r31, ~(1<<%M[mpcm_bit]) \n\t"
+
+			"sts %M[UCSRA_reg], r31 \n\t"
+
+		"USART3_RX_CONTINUE: "
+		#endif	
+			
+			"sts (rx3_Head), r30 \n\t"
+			
+			"ldi r31, 0x00 \n\t"
+			"subi r30, lo8(-(rx3_buffer))\n\t"
+			"sbci r31, hi8(-(rx3_buffer))\n\t"
+			"st Z, r25 \n\t"
+		
+			RX3_LATE_RECEIVE_EVENT
+		
+		"USART3_RX_EXIT: "
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"cli \n\t"
+			
+			"lds r31, %M[control_reg] \n\t"
+			"ori r31, (1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+			
+		"USART3_RX_EXIT_SKIP: "
+		#endif
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r31 \n\t"
+			"pop r30 \n\t"
+		#else
+			"movw r30, %[z_save] \n\t"
+		#endif
+		
+			"pop r25 \n\t"
+	
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#else
+			"out __SREG__, %[sreg_save] \n\t"
+		#endif
+
+			"reti \n\t"
+		
+		#if defined(USART3_USE_SOFT_RTS)||(defined(USART3_EXTEND_RX_BUFFER)&&!defined(USART_UNSAFE_RX_INTERRUPT))
+		"USART3_DISABLE_RXCIE: "
+		
+		#ifdef USART3_USE_SOFT_RTS
+			"sbi %M[rts_port], %M[rts_pin] \n\t"
+		#endif
+		
+		#ifndef USART_UNSAFE_RX_INTERRUPT
+			"lds r31, %M[control_reg] \n\t"
+			"andi r31, ~(1<<%M[rxcie_bit]) \n\t"
+			"sts %M[control_reg], r31 \n\t"
+		#endif
+			
+		#ifdef USART_UNSAFE_RX_INTERRUPT
+			"rjmp USART3_RX_EXIT_SKIP \n\t"
+		#else
+			"rjmp USART3_RX_EXIT \n\t"
+		#endif
+		#endif
+			: // output operands
+			USART_REG_SAVE_LIST
+			
+			: // input operands
+			RX3_INPUT_OPERAND_LIST
+			[UDR_reg]            "n" (_SFR_MEM_ADDR(UDR3_REGISTER)),
+			[mask]               "M" (RX3_BUFFER_MASK),
+			[mpcm_address]       "M" (MPCM3_ADDRESS),
+		#ifdef MPCM3_GCALL_ADDRESS
+			[mpcm_gcall_address] "M" (MPCM3_GCALL_ADDRESS),
+		#endif
+			[mpcm_bit]           "M" (MPCM3_BIT),
+		#ifdef USART3_USE_SOFT_RTS
+			[rts_port]           "M" (_SFR_IO_ADDR(RTS3_PORT)),
+			[rts_pin]            "M" (RTS3_IONUM),
+		#endif
+			[UCSRA_reg]          "n" (_SFR_MEM_ADDR(UCSR3A_REGISTER)),
+			[control_reg]        "n" (_SFR_MEM_ADDR(UCSR3B_REGISTER)),
+			[rxcie_bit]          "M" (RXCIE3_BIT)
+		
+			// no clobbers
+		);
+		
+	}
+
+#endif // NO_RX3_INTERRUPT
\ No newline at end of file
diff --git a/vendor/jnk0le-AVR-UART-lib/usart.h b/vendor/jnk0le-AVR-UART-lib/usart.h
new file mode 100644
index 0000000..9f574a2
--- /dev/null
+++ b/vendor/jnk0le-AVR-UART-lib/usart.h
@@ -0,0 +1,2546 @@
+/*!
+ * \brief
+ *
+ * \author Jan Oleksiewicz <jnk0le@hotmail.com>
+ * \license SPDX-License-Identifier: MIT
+ */
+
+#ifndef _USART_H_
+#define _USART_H_
+
+#include <avr/io.h> // for inline func
+#include "usart_config.h"
+
+#ifndef F_CPU
+	#warning F_CPU is undefined, USART may not work correctly without this
+#endif
+
+#define BAUD_CALC(x) ((F_CPU+(x)*8UL) / (16UL*(x))-1UL) // macro calculating precise UBRR value
+#define BAUD_CALC_FAST(x) ((F_CPU)/((x)*16UL)-1) // for faster real time calculations ? // not recommended
+#define DOUBLE_BAUD_CALC(x) ((F_CPU+(x)*4UL) / (8UL*(x))-1UL) // macro calculating UBRR value for double speed
+
+#if !defined(__OPTIMIZE__)&&!defined(USART_NO_ABI_BREAKING_PREMATURES)
+	#warning Compiler optimizations disabled; functions from usart.h might not work as designed
+#endif
+
+#ifdef DEBUG
+	#define USART_NO_ABI_BREAKING_PREMATURES
+#endif
+
+#ifndef __AVR_ARCH__ // compiler fault ?
+	#define USART_NO_ABI_BREAKING_PREMATURES
+#endif
+
+#ifndef RX_BUFFER_SIZE
+	#define RX_BUFFER_SIZE 32 // Size of the ring buffers, must be power of 2
+#endif
+
+#ifndef TX_BUFFER_SIZE
+	#define TX_BUFFER_SIZE 32 // Size of the ring buffers, must be power of 2
+#endif
+
+#ifndef TX0_BUFFER_SIZE
+	#define TX0_BUFFER_SIZE TX_BUFFER_SIZE
+#endif
+#ifndef RX0_BUFFER_SIZE
+	#define RX0_BUFFER_SIZE RX_BUFFER_SIZE
+#endif
+#ifndef TX1_BUFFER_SIZE
+	#define TX1_BUFFER_SIZE TX_BUFFER_SIZE
+#endif
+#ifndef RX1_BUFFER_SIZE
+	#define RX1_BUFFER_SIZE RX_BUFFER_SIZE
+#endif
+#ifndef TX2_BUFFER_SIZE
+	#define TX2_BUFFER_SIZE TX_BUFFER_SIZE
+#endif
+#ifndef RX2_BUFFER_SIZE
+	#define RX2_BUFFER_SIZE RX_BUFFER_SIZE
+#endif
+#ifndef TX3_BUFFER_SIZE
+	#define TX3_BUFFER_SIZE TX_BUFFER_SIZE
+#endif
+#ifndef RX3_BUFFER_SIZE
+	#define RX3_BUFFER_SIZE RX_BUFFER_SIZE
+#endif
+
+#define TX0_BUFFER_MASK (TX0_BUFFER_SIZE - 1)
+#define RX0_BUFFER_MASK (RX0_BUFFER_SIZE - 1)
+
+#define TX1_BUFFER_MASK (TX1_BUFFER_SIZE - 1)
+#define RX1_BUFFER_MASK (RX1_BUFFER_SIZE - 1)
+
+#define TX2_BUFFER_MASK (TX2_BUFFER_SIZE - 1)
+#define RX2_BUFFER_MASK (RX2_BUFFER_SIZE - 1)
+
+#define TX3_BUFFER_MASK (TX3_BUFFER_SIZE - 1)
+#define RX3_BUFFER_MASK (RX3_BUFFER_SIZE - 1)
+
+enum {COMPLETED = 1, BUFFER_EMPTY = 0, BUFFER_FULL = 0};
+	
+#if defined(URSEL)||defined(URSEL0)||defined(URSEL1)||defined(URSEL2)||defined(URSEL3)
+
+	#define USART_XCK_RISING_EDGE 0x80
+	#define USART_XCK_FALLING_EDGE 0x81
+
+	#define USART_5BIT_DATA 0x80
+	#define USART_6BIT_DATA 0x82
+	#define USART_7BIT_DATA 0x84
+	#define USART_8BIT_DATA 0x86
+
+	#define USART_1STOP_BIT 0x80
+	#define USART_2STOP_BITS 0x88
+
+	#define USART_NO_PARITY 0x80
+	#define USART_EVEN_PARITY 0xA0
+	#define USART_ODD_PARITY 0xB0
+	
+	#define USART_ASYNC_MODE 0x80
+	#define USART_SYNC_MODE 0xC0
+#else
+	#define USART_XCK_RISING_EDGE 0x00
+	#define USART_XCK_FALLING_EDGE 0x01
+
+	#define USART_5BIT_DATA 0x00
+	#define USART_6BIT_DATA 0x02
+	#define USART_7BIT_DATA 0x04
+	#define USART_8BIT_DATA 0x06
+
+	#define USART_1STOP_BIT 0x00
+	#define USART_2STOP_BITS 0x08
+
+	#define USART_NO_PARITY 0x00
+	#define USART_EVEN_PARITY 0x20
+	#define USART_ODD_PARITY 0x30
+	
+	#define USART_ASYNC_MODE 0x00
+	#define USART_SYNC_MODE 0x40
+	#define USART_MSPI_MODE 0xC0
+#endif
+
+	#define USART_8N1 (USART_8BIT_DATA|USART_NO_PARITY|USART_1STOP_BIT)
+	#define USART_8N2 (USART_8BIT_DATA|USART_NO_PARITY|USART_2STOP_BITS)
+	#define USART_8E1 (USART_8BIT_DATA|USART_EVEN_PARITY|USART_1STOP_BIT)
+	#define USART_8E2 (USART_8BIT_DATA|USART_EVEN_PARITY|USART_2STOP_BITS)
+	#define USART_8O1 (USART_8BIT_DATA|USART_ODD_PARITY|USART_1STOP_BIT)
+	#define USART_8O2 (USART_8BIT_DATA|USART_ODD_PARITY|USART_2STOP_BITS)
+	#define USART_7N1 (USART_7BIT_DATA|USART_NO_PARITY|USART_1STOP_BIT)
+	#define USART_7N2 (USART_7BIT_DATA|USART_NO_PARITY|USART_2STOP_BITS)
+	#define USART_7E1 (USART_7BIT_DATA|USART_EVEN_PARITY|USART_1STOP_BIT)
+	#define USART_7E2 (USART_7BIT_DATA|USART_EVEN_PARITY|USART_2STOP_BITS)
+	#define USART_7O1 (USART_7BIT_DATA|USART_ODD_PARITY|USART_1STOP_BIT)
+	#define USART_7O2 (USART_7BIT_DATA|USART_ODD_PARITY|USART_2STOP_BITS)
+
+#ifdef NO_USART_RX // remove all RX interrupts
+	#define NO_RX0_INTERRUPT
+	#define NO_RX1_INTERRUPT
+	#define NO_RX2_INTERRUPT
+	#define NO_RX3_INTERRUPT
+#endif
+
+#ifdef NO_USART_TX // remove all TX interrupts
+	#define NO_TX0_INTERRUPT
+	#define NO_TX1_INTERRUPT
+	#define NO_TX2_INTERRUPT
+	#define NO_TX3_INTERRUPT
+#endif
+
+#ifdef USE_DOUBLE_SPEED 
+	#define USART0_U2X_SPEED
+	#define USART1_U2X_SPEED
+	#define USART2_U2X_SPEED
+	#define USART3_U2X_SPEED
+#endif
+
+#ifdef RX_GETC_ECHO
+	#define RX0_GETC_ECHO
+	#define RX1_GETC_ECHO
+	#define RX2_GETC_ECHO
+	#define RX3_GETC_ECHO
+#endif
+
+#ifdef PUTC_CONVERT_LF_TO_CRLF
+	#define PUTC0_CONVERT_LF_TO_CRLF
+	#define PUTC1_CONVERT_LF_TO_CRLF
+	#define PUTC2_CONVERT_LF_TO_CRLF
+	#define PUTC3_CONVERT_LF_TO_CRLF
+#endif
+
+#ifdef USART_EXTEND_RX_BUFFER
+	#define USART0_EXTEND_RX_BUFFER
+	#define USART1_EXTEND_RX_BUFFER
+	#define USART2_EXTEND_RX_BUFFER
+	#define USART3_EXTEND_RX_BUFFER
+#endif
+
+#ifdef USART_PUTC_FAST_INSERTIONS
+	#define USART0_PUTC_FAST_INSERTIONS
+	#define USART1_PUTC_FAST_INSERTIONS
+	#define USART2_PUTC_FAST_INSERTIONS
+	#define USART3_PUTC_FAST_INSERTIONS
+#endif
+
+#ifdef USART_MPCM_MODE
+	#define USART0_MPCM_MODE
+	#define USART1_MPCM_MODE
+	#define USART2_MPCM_MODE
+	#define USART3_MPCM_MODE
+#endif
+
+#if defined(CTS0_DDR)&&defined(CTS0_PORT)&&defined(CTS0_PIN)&&defined(CTS0_IONUM)
+	#define USART0_USE_SOFT_CTS
+#endif
+#if defined(CTS1_DDR)&&defined(CTS1_PORT)&&defined(CTS1_PIN)&&defined(CTS1_IONUM)
+	#define USART1_USE_SOFT_CTS
+#endif
+#if defined(CTS2_DDR)&&defined(CTS2_PORT)&&defined(CTS2_PIN)&&defined(CTS2_IONUM)
+	#define USART2_USE_SOFT_CTS
+#endif
+#if defined(CTS3_DDR)&&defined(CTS3_PORT)&&defined(CTS3_PIN)&&defined(CTS3_IONUM)
+	#define USART3_USE_SOFT_CTS
+#endif
+
+#if defined(RTS0_DDR)&&defined(RTS0_PORT)&&defined(RTS0_PIN)&&defined(RTS0_IONUM)
+	#define USART0_USE_SOFT_RTS
+#endif
+#if defined(RTS1_DDR)&&defined(RTS1_PORT)&&defined(RTS1_PIN)&&defined(RTS1_IONUM)
+	#define USART1_USE_SOFT_RTS
+#endif
+#if defined(RTS2_DDR)&&defined(RTS2_PORT)&&defined(RTS2_PIN)&&defined(RTS2_IONUM)
+	#define USART2_USE_SOFT_RTS
+#endif
+#if defined(RTS3_DDR)&&defined(RTS3_PORT)&&defined(RTS3_PIN)&&defined(RTS3_IONUM)
+	#define USART3_USE_SOFT_RTS
+#endif
+
+#if defined(RS485_CONTROL0_DDR)&&defined(RS485_CONTROL0_PORT)&&defined(RS485_CONTROL0_PIN)&&defined(RS485_CONTROL0_IONUM)
+	#define USART0_RS485_MODE
+#endif
+#if defined(RS485_CONTROL1_DDR)&&defined(RS485_CONTROL1_PORT)&&defined(RS485_CONTROL1_PIN)&&defined(RS485_CONTROL1_IONUM)
+	#define USART1_RS485_MODE
+#endif
+#if defined(RS485_CONTROL2_DDR)&&defined(RS485_CONTROL2_PORT)&&defined(RS485_CONTROL2_PIN)&&defined(RS485_CONTROL2_IONUM)
+	#define USART2_RS485_MODE
+#endif
+#if defined(RS485_CONTROL3_DDR)&&defined(RS485_CONTROL3_PORT)&&defined(RS485_CONTROL3_PIN)&&defined(RS485_CONTROL3_IONUM)
+	#define USART3_RS485_MODE
+#endif
+
+#ifdef USART0_USE_SOFT_RTS
+	#ifndef USART0_EXTEND_RX_BUFFER
+		#define USART0_EXTEND_RX_BUFFER
+	#endif
+#endif
+
+#ifdef USART1_USE_SOFT_RTS
+	#ifndef USART1_EXTEND_RX_BUFFER
+		#define USART1_EXTEND_RX_BUFFER
+	#endif
+#endif
+
+#ifdef USART2_USE_SOFT_RTS
+	#ifndef USART2_EXTEND_RX_BUFFER
+		#define USART2_EXTEND_RX_BUFFER
+	#endif
+#endif
+
+#ifdef USART3_USE_SOFT_RTS
+	#ifndef USART3_EXTEND_RX_BUFFER
+		#define USART3_EXTEND_RX_BUFFER
+	#endif
+#endif
+
+#ifdef RX_NEWLINE_MODE
+	
+	#if (RX_NEWLINE_MODE == 0)
+		#define RX_NEWLINE_MODE_R
+	#elif (RX_NEWLINE_MODE == 1)
+		#define RX_NEWLINE_MODE_N
+	#else // RX_NEWLINE_MODE == 2
+		#define RX_NEWLINE_MODE_RN
+	#endif
+#else
+	#define RX_NEWLINE_MODE_RN // 2
+#endif
+
+#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+	register uint8_t USART_SREG_SAVE_REG_NAME asm(USART_SREG_SAVE_REG_NUM); // have to be defined separately in every compilation unit
+#endif
+
+#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+	register uint16_t USART_Z_SAVE_REG_NAME asm(USART_Z_SAVE_REG_NUM); // have to be defined separately in every compilation unit
+#endif
+
+#if defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)&&defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE)
+	#define USART_REG_SAVE_LIST \
+		[sreg_save] "+r" (USART_SREG_SAVE_REG_NAME), \
+		[z_save] "+r" (USART_Z_SAVE_REG_NAME)
+		
+#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE)
+	#define USART_REG_SAVE_LIST \
+		[z_save] "+r" (USART_Z_SAVE_REG_NAME)
+	
+#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
+	#define USART_REG_SAVE_LIST \
+		[sreg_save] "+r" (USART_SREG_SAVE_REG_NAME)
+#else
+	#define USART_REG_SAVE_LIST
+#endif
+
+#if defined(__usbdrv_h_included__)&&!defined(USART_UNSAFE_RX_INTERRUPT)
+	#warning "usb may not work with uart's RX ISR"
+#endif
+
+#if defined(__usbdrv_h_included__)&&!defined(USART_UNSAFE_TX_INTERRUPT)
+	#warning "usb may not work with uart's TX ISR"
+#endif
+
+#if (defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)||defined(USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE))&&(defined(USART_UNSAFE_TX_INTERRUPT)||defined(USART_UNSAFE_RX_INTERRUPT))
+	#warning "using globally reserved save registers with interruptable interrupts might create special conditions"
+#endif
+
+#if defined(__AVR_ATtiny102__)||defined(__AVR_ATtiny104__)||defined(__AVR_ATtiny2313__)||defined(__AVR_ATtiny2313A__)
+	#define USART_USE_TINY_MEMORY_MODEL
+#endif
+
+#if defined(__AVR_ATtiny102__)||defined(__AVR_ATtiny104__)
+
+#if (TX0_BUFFER_SIZE > 8)||(RX0_BUFFER_SIZE > 8)
+	#warning "TX or RX buffer may be too large for this mcu"
+#endif
+
+#define USART0_IN_UPPER_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RXC_vect
+	#define TXC0_INTERRUPT  	USART0_TXC_vect
+	#define UDRE0_INTERRUPT		USART0_DRE_vect
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT   		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+	
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATtiny2313__)||defined(__AVR_ATtiny2313A__)||defined(__AVR_ATtiny4313)
+
+#define USART0_IN_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART_RX_vect
+	#define TXC0_INTERRUPT  	USART_TX_vect
+	#define UDRE0_INTERRUPT		USART_UDRE_vect
+	#define UDR0_REGISTER		UDR
+	#define UBRR0L_REGISTER		UBRRL
+	#define UBRR0H_REGISTER		UBRRH
+	#define UCSR0A_REGISTER		UCSRA
+	#define UCSR0B_REGISTER		UCSRB
+	#define UCSR0C_REGISTER		UCSRC
+	#define TXCIE0_BIT      	TXCIE
+	#define UDRIE0_BIT    		UDRIE
+	#define RXCIE0_BIT  		RXCIE
+	#define TXEN0_BIT   		TXEN
+	#define RXEN0_BIT   		RXEN
+	#define UDRE0_BIT   		UDRE
+	#define RXC0_BIT    		RXC
+	#define U2X0_BIT    		U2X
+	#define MPCM0_BIT   		MPCM
+	#define UCSZ02_BIT  		UCSZ2
+	#define TXB80_BIT   		TXB8
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATtiny1634__)
+
+#define USART0_IN_UPPER_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT  	USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT  	USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+
+#endif //NO_USART1
+#endif
+
+#if defined(__AVR_ATtiny441__)||defined(__AVR_ATtiny841__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT  	USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT  	USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+
+#endif //NO_USART1
+#endif
+
+#if defined(__AVR_ATmega48__)||defined(__AVR_ATmega48P__)||defined(__AVR_ATmega48PA__)||defined(__AVR_ATmega48PB__)\
+||defined(__AVR_ATmega88__)||defined(__AVR_ATmega88P__)||defined(__AVR_ATmega88PA__)||defined(__AVR_ATmega88PB__)\
+||defined(__AVR_ATmega168__)||defined(__AVR_ATmega168P__)||defined(__AVR_ATmega168PA__)||defined(__AVR_ATmega168PB__)\
+||defined(__AVR_ATmega328__)||defined(__AVR_ATmega328P__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART_RX_vect
+	#define TXC0_INTERRUPT  	USART_TX_vect
+	#define UDRE0_INTERRUPT		USART_UDRE_vect
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT   		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80	
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATmega328PB__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT   		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT  	USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT   		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81	
+
+#endif //NO_USART1
+#endif
+
+#if defined(__AVR_ATmega8__)||defined(__AVR_ATmega8P__)||defined(__AVR_ATmega16__)\
+||defined(__AVR_ATmega16A__)||defined(__AVR_ATmega32__)||defined(__AVR_ATmega32A__)\
+||defined(__AVR_ATmega8A__)||defined(__AVR_ATmega8L__)
+
+#define USART0_IN_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART_RXC_vect
+	#define TXC0_INTERRUPT		USART_TXC_vect
+	#define UDRE0_INTERRUPT 	USART_UDRE_vect 
+	#define UDR0_REGISTER		UDR
+	#define UBRR0L_REGISTER		UBRRL
+	#define UBRR0H_REGISTER		UBRRH
+	#define UCSR0A_REGISTER		UCSRA
+	#define UCSR0B_REGISTER		UCSRB
+	#define UCSR0C_REGISTER		UCSRC
+	#define TXCIE0_BIT	    	TXCIE
+	#define UDRIE0_BIT    		UDRIE
+	#define RXCIE0_BIT  		RXCIE
+	#define TXEN0_BIT   		TXEN
+	#define RXEN0_BIT   		RXEN
+	#define UDRE0_BIT   		UDRE
+	#define RXC0_BIT    		RXC
+	#define U2X0_BIT    		U2X
+	#define MPCM0_BIT   		MPCM
+	#define UCSZ02_BIT  		UCSZ2
+	#define TXB80_BIT   		TXB8
+	
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATmega8515__)||defined(__AVR_ATmega8515L__)
+
+#define USART0_IN_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART_RX_vect
+	#define TXC0_INTERRUPT		USART_TX_vect
+	#define UDRE0_INTERRUPT		USART_UDRE_vect 
+	#define UDR0_REGISTER		UDR
+	#define UBRR0L_REGISTER		UBRRL
+	#define UBRR0H_REGISTER		UBRRH
+	#define UCSR0A_REGISTER		UCSRA
+	#define UCSR0B_REGISTER		UCSRB
+	#define UCSR0C_REGISTER		UCSRC
+	#define TXCIE0_BIT      	TXCIE
+	#define UDRIE0_BIT    		UDRIE
+	#define RXCIE0_BIT  		RXCIE
+	#define TXEN0_BIT   		TXEN
+	#define RXEN0_BIT   		RXEN
+	#define UDRE0_BIT   		UDRE
+	#define RXC0_BIT    		RXC
+	#define U2X0_BIT    		U2X
+	#define MPCM0_BIT   		MPCM
+	#define UCSZ02_BIT  		UCSZ2
+	#define TXB80_BIT   		TXB8
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATmega162__)
+
+#define USART0_IN_IO_ADDRESS_SPACE
+#define USART1_IN_IO_ADDRESS_SPACE
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RXC_vect
+	#define TXC0_INTERRUPT		USART0_TXC_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RXC_vect
+	#define TXC1_INTERRUPT		USART1_TXC_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect 
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+
+#endif //NO_USART1
+#endif
+
+#if defined(__AVR_ATmega128__)||defined(__AVR_ATmega128A__)||defined(__AVR_ATmega64__)\
+||defined(__AVR_ATmega64A__)
+	#define USART0_IN_IO_ADDRESS_SPACE
+#endif
+
+#if defined(__AVR_ATmega644__)||defined(__AVR_ATmega644P__)||defined(__AVR_ATmega644PA__)\
+||defined(__AVR_ATmega1284__)||defined(__AVR_ATmega1284P__)||defined(__AVR_ATmega128__)\
+||defined(__AVR_ATmega128A__)||defined(__AVR_ATmega64__)||defined(__AVR_ATmega64A__)\
+||defined(__AVR_ATmega1281__)||defined(__AVR_ATmega2561__)||defined(__AVR_ATmega640__)\
+||defined(__AVR_ATmega1280__)||defined(__AVR_ATmega2560__)||defined(__AVR_ATmega164P__)\
+||defined(__AVR_ATmega324P__)||defined(__AVR_ATmega324A__)||defined(__AVR_ATmega324PA__)\
+||defined(__AVR_ATmega324PB__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif
+
+#if !defined(NO_USART1) && !defined(__AVR_ATmega644__)
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT		USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect 
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+	
+#endif // NO_USART1 && 644
+
+#endif
+
+#if defined(__AVR_ATmega640__)||defined(__AVR_ATmega1280__)||defined(__AVR_ATmega2560__)||defined(__AVR_ATmega324PB__)
+
+#ifndef NO_USART2
+#define USE_USART2
+
+	#define RX2_INTERRUPT		USART2_RX_vect
+	#define TXC2_INTERRUPT		USART2_TX_vect
+	#define UDRE2_INTERRUPT		USART2_UDRE_vect 
+	#define UDR2_REGISTER		UDR2
+	#define UBRR2L_REGISTER		UBRR2L
+	#define UBRR2H_REGISTER		UBRR2H
+	#define UCSR2A_REGISTER		UCSR2A
+	#define UCSR2B_REGISTER		UCSR2B
+	#define UCSR2C_REGISTER		UCSR2C
+	#define TXCIE2_BIT      	TXCIE2
+	#define UDRIE2_BIT    		UDRIE2
+	#define RXCIE2_BIT  		RXCIE2
+	#define TXEN2_BIT   		TXEN2
+	#define RXEN2_BIT   		RXEN2
+	#define UDRE2_BIT   		UDRE2
+	#define RXC2_BIT    		RXC2
+	#define U2X2_BIT    		U2X2
+	#define MPCM2_BIT   		MPCM2
+	#define UCSZ22_BIT  		UCSZ22
+	#define TXB82_BIT   		TXB82
+	
+#endif // NO_USART2
+
+#if !defined(NO_USART3)&&!defined(__AVR_ATmega324PB__)
+#define USE_USART3
+
+	#define RX3_INTERRUPT		USART3_RX_vect
+	#define TXC3_INTERRUPT		USART3_TX_vect
+	#define UDRE3_INTERRUPT		USART3_UDRE_vect 
+	#define UDR3_REGISTER		UDR3
+	#define UBRR3L_REGISTER 	UBRR3L
+	#define UBRR3H_REGISTER		UBRR3H
+	#define UCSR3A_REGISTER		UCSR3A
+	#define UCSR3B_REGISTER		UCSR3B
+	#define UCSR3C_REGISTER		UCSR3C
+	#define TXCIE3_BIT      	TXCIE3
+	#define UDRIE3_BIT    		UDRIE3
+	#define RXCIE3_BIT  		RXCIE3
+	#define TXEN3_BIT   		TXEN3
+	#define RXEN3_BIT   		RXEN3
+	#define UDRE3_BIT   		UDRE3
+	#define RXC3_BIT    		RXC3
+	#define U2X3_BIT    		U2X3
+	#define MPCM3_BIT   		MPCM3
+	#define UCSZ32_BIT  		UCSZ32
+	#define TXB83_BIT   		TXB83
+	
+#endif // NO_USART3
+#endif // 640/1280/2560 usart 2 & 3 
+
+#if defined(__AVR_ATmega8U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega16U4__)\
+||defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U6__)\
+||defined(__AVR_AT90USB82__)||defined(__AVR_AT90USB162__)
+
+#define USART1_HARDWARE_FLOW_CONTROL_AVAILABLE
+
+#ifndef NO_USART1 // we will call the only usart, as an usart0
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT		USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect 
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define UCSR1D_REGISTER		UCSR1D
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+	#define CTSEN1_BIT  		CTSEN
+	#define RTSEN1_BIT  		RTSEN
+
+#endif // NO_USART1
+#endif
+
+#if defined(__AVR_ATmega169A__)||defined(__AVR_ATmega169__)||defined(__AVR_ATmega169P__)||defined(__AVR_ATmega169PA__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR
+	#define UBRR0L_REGISTER		UBRRL
+	#define UBRR0H_REGISTER		UBRRH
+	#define UCSR0A_REGISTER		UCSRA
+	#define UCSR0B_REGISTER		UCSRB
+	#define UCSR0C_REGISTER		UCSRC
+	#define TXCIE0_BIT      	TXCIE
+	#define UDRIE0_BIT    		UDRIE
+	#define RXCIE0_BIT  		RXCIE
+	#define TXEN0_BIT   		TXEN
+	#define RXEN0_BIT   		RXEN
+	#define UDRE0_BIT   		UDRE
+	#define RXC0_BIT    		RXC
+	#define U2X0_BIT    		U2X
+	#define MPCM0_BIT   		MPCM
+	#define UCSZ02_BIT  		UCSZ2
+	#define TXB80_BIT   		TXB8
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATmega329__)||defined(__AVR_ATmega329P__)||defined(__AVR_ATmega329PA__)\
+||defined(__AVR_ATmega329A__)||defined(__AVR_ATmega649__)||defined(__AVR_ATmega649A__)\
+||defined(__AVR_ATmega649P__)||defined(__AVR_ATmega169P__)||defined(__AVR_ATmega169PA__)\
+||defined(__AVR_ATmega325__)||defined(__AVR_ATmega325A__)||defined(__AVR_ATmega325P__)\
+||defined(__AVR_ATmega325PA__)||defined(__AVR_ATmega645__)||defined(__AVR_ATmega645A__)\
+||defined(__AVR_ATmega645P__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_ATmega3290__)||defined(__AVR_ATmega6490__)||defined(__AVR_ATmega3290P__)\
+||defined(__AVR_ATmega3290PA__)||defined(__AVR_ATmega3290A__)||defined(__AVR_ATmega6490A__)\
+||defined(__AVR_ATmega6490P__)||defined(__AVR_ATmega3250__)||defined(__AVR_ATmega3250A__)\
+||defined(__AVR_ATmega3250P__)||defined(__AVR_ATmega3250PA__)||defined(__AVR_ATmega6450__)\
+||defined(__AVR_ATmega6450A__)||defined(__AVR_ATmega6450P__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART_RX_vect // wtf
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif //NO_USART0
+#endif
+
+#if defined(__AVR_AT90CAN32__)||defined(__AVR_AT90CAN64__)||defined(__AVR_AT90CAN128__)\
+||defined(__AVR_ATmega64RFR2__)||defined(__AVR_ATmega128RFR2__)||defined(__AVR_ATmega256RFR2__)\
+||defined(__AVR_ATmega644RFR2__)||defined(__AVR_ATmega1284RFR2__)||defined(__AVR_ATmega2564RFR2__)\
+||defined(__AVR_ATmega128RFA1__)
+
+#ifndef NO_USART0
+#define USE_USART0
+
+	#define RX0_INTERRUPT		USART0_RX_vect
+	#define TXC0_INTERRUPT		USART0_TX_vect
+	#define UDRE0_INTERRUPT		USART0_UDRE_vect 
+	#define UDR0_REGISTER		UDR0
+	#define UBRR0L_REGISTER		UBRR0L
+	#define UBRR0H_REGISTER		UBRR0H
+	#define UCSR0A_REGISTER		UCSR0A
+	#define UCSR0B_REGISTER		UCSR0B
+	#define UCSR0C_REGISTER		UCSR0C
+	#define TXCIE0_BIT      	TXCIE0
+	#define UDRIE0_BIT    		UDRIE0
+	#define RXCIE0_BIT  		RXCIE0
+	#define TXEN0_BIT   		TXEN0
+	#define RXEN0_BIT   		RXEN0
+	#define UDRE0_BIT   		UDRE0
+	#define RXC0_BIT    		RXC0
+	#define U2X0_BIT    		U2X0
+	#define MPCM0_BIT   		MPCM0
+	#define UCSZ02_BIT  		UCSZ02
+	#define TXB80_BIT   		TXB80
+
+#endif // NO_USART0
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT		USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect 
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+	
+#endif // NO_USART1
+#endif
+
+#if defined(__AVR_AT90USB646__)||defined(__AVR_AT90USB647__)||defined(__AVR_AT90USB1286__)||defined(__AVR_AT90USB1287__)
+
+#ifndef NO_USART1
+#define USE_USART1
+
+	#define RX1_INTERRUPT		USART1_RX_vect
+	#define TXC1_INTERRUPT		USART1_TX_vect
+	#define UDRE1_INTERRUPT		USART1_UDRE_vect 
+	#define UDR1_REGISTER		UDR1
+	#define UBRR1L_REGISTER		UBRR1L
+	#define UBRR1H_REGISTER		UBRR1H
+	#define UCSR1A_REGISTER		UCSR1A
+	#define UCSR1B_REGISTER		UCSR1B
+	#define UCSR1C_REGISTER		UCSR1C
+	#define TXCIE1_BIT      	TXCIE1
+	#define UDRIE1_BIT    		UDRIE1
+	#define RXCIE1_BIT  		RXCIE1
+	#define TXEN1_BIT   		TXEN1
+	#define RXEN1_BIT   		RXEN1
+	#define UDRE1_BIT   		UDRE1
+	#define RXC1_BIT    		RXC1
+	#define U2X1_BIT    		U2X1
+	#define MPCM1_BIT   		MPCM1
+	#define UCSZ12_BIT  		UCSZ12
+	#define TXB81_BIT   		TXB81
+
+#endif // NO_USART1
+#endif
+
+#if defined(USART_REMAP_LAST_INTERFACE)&&!defined(USE_USART0)&&defined(USE_USART1)&&!defined(USE_USART2)&&!defined(USE_USART3)
+	#undef USE_USART1
+	#define USE_USART0
+	
+	#ifdef USART1_HARDWARE_FLOW_CONTROL_AVAILABLE
+		#define USART0_HARDWARE_FLOW_CONTROL_AVAILABLE
+	
+		#define UCSR0D_REGISTER    UCSR1D_REGISTER
+		#define CTSEN0_BIT         CTSEN1_BIT
+		#define RTSEN0_BIT         RTSEN1_BIT
+	#endif
+	
+	#define RX0_INTERRUPT		RX1_INTERRUPT
+	#define TXC0_INTERRUPT		TXC1_INTERRUPT
+	#define UDRE0_INTERRUPT		UDRE1_INTERRUPT
+	#define UDR0_REGISTER		UDR1_REGISTER
+	#define UBRR0L_REGISTER		UBRR1L_REGISTER
+	#define UBRR0H_REGISTER		UBRR1H_REGISTER
+	#define UCSR0A_REGISTER		UCSR1A_REGISTER
+	#define UCSR0B_REGISTER		UCSR1B_REGISTER
+	#define UCSR0C_REGISTER		UCSR1C_REGISTER
+	#define TXCIE0_BIT      	TXCIE1_BIT
+	#define UDRIE0_BIT    		UDRIE1_BIT
+	#define RXCIE0_BIT  		RXCIE1_BIT
+	#define TXEN0_BIT   		TXEN1_BIT
+	#define RXEN0_BIT   		RXEN1_BIT
+	#define UDRE0_BIT   		UDRE1_BIT
+	#define RXC0_BIT    		RXC1_BIT
+	#define U2X0_BIT    		U2X1_BIT
+	#define MPCM0_BIT   		MPCM1_BIT
+	#define UCSZ02_BIT  		UCSZ12_BIT
+	#define TXB80_BIT   		TXB81_BIT
+#endif
+
+#if defined(USART_REMAP_LAST_INTERFACE)&&!defined(USE_USART0)&&!defined(USE_USART1)&&defined(USE_USART2)&&!defined(USE_USART3)
+	#undef USE_USART2
+	#define USE_USART0
+	
+	#define RX0_INTERRUPT		RX2_INTERRUPT
+	#define TXC0_INTERRUPT		TXC2_INTERRUPT
+	#define UDRE0_INTERRUPT		UDRE2_INTERRUPT
+	#define UDR0_REGISTER		UDR2_REGISTER
+	#define UBRR0L_REGISTER		UBRR2L_REGISTER
+	#define UBRR0H_REGISTER		UBRR2H_REGISTER
+	#define UCSR0A_REGISTER		UCSR2A_REGISTER
+	#define UCSR0B_REGISTER		UCSR2B_REGISTER
+	#define UCSR0C_REGISTER		UCSR2C_REGISTER
+	#define TXCIE0_BIT      	TXCIE2_BIT
+	#define UDRIE0_BIT    		UDRIE2_BIT
+	#define RXCIE0_BIT  		RXCIE2_BIT
+	#define TXEN0_BIT   		TXEN2_BIT
+	#define RXEN0_BIT   		RXEN2_BIT
+	#define UDRE0_BIT   		UDRE2_BIT
+	#define RXC0_BIT    		RXC2_BIT
+	#define U2X0_BIT    		U2X2_BIT
+	#define MPCM0_BIT   		MPCM2_BIT
+	#define UCSZ02_BIT   		UCSZ22_BIT
+	#define TXB80_BIT   		TXB82_BIT
+#endif
+
+#if defined(USART_REMAP_LAST_INTERFACE)&&!defined(USE_USART0)&&!defined(USE_USART1)&&!defined(USE_USART2)&&defined(USE_USART3)
+	#undef USE_USART3
+	#define USE_USART0
+	
+	#define RX0_INTERRUPT		RX3_INTERRUPT
+	#define TXC0_INTERRUPT		TXC3_INTERRUPT
+	#define UDRE0_INTERRUPT		UDRE3_INTERRUPT
+	#define UDR0_REGISTER		UDR3_REGISTER
+	#define UBRR0L_REGISTER		UBRR3L_REGISTER
+	#define UBRR0H_REGISTER		UBRR3H_REGISTER
+	#define UCSR0A_REGISTER		UCSR3A_REGISTER
+	#define UCSR0B_REGISTER		UCSR3B_REGISTER
+	#define UCSR0C_REGISTER		UCSR3C_REGISTER
+	#define TXCIE0_BIT      	TXCIE3_BIT
+	#define UDRIE0_BIT    		UDRIE3_BIT
+	#define RXCIE0_BIT  		RXCIE3_BIT
+	#define TXEN0_BIT   		TXEN3_BIT
+	#define RXEN0_BIT   		RXEN3_BIT
+	#define UDRE0_BIT   		UDRE3_BIT
+	#define RXC0_BIT    		RXC3_BIT
+	#define U2X0_BIT    		U2X3_BIT
+	#define MPCM0_BIT   		MPCM3_BIT
+	#define UCSZ02_BIT   		UCSZ32_BIT
+	#define TXB80_BIT   		TXB83_BIT
+#endif
+
+#if !defined(USE_USART0) && !defined(USE_USART1) && !defined(USE_USART2) && !defined(USE_USART3)
+	#warning "USART not available or unknown mcu"
+#endif
+
+#ifndef USE_USART0 
+	#define NO_TX0_INTERRUPT
+	#define NO_RX0_INTERRUPT
+#endif
+
+#ifndef USE_USART1
+	#define NO_TX1_INTERRUPT
+	#define NO_RX1_INTERRUPT
+#endif
+
+#ifndef USE_USART2
+	#define NO_TX2_INTERRUPT
+	#define NO_RX2_INTERRUPT
+#endif
+
+#ifndef USE_USART3
+	#define NO_TX3_INTERRUPT
+	#define NO_RX3_INTERRUPT
+#endif
+
+#if (defined(USE_USART0)&&!defined(USE_USART1)&&!defined(USE_USART2)&&!defined(USE_USART3))
+	#ifdef NO_TX0_INTERRUPT
+		#define NO_USART_TX
+	#endif
+	
+	#ifdef NO_RX0_INTERRUPT
+		#define NO_USART_RX
+	#endif
+#endif
+
+#if defined(USART0_RS485_MODE)&&!defined(NO_TX0_INTERRUPT)
+	#define USART0_USE_TXC_INTERRUPT
+#endif
+
+#if defined(USART1_RS485_MODE)&&!defined(NO_TX1_INTERRUPT)
+	#define USART1_USE_TXC_INTERRUPT
+#endif
+
+#if defined(USART2_RS485_MODE)&&!defined(NO_TX2_INTERRUPT)
+	#define USART2_USE_TXC_INTERRUPT
+#endif
+
+#if defined(USART3_RS485_MODE)&&!defined(NO_TX3_INTERRUPT)
+	#define USART3_USE_TXC_INTERRUPT
+#endif
+
+#ifndef USART0_CONFIG_B // set config bytes for UCSR0B_REGISTER
+	
+	#ifdef USART0_MPCM_MODE
+		#if defined(NO_RX0_INTERRUPT)
+			#define USART0_CONFIG_B (1<<TXEN0_BIT)|(1<<UCSZ02_BIT)
+		
+		#elif defined(NO_TX0_INTERRUPT)
+			#define USART0_CONFIG_B (1<<RXEN0_BIT)|(1<<RXCIE0_BIT)|(1<<UCSZ02_BIT)
+		#else
+			#ifdef USART0_RS485_MODE
+				#define USART0_CONFIG_B (1<<TXEN0_BIT)|(1<<TXCIE0_BIT)|(1<<RXEN0_BIT)|(1<<RXCIE0_BIT)|(1<<UCSZ02_BIT)
+			#else
+				#define USART0_CONFIG_B (1<<TXEN0_BIT)|(1<<RXEN0_BIT)|(1<<RXCIE0_BIT)|(1<<UCSZ02_BIT)
+			#endif
+		#endif
+	#else
+		#if defined(NO_RX0_INTERRUPT)
+			#define USART0_CONFIG_B (1<<TXEN0_BIT)
+		
+		#elif defined(NO_TX0_INTERRUPT)
+			#define USART0_CONFIG_B (1<<RXEN0_BIT)|(1<<RXCIE0_BIT)
+		#else
+			#ifdef USART0_RS485_MODE
+				#define USART0_CONFIG_B (1<<TXEN0_BIT)|(1<<TXCIE0_BIT)|(1<<RXEN0_BIT)|(1<<RXCIE0_BIT)
+			#else
+				#define USART0_CONFIG_B (1<<TXEN0_BIT)|(1<<RXEN0_BIT)|(1<<RXCIE0_BIT)
+			#endif
+		#endif
+	#endif
+#endif // USART0_CONFIG
+
+#ifndef USART1_CONFIG_B // set config bytes for UCSR1B_REGISTER
+	
+	#ifdef USART1_MPCM_MODE
+		#if defined(NO_RX1_INTERRUPT)
+			#define USART1_CONFIG_B (1<<TXEN1_BIT)|(1<<UCSZ12_BIT)
+	
+		#elif defined(NO_TX1_INTERRUPT)
+			#define USART1_CONFIG_B (1<<RXEN1_BIT)|(1<<RXCIE1_BIT)|(1<<UCSZ12_BIT)
+		#else
+			#ifdef USART1_RS485_MODE
+				#define USART1_CONFIG_B (1<<TXEN1_BIT)|(1<<TXCIE1_BIT)|(1<<RXEN1_BIT)|(1<<RXCIE1_BIT)|(1<<UCSZ12_BIT)
+			#else
+				#define USART1_CONFIG_B (1<<TXEN1_BIT)|(1<<RXEN1_BIT)|(1<<RXCIE1_BIT)|(1<<UCSZ12_BIT)
+			#endif
+		#endif
+	#else
+		#if defined(NO_RX1_INTERRUPT)
+			#define USART1_CONFIG_B (1<<TXEN1_BIT)
+
+		#elif defined(NO_TX1_INTERRUPT)
+			#define USART1_CONFIG_B (1<<RXEN1_BIT)|(1<<RXCIE1_BIT)
+		#else
+			#ifdef USART1_RS485_MODE
+				#define USART1_CONFIG_B (1<<TXEN1_BIT)|(1<<TXCIE1_BIT)|(1<<RXEN1_BIT)|(1<<RXCIE1_BIT)
+			#else
+				#define USART1_CONFIG_B (1<<TXEN1_BIT)|(1<<RXEN1_BIT)|(1<<RXCIE1_BIT)
+			#endif
+		#endif
+	#endif
+#endif // USART1_CONFIG
+
+#ifndef USART2_CONFIG_B // set config bytes for UCSR2B_REGISTER
+
+	#ifdef USART2_MPCM_MODE
+		#if defined(NO_RX2_INTERRUPT)
+			#define USART2_CONFIG_B (1<<TXEN2_BIT)|(1<<UCSZ22_BIT)
+	
+		#elif defined(NO_TX2_INTERRUPT)
+			#define USART2_CONFIG_B (1<<RXEN2_BIT)|(1<<RXCIE2_BIT)|(1<<UCSZ22_BIT)
+		#else
+			#ifdef USART2_RS485_MODE
+				#define USART2_CONFIG_B (1<<TXEN2_BIT)|(1<<TXCIE2_BIT)|(1<<RXEN2_BIT)|(1<<RXCIE2_BIT)|(1<<UCSZ22_BIT)
+			#else
+				#define USART2_CONFIG_B (1<<TXEN2_BIT)|(1<<RXEN2_BIT)|(1<<RXCIE2_BIT)|(1<<UCSZ22_BIT)
+			#endif
+		#endif
+	#else
+		#if defined(NO_RX2_INTERRUPT)
+			#define USART2_CONFIG_B (1<<TXEN2_BIT)
+
+		#elif defined(NO_TX2_INTERRUPT)
+			#define USART2_CONFIG_B (1<<RXEN2_BIT)|(1<<RXCIE2_BIT)
+		#else
+			#ifdef USART2_RS485_MODE
+				#define USART2_CONFIG_B (1<<TXEN2_BIT)|(1<<TXCIE2_BIT)|(1<<RXEN2_BIT)|(1<<RXCIE2_BIT)
+			#else	
+				#define USART2_CONFIG_B (1<<TXEN2_BIT)|(1<<RXEN2_BIT)|(1<<RXCIE2_BIT)
+			#endif
+		#endif
+	#endif
+#endif // USART2_CONFIG
+
+#ifndef USART3_CONFIG_B // set config bytes for UCSR3B_REGISTER
+
+	#ifdef USART3_MPCM_MODE
+		#if defined(NO_RX3_INTERRUPT)
+			#define USART3_CONFIG_B (1<<TXEN3_BIT)|(1<<UCSZ32_BIT)
+	
+		#elif defined(NO_TX3_INTERRUPT)
+			#define USART3_CONFIG_B (1<<RXEN3_BIT)|(1<<RXCIE3_BIT)|(1<<UCSZ32_BIT)
+		#else
+			#ifdef USART3_RS485_MODE
+				#define USART3_CONFIG_B (1<<TXEN3_BIT)|(1<<TXCIE3_BIT)|(1<<RXEN3_BIT)|(1<<RXCIE3_BIT)|(1<<UCSZ32_BIT)
+			#else
+				#define USART3_CONFIG_B (1<<TXEN3_BIT)|(1<<RXEN3_BIT)|(1<<RXCIE3_BIT)|(1<<UCSZ32_BIT)
+			#endif
+		#endif
+	#else	
+		#if defined(NO_RX3_INTERRUPT)
+			#define USART3_CONFIG_B (1<<TXEN3_BIT)
+		
+		#elif defined(NO_TX3_INTERRUPT)
+			#define USART3_CONFIG_B (1<<RXEN3_BIT)|(1<<RXCIE3_BIT)
+		#else
+			#ifdef USART3_RS485_MODE
+				#define USART3_CONFIG_B (1<<TXEN3_BIT)|(1<<TXCIE3_BIT)|(1<<RXEN3_BIT)|(1<<RXCIE3_BIT)
+			#else
+				#define USART3_CONFIG_B (1<<TXEN3_BIT)|(1<<RXEN3_BIT)|(1<<RXCIE3_BIT)
+			#endif
+		#endif
+	#endif
+#endif // USART3_CONFIG
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/************************************************************************************
+ *                                   Initializers                                   *
+ ************************************************************************************/
+	
+	// functions smaller then calling overhead (including context saves) or executed once are inline for reducing 
+	// flash memory usage (eg. if() statements routines can be executed during compilation)
+	
+#ifdef USE_USART0
+	void uart0_reinit(uint16_t ubrr_value); // for runtime reinitialization of uart
+	
+	static inline void uart0_init(uint16_t ubrr_value) __attribute__((always_inline));
+	static inline void uart0_init(uint16_t ubrr_value) // have to be called once at startup
+	{
+	#ifdef USART0_RS485_MODE
+		RS485_CONTROL0_DDR |= (1<<RS485_CONTROL0_IONUM); // default pin state is low
+	#endif
+		
+		UBRR0L_REGISTER = (uint8_t) ubrr_value;
+		
+	#ifdef USART_SKIP_UBRRH_IF_ZERO
+		if(__builtin_constant_p(ubrr_value))
+			if(((ubrr_value>>8) != 0)) // requires -Os flag - do not use in non-inline functions
+	#endif
+			UBRR0H_REGISTER = (ubrr_value>>8);
+		
+	#ifdef USART0_U2X_SPEED
+		#ifdef USART0_MPCM_MODE
+			UCSR0A_REGISTER = (1<<U2X0_BIT)|(1<<MPCM0_BIT);
+		#else
+			UCSR0A_REGISTER = (1<<U2X0_BIT); // enable double speed
+		#endif
+	#elif defined(USART0_MPCM_MODE)
+		UCSR0A_REGISTER |= (1<<MPCM0_BIT);
+	#endif
+		
+		UCSR0B_REGISTER = USART0_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART0_USE_SOFT_RTS
+		RTS0_DDR |= (1<<RTS0_IONUM);
+	#endif
+	}
+	
+	static inline void uart0_set_FrameFormat(uint8_t UCSRC_reg) __attribute__((always_inline));
+	static inline void uart0_set_FrameFormat(uint8_t UCSRC_reg) // UCSRC_reg can be used to set other than 8n1 transmission
+	{
+		UCSR0C_REGISTER = UCSRC_reg;
+	} 
+	
+	static inline void uart0_set_U2X(void) __attribute__((always_inline));
+	static inline void uart0_set_U2X(void) // use instead of USE_DOUBLE_SPEED 
+	{
+		UCSR0A_REGISTER |= (1<<U2X0_BIT);
+	} 
+
+#ifdef USART0_MPCM_MODE
+	static inline void uart0_mpcm_slave_return_idle(void) __attribute__((always_inline));
+	static inline void uart0_mpcm_slave_return_idle(void) // return slave to mpcm idle mode (wait for own addres frame)
+	{
+		UCSR0A_REGISTER |= (1<<MPCM0_BIT);
+	}
+#endif
+
+#ifdef USART0_HARDWARE_FLOW_CONTROL_AVAILABLE
+	void uart0_hardware_flow_control_init(uint8_t ctsenable, uint8_t rtsenable) __attribute__((always_inline));
+	void uart0_hardware_flow_control_init(uint8_t ctsenable, uint8_t rtsenable) // pass true to enable
+	{
+		if(ctsenable && rtsenable) // -Os dependent, do not use in non-inline functions 
+			UCSR0D_REGISTER = (1<<CTSEN0_BIT)|(1<<RTSEN0_BIT);
+		else if(ctsenable)
+			UCSR0D_REGISTER = (1<<CTSEN0_BIT);
+		else
+			UCSR0D_REGISTER = (1<<RTSEN0_BIT);
+	}
+	#define uart_hardware_flow_control_init(__ctsenable, __rtsenable) uart0_hardware_flow_control_init(__ctsenable, __rtsenable)
+#endif
+	
+	#define uart_init(__ubrr) uart0_init(__ubrr)
+	#define uart_reinit(__ubrr) uart0_reinit(__ubrr)
+	#define uart_set_FrameFormat(__ucsrc) uart0_set_FrameFormat(__ucsrc)
+	#define uart_set_U2X() uart0_set_U2X()
+	#define uart_mpcm_slave_return_idle() uart0_mpcm_slave_return_idle()
+#endif // USE_USART0
+
+#ifdef USE_USART1
+	void uart1_reinit(uint16_t ubrr_value); // for runtime reinitialization of uart
+	
+	static inline void uart1_init(uint16_t ubrr_value) __attribute__((always_inline));
+	static inline void uart1_init(uint16_t ubrr_value) // have to be called once at startup
+	{
+	#ifdef USART1_RS485_MODE
+		RS485_CONTROL1_DDR |= (1<<RS485_CONTROL1_IONUM); // default pin state is low
+	#endif
+		
+		UBRR1L_REGISTER = (uint8_t) ubrr_value;
+		
+	#ifdef USART_SKIP_UBRRH_IF_ZERO
+		if(__builtin_constant_p(ubrr_value))
+			if(((ubrr_value>>8) != 0)) // requires -Os flag - do not use in non-inline functions
+	#endif
+			UBRR1H_REGISTER = (ubrr_value>>8);
+		
+	#ifdef USART1_U2X_SPEED
+		#ifdef USART1_MPCM_MODE
+			UCSR1A_REGISTER = (1<<U2X1_BIT)|(1<<MPCM1_BIT);
+		#else
+			UCSR1A_REGISTER = (1<<U2X1_BIT); // enable double speed
+		#endif
+	#elif defined(USART1_MPCM_MODE)
+		UCSR1A_REGISTER |= (1<<MPCM1_BIT);
+	#endif
+		
+		UCSR1B_REGISTER = USART1_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART1_USE_SOFT_RTS
+		RTS1_DDR |= (1<<RTS1_IONUM);
+	#endif
+	}
+
+	static inline void uart1_set_FrameFormat(uint8_t UCSRC_reg) __attribute__((always_inline));
+	static inline void uart1_set_FrameFormat(uint8_t UCSRC_reg) // UCSRC_reg can be used to set other than 8n1 transmission
+	{
+		UCSR1C_REGISTER = UCSRC_reg;
+	} 
+	
+	static inline void uart1_set_U2X(void) __attribute__((always_inline));
+	static inline void uart1_set_U2X(void) // use instead of USE_DOUBLE_SPEED 
+	{
+		UCSR1A_REGISTER |= (1<<U2X1_BIT);
+	} 
+
+#ifdef USART1_MPCM_MODE
+	static inline void uart1_mpcm_slave_return_idle(void) __attribute__((always_inline));
+	static inline void uart1_mpcm_slave_return_idle(void) // return slave to mpcm idle mode (wait for own addres frame)
+	{
+		UCSR1A_REGISTER |= (1<<MPCM1_BIT);
+	}
+#endif
+
+#ifdef USART1_HARDWARE_FLOW_CONTROL_AVAILABLE
+	static inline void uart1_hardware_flow_control_init(uint8_t ctsenable, uint8_t rtsenable) __attribute__((always_inline));
+	static inline void uart1_hardware_flow_control_init(uint8_t ctsenable, uint8_t rtsenable) // pass true to enable
+	{
+		if(ctsenable && rtsenable) // -Os dependent, do not use in non-inline functions 
+			UCSR1D_REGISTER = (1<<CTSEN1_BIT)|(1<<RTSEN1_BIT);
+		else if(ctsenable)
+			UCSR1D_REGISTER = (1<<CTSEN1_BIT);
+		else
+			UCSR1D_REGISTER = (1<<RTSEN1_BIT);
+	}
+#endif
+
+#endif // USE_USART1
+
+#ifdef USE_USART2
+	void uart2_reinit(uint16_t ubrr_value); // for runtime reinitialization of uart
+	
+	static inline void uart2_init(uint16_t ubrr_value) __attribute__((always_inline));
+	static inline void uart2_init(uint16_t ubrr_value) // have to be called once at startup
+	{
+	#ifdef USART2_RS485_MODE
+		RS485_CONTROL2_DDR |= (1<<RS485_CONTROL2_IONUM); // default pin state is low
+	#endif
+		
+		UBRR2L_REGISTER = (uint8_t) ubrr_value;
+		
+	#ifdef USART_SKIP_UBRRH_IF_ZERO
+		if(__builtin_constant_p(ubrr_value))
+			if(((ubrr_value>>8) != 0)) // requires -Os flag - do not use in non-inline functions
+	#endif
+			UBRR2H_REGISTER = (ubrr_value>>8);
+		
+	#ifdef USART2_U2X_SPEED
+		#ifdef USART2_MPCM_MODE
+			UCSR2A_REGISTER = (1<<U2X2_BIT)|(1<<MPCM2_BIT);
+		#else
+			UCSR2A_REGISTER = (1<<U2X2_BIT); // enable double speed
+		#endif
+	#elif defined(USART2_MPCM_MODE)
+		UCSR2A_REGISTER |= (1<<MPCM2_BIT);
+	#endif
+		
+		UCSR2B_REGISTER = USART2_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART2_USE_SOFT_RTS
+		RTS2_DDR |= (1<<RTS2_IONUM);
+	#endif
+	}
+
+	static inline void uart2_set_FrameFormat(uint8_t UCSRC_reg) __attribute__((always_inline));
+	static inline void uart2_set_FrameFormat(uint8_t UCSRC_reg) // UCSRC_reg can be used to set other than 8n1 transmission
+	{
+		UCSR2C_REGISTER = UCSRC_reg;
+	} 
+	
+	static inline void uart2_set_U2X(void) __attribute__((always_inline));
+	static inline void uart2_set_U2X(void) // use instead of USE_DOUBLE_SPEED 
+	{
+		UCSR2A_REGISTER |= (1<<U2X2_BIT);
+	} 
+
+#ifdef USART2_MPCM_MODE
+	static inline void uart2_mpcm_slave_return_idle(void) __attribute__((always_inline));
+	static inline void uart2_mpcm_slave_return_idle(void) // return slave to mpcm idle mode (wait for own addres frame)
+	{
+		UCSR2A_REGISTER |= (1<<MPCM2_BIT);
+	}
+#endif
+#endif // USE_USART2
+
+#ifdef USE_USART3
+	void uart3_reinit(uint16_t ubrr_value); // for runtime reinitialization of uart
+	
+	static inline void uart3_init(uint16_t ubrr_value) __attribute__((always_inline));
+	static inline void uart3_init(uint16_t ubrr_value) // have to be called once at startup
+	{
+	#ifdef USART3_RS485_MODE
+		RS485_CONTROL3_DDR |= (1<<RS485_CONTROL3_IONUM); // default pin state is low
+	#endif
+		
+		UBRR3L_REGISTER = (uint8_t) ubrr_value;
+		
+	#ifdef USART_SKIP_UBRRH_IF_ZERO
+		if(__builtin_constant_p(ubrr_value))
+			if(((ubrr_value>>8) != 0)) // requires -Os flag - do not use in non-inline functions
+	#endif
+			UBRR3H_REGISTER = (ubrr_value>>8);
+		
+	#ifdef USART3_U2X_SPEED
+		#ifdef USART3_MPCM_MODE
+			UCSR3A_REGISTER = (1<<U2X3_BIT)|(1<<MPCM3_BIT);
+		#else
+			UCSR3A_REGISTER = (1<<U2X3_BIT); // enable double speed
+		#endif
+	#elif defined(USART3_MPCM_MODE)
+		UCSR3A_REGISTER |= (1<<MPCM3_BIT);
+	#endif
+		
+		UCSR3B_REGISTER = USART3_CONFIG_B;
+		// 8n1 is set by default, setting UCSRC is not needed
+		
+	#ifdef USART3_USE_SOFT_RTS
+		RTS3_DDR |= (1<<RTS3_IONUM);
+	#endif
+	}
+
+	static inline void uart3_set_FrameFormat(uint8_t UCSRC_reg) __attribute__((always_inline));
+	static inline void uart3_set_FrameFormat(uint8_t UCSRC_reg) // UCSRC_reg can be used to set other than 8n1 transmission
+	{
+		UCSR3C_REGISTER = UCSRC_reg;
+	} 
+	
+	static inline void uart3_set_U2X(void) __attribute__((always_inline));
+	static inline void uart3_set_U2X(void) // use instead of USE_DOUBLE_SPEED 
+	{
+		UCSR3A_REGISTER |= (1<<U2X3_BIT);
+	} 
+
+#ifdef USART3_MPCM_MODE
+	static inline void uart3_mpcm_slave_return_idle(void) __attribute__((always_inline));
+	static inline void uart3_mpcm_slave_return_idle(void) // return slave to mpcm idle mode (wait for own addres frame)
+	{
+		UCSR3A_REGISTER |= (1<<MPCM3_BIT);
+	}
+#endif
+#endif // USE_USART3
+	
+/************************************************************************************
+ *                              Transmitter functions                               *
+ ************************************************************************************/
+#ifndef NO_USART_TX
+	
+	#ifndef NO_TX0_INTERRUPT
+		#ifdef USART_NO_ABI_BREAKING_PREMATURES
+			void uart0_putc(char data);
+			inline char uart0_putc_(char data) __attribute__ ((always_inline));
+			inline char uart0_putc_(char data) { uart0_putc(data); return data; }
+		#else
+			void uart0_putc(char data) __attribute__ ((naked, noinline));
+			char uart0_putc_(char data) __attribute__ ((noinline)); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+		#endif
+		
+		uint8_t uart0_putc_noblock(char data); // returns BUFFER_FULL (false) if buffer is full and character cannot be sent at the moment
+	
+		void uart0_putstr(char *string); // send string from the memory buffer // stops when NULL byte is hit (NULL byte is not included into transmission)
+		void uart0_putstrl(char *string, uint8_t BytesToWrite); // send specified number of bytes from the pointed buffer (up to 255 bytes)
+		
+		#ifdef __cplusplus
+			#define uart0_puts(str) uart0_putstr((const char*)(str))// macro to avoid const char* conversion restrictions
+		#else
+			#define uart0_puts(str) uart0_putstr(str)
+		#endif
+			// for deprecated usage only (wastes SRAM data memory to keep all string constants), instead of this try to use puts_P
+	
+		#ifdef __cplusplus
+			void uart0_puts_p(const char *string); // send string from flash memory
+		#else
+			void uart0_puts_p(const __flash char *string); // send string from flash memory
+		#endif
+			#define uart0_puts_P(__strP) uart0_puts_p(PSTR(__strP))
+			// macro to automatically put a string constant into flash
+	
+		void uart0_putint(int16_t data);
+		void uart0_putintr(int16_t data, uint8_t radix);
+
+		void uart0_putuint(uint16_t data);
+		void uart0_putuintr(uint16_t data, uint8_t radix);
+	
+		void uart0_puthex(uint8_t data);
+
+		void uart0_putlong(int32_t data);
+		void uart0_putlongr(int32_t data, uint8_t radix);
+
+		void uart0_putulong(uint32_t data);
+		void uart0_putulongr(uint32_t data, uint8_t radix);
+	
+		void uart0_putfloat(float data);
+		void uart0_fputfloat(float data, uint8_t precision);
+	
+		void uart0_flush(void); // flush tx buffer
+		
+		extern volatile uint8_t tx0_Head, tx0_Tail;
+		inline uint8_t uart0_BytesToSend(void) { return (tx0_Head - tx0_Tail - 1) & TX0_BUFFER_MASK; }
+		// returns number of bytes waiting in the transmit buffer
+	
+		#ifdef USART0_MPCM_MODE
+			void uart0_mpcm_transmit_addres_Frame(uint8_t dat);
+		#endif
+		
+		#define uart_putc(__data) uart0_putc(__data)
+		#define uart_putc_(__data) uart0_putc_(__data)
+		#define uart_putc_noblock(__data) uart0_putc_noblock(__data)
+		#define uart_putstrl(__str, __limit) uart0_putstrl(__str, __limit)
+		#define uart_putstr(__str) uart0_putstr(__str)
+		#define uart_puts(__str) uart0_puts(__str)
+		#define uart_puts_p(__strP) uart0_puts_p(__strP)
+		#define uart_puts_P(__str) uart0_puts_P(__str)
+		#define uart_putint(__data) uart0_putint(__data)
+		#define uart_putintr(__data, __radix) uart0_putintr(__data, __radix)
+		#define uart_putuint(__data) uart0_putuint(__data)
+		#define uart_putuintr(__data, __radix) uart0_putuintr(__data, __radix)
+		#define uart_puthex(__data) uart0_puthex(__data)
+		#define uart_putlong(__data) uart0_putlong(__data)
+		#define uart_putlongr(__data, __radix) uart0_putlongr(__data, __radix)
+		#define uart_putulong(__data) uart0_putulong(__data)
+		#define uart_putulongr(__data, __radix) uart0_putulongr(__data, __radix)
+		#define uart_putfloat(__data) uart0_putfloat(__data)
+		#define uart_fputfloat(__data, __precision) uart0_fputfloat(__data, __precision)
+		#define uart_flush() uart0_flush()
+		
+		#ifdef USART0_MPCM_MODE
+			#define uart_mpcm_transmit_addres_Frame(__data) uart0_mpcm_transmit_addres_Frame(__data)
+		#endif
+	#endif // NO_TX0_INTERRUPT
+	
+	#ifndef NO_TX1_INTERRUPT
+		#ifdef USART_NO_ABI_BREAKING_PREMATURES
+			void uart1_putc(char data);
+			inline char uart1_putc_(char data) __attribute__ ((always_inline));
+			inline char uart1_putc_(char data) { uart1_putc(data); return data; }
+		#else
+			void uart1_putc(char data) __attribute__ ((naked, noinline));
+			char uart1_putc_(char data) __attribute__ ((noinline)); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+		#endif
+		
+		uint8_t uart1_putc_noblock(char data); // returns BUFFER_FULL (false) if buffer is full and character cannot be sent at the moment
+	
+		void uart1_putstr(char *string); // send string from the memory buffer // stops when NULL byte is hit (NULL byte is not included into transmission)
+		void uart1_putstrl(char *string, uint8_t BytesToWrite); // send specified number of bytes from the pointed buffer (up to 255 bytes)
+		
+		#ifdef __cplusplus
+			#define uart1_puts(str) uart1_putstr((const char*)(str))// macro to avoid const char* conversion restrictions
+		#else
+			#define uart1_puts(str) uart1_putstr(str)
+		#endif
+			// for deprecated usage only (wastes SRAM data memory to keep all string constants), instead of this try to use puts_P
+
+		#ifdef __cplusplus
+			void uart1_puts_p(const char *string); // send string from flash memory
+		#else	
+			void uart1_puts_p(const __flash char *string); // send string from flash memory
+		#endif
+			#define uart1_puts_P(__s)    uart1_puts_p(PSTR(__s))
+			// macro to automatically put a string constant into flash
+	
+		void uart1_putint(int16_t data);
+		void uart1_putintr(int16_t data, uint8_t radix);
+
+		void uart1_putuint(uint16_t data);
+		void uart1_putuintr(uint16_t data, uint8_t radix);
+	
+		void uart1_puthex(uint8_t data);
+
+		void uart1_putlong(int32_t data);
+		void uart1_putlongr(int32_t data, uint8_t radix);
+
+		void uart1_putulong(uint32_t data);
+		void uart1_putulongr(uint32_t data, uint8_t radix);
+	
+		void uart1_putfloat(float data);
+		void uart1_fputfloat(float data, uint8_t precision);
+	
+		void uart1_flush(void); // flush tx buffer
+		
+		extern volatile uint8_t tx1_Head, tx1_Tail;
+		inline uint8_t uart1_BytesToSend(void) { return (tx1_Head - tx1_Tail - 1) & TX1_BUFFER_MASK; }
+		// returns number of bytes waiting in the transmit buffer
+	
+		#ifdef USART1_MPCM_MODE
+			void uart1_mpcm_transmit_addres_Frame(uint8_t dat);
+		#endif
+	#endif // NO_TX1_INTERRUPT
+	
+	#ifndef NO_TX2_INTERRUPT
+		#ifdef USART_NO_ABI_BREAKING_PREMATURES
+			void uart2_putc(char data);
+			inline char uart2_putc_(char data) __attribute__ ((always_inline));
+			inline char uart2_putc_(char data) { uart2_putc(data); return data; }
+		#else
+			void uart2_putc(char data) __attribute__ ((naked, noinline));
+			char uart2_putc_(char data) __attribute__ ((noinline)); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+		#endif
+		
+		uint8_t uart2_putc_noblock(char data); // returns BUFFER_FULL (false) if buffer is full and character cannot be sent at the moment
+	
+		void uart2_putstr(char *string); // send string from the memory buffer // stops when NULL byte is hit (NULL byte is not included into transmission)
+		void uart2_putstrl(char *string, uint8_t BytesToWrite); // send specified number of bytes from the pointed buffer (up to 255 bytes)
+		
+		#ifdef __cplusplus
+			#define uart2_puts(str) uart2_putstr((const char*)(str)) // macro to avoid const char* conversion restrictions
+		#else
+			#define uart2_puts(str) uart2_putstr(str)
+		#endif
+			// for deprecated usage only (wastes SRAM data memory to keep all string constants), instead of this try to use puts_P
+
+		#ifdef __cplusplus
+			void uart2_puts_p(const char *string); // send string from flash memory
+		#else
+			void uart2_puts_p(const __flash char *string); // send string from flash memory
+		#endif
+			#define uart2_puts_P(__s)    uart2_puts_p(PSTR(__s))
+			// macro to automatically put a string constant into flash
+	
+		void uart2_putint(int16_t data);
+		void uart2_putintr(int16_t data, uint8_t radix);
+
+		void uart2_putuint(uint16_t data);
+		void uart2_putuintr(uint16_t data, uint8_t radix);
+	
+		void uart2_puthex(uint8_t data);
+
+		void uart2_putlong(int32_t data);
+		void uart2_putlongr(int32_t data, uint8_t radix);
+
+		void uart2_putulong(uint32_t data);
+		void uart2_putulongr(uint32_t data, uint8_t radix);
+	
+		void uart2_putfloat(float data);
+		void uart2_fputfloat(float data, uint8_t precision);
+	
+		void uart2_flush(void); // flush tx buffer
+		
+		extern volatile uint8_t tx2_Head, tx2_Tail;
+		inline uint8_t uart2_BytesToSend(void) { return (tx2_Head - tx2_Tail - 1) & TX2_BUFFER_MASK; }
+		// returns number of bytes waiting in the transmit buffer	
+	
+		#ifdef USART2_MPCM_MODE
+			void uart2_mpcm_transmit_addres_Frame(uint8_t dat);
+		#endif
+	#endif // NO_TX2_INTERRUPT
+	
+	#ifndef NO_TX3_INTERRUPT
+		#ifdef USART_NO_ABI_BREAKING_PREMATURES
+			void uart3_putc(char data);
+			inline char uart3_putc_(char data) __attribute__ ((always_inline));
+			inline char uart3_putc_(char data) { uart3_putc(data); return data; }
+		#else
+			void uart3_putc(char data) __attribute__ ((naked, noinline));
+			char uart3_putc_(char data) __attribute__ ((noinline)); // alias for uart_putc that returns passed argument unaffected by omitting any existent rule
+		#endif
+		
+		uint8_t uart3_putc_noblock(char data); // returns BUFFER_FULL (false) if buffer is full and character cannot be sent at the moment
+	
+		void uart3_putstr(char *string); // send string from the memory buffer // stops when NULL byte is hit (NULL byte is not included into transmission)
+		void uart3_putstrl(char *string, uint8_t BytesToWrite); // send specified number of bytes from the pointed buffer (up to 255 bytes)
+		
+		#ifdef __cplusplus
+			#define uart3_puts(str) uart3_putstr((const char*)(str))// macro to avoid const char* conversion restrictions
+		#else
+			#define uart3_puts(str) uart3_putstr(str)
+		#endif
+			// for deprecated usage only (wastes SRAM data memory to keep all string constants), instead of this try to use puts_P
+
+		#ifdef __cplusplus
+			void uart3_puts_p(const char *string); // send string from flash memory
+		#else
+			void uart3_puts_p(const __flash char *string); // send string from flash memory
+		#endif
+			#define uart3_puts_P(__s)    uart3_puts_p(PSTR(__s))
+			// macro to automatically put a string constant into flash
+	
+		void uart3_putint(int16_t data);
+		void uart3_putintr(int16_t data, uint8_t radix);
+
+		void uart3_putuint(uint16_t data);
+		void uart3_putuintr(uint16_t data, uint8_t radix);
+	
+		void uart3_puthex(uint8_t data);
+
+		void uart3_putlong(int32_t data);
+		void uart3_putlongr(int32_t data, uint8_t radix);
+
+		void uart3_putulong(uint32_t data);
+		void uart3_putulongr(uint32_t data, uint8_t radix);
+	
+		void uart3_putfloat(float data);
+		void uart3_fputfloat(float data, uint8_t precision);
+	
+		void uart3_flush(void); // flush tx buffer
+		
+		extern volatile uint8_t tx3_Head, tx3_Tail;
+		inline uint8_t uart3_BytesToSend(void) { return (tx3_Head - tx3_Tail - 1) & TX3_BUFFER_MASK; }
+		// returns number of bytes waiting in the transmit buffer
+	
+		#ifdef USART3_MPCM_MODE
+			void uart3_mpcm_transmit_addres_Frame(uint8_t dat);
+		#endif
+	#endif // NO_TX0_INTERRUPT
+
+#endif // NO_USART_TX
+
+/************************************************************************************
+ *                                Receiver functions                                *
+ ************************************************************************************/
+#ifndef NO_USART_RX
+	
+	#ifndef NO_RX0_INTERRUPT
+		char uart0_getc(void); // get character from receiver ring buffer
+	
+		void uart0_gets(char *buffer, uint8_t bufferlimit); // reads whole receiver buffer or bufferlimit-1 characters
+		// newline terminator will not be cut // adds NULL byte at the end of string
+		void uart0_getln(char *buffer, uint8_t bufferlimit); // reads one line from the buffer
+		// waits for newline terminator or reached bufferlimit // adds NULL byte at the end of string
+		void uart0_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit); // read one line to the first whitespace after the string
+		// cuts all whitespaces before string and one after the string
+	
+		inline char uart0_skipWhiteSpaces(void) { char c; do{ c = uart0_getc(); }while(c <= 32); return c; }
+		// returns first nonspace character found in the buffer
+		
+		int16_t uart0_getint(void);
+		int32_t uart0_getlong(void);
+		float uart0_getfloat(void);
+	
+		int16_t uart0_getData(void); // reads single byte from a buffer // returns negative value if buffer is empty (upper byte is non zero)
+		uint8_t uart0_LoadData(uint8_t *data); // reads single byte from a buffer and loads it into *data byte
+		// in case of empty buffers returned flag is set to BUFFER_EMPTY - NULL
+		
+		extern volatile uint8_t rx0_Head, rx0_Tail;
+		inline uint8_t uart0_AvailableBytes(void) { return (rx0_Head - rx0_Tail) & RX0_BUFFER_MASK; }
+		// returns number of bytes waiting in the receiver buffer
+		
+		uint8_t uart0_peek(void); // returns next byte from buffer // returned byte is invalid if there is nothing to read
+		
+		#define uart_getc() uart0_getc()
+		#define uart_gets(__buffptr, __limit) uart0_gets(__buffptr, __limit)
+		#define uart_getln(__buffptr, __limit) uart0_getln(__buffptr, __limit)
+		#define uart_getlnToFirstWhiteSpace(__buffptr, __limit) uart0_getlnToFirstWhiteSpace(__buffptr, __limit)
+		#define uart_skipWhiteSpaces() uart0_skipWhiteSpaces()
+		#define uart_getint() uart0_getint()
+		#define uart_getlong() uart0_getlong()
+		#define uart_getfloat() uart0_getfloat()
+		#define uart_getData() uart0_getData()
+		#define uart_LoadData(__dataptr) uart0_LoadData(__dataptr)
+		#define uart_AvailableBytes() uart0_AvailableBytes()
+		#define uart_peek() uart0_peek()
+	#endif // NO_RX0_INTERRUPT
+	
+	#ifndef NO_RX1_INTERRUPT
+		char uart1_getc(void); // get character from receiver ring buffer
+		
+		void uart1_gets(char *buffer, uint8_t bufferlimit); // reads whole receiver buffer or bufferlimit-1 characters
+		// newline terminator will not be cut // adds NULL byte at the end of string
+		void uart1_getln(char *buffer, uint8_t bufferlimit); // reads one line from the buffer
+		// waits for newline terminator or reached bufferlimit // adds NULL byte at the end of string
+		void uart1_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit); // read one line to the first whitespace after the string
+		// cuts all whitespaces before string and one after the string
+		
+		inline char uart1_skipWhiteSpaces(void) { char c; do{ c = uart1_getc(); }while(c <= 32); return c; }
+		// returns first nonspace character found in the buffer
+		
+		int16_t uart1_getint(void);
+		int32_t uart1_getlong(void);
+		float uart1_getfloat(void);
+		
+		int16_t uart1_getData(void); // reads single byte from a buffer // returns negative value if buffer is empty (upper byte is non zero)
+		uint8_t uart1_LoadData(uint8_t *data); // reads single byte from a buffer and loads it into *data byte
+		// in case of empty buffers returned flag is set to BUFFER_EMPTY - NULL
+		
+		extern volatile uint8_t rx1_Head, rx1_Tail;
+		inline uint8_t uart1_AvailableBytes(void) { return (rx1_Head - rx1_Tail) & RX1_BUFFER_MASK; }
+		// returns number of bytes waiting in the receiver buffer
+		
+		uint8_t uart1_peek(void); // returns next byte from buffer // returned byte is invalid if there is nothing to read
+	#endif // NO_RX0_INTERRUPT
+	
+	#ifndef NO_RX2_INTERRUPT
+		char uart2_getc(void); // get character from receiver ring buffer
+		
+		void uart2_gets(char *buffer, uint8_t bufferlimit); // reads whole receiver buffer or bufferlimit-1 characters
+		// newline terminator will not be cut // adds NULL byte at the end of string
+		void uart2_getln(char *buffer, uint8_t bufferlimit); // reads one line from the buffer
+		// waits for newline terminator or reached bufferlimit // adds NULL byte at the end of string
+		void uart2_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit); // read one line to the first whitespace after the string
+		// cuts all whitespaces before string and one after the string
+		
+		inline char uart2_skipWhiteSpaces(void) { char c; do{ c = uart2_getc(); }while(c <= 32); return c; }
+		// returns first nonspace character found in the buffer
+		
+		int16_t uart2_getint(void);
+		int32_t uart2_getlong(void);
+		float uart2_getfloat(void);
+		
+		int16_t uart2_getData(void); // reads single byte from a buffer // returns negative value if buffer is empty (upper byte is non zero)
+		uint8_t uart2_LoadData(uint8_t *data); // reads single byte from a buffer and loads it into *data byte
+		// in case of empty buffers returned flag is set to BUFFER_EMPTY - NULL
+		
+		extern volatile uint8_t rx2_Head, rx2_Tail;
+		inline uint8_t uart2_AvailableBytes(void) { return (rx2_Head - rx2_Tail) & RX2_BUFFER_MASK; }
+		// returns number of bytes waiting in the receiver buffer
+		
+		uint8_t uart2_peek(void); // returns next byte from buffer // returned byte is invalid if there is nothing to read
+	#endif // NO_RX0_INTERRUPT
+	
+	#ifndef NO_RX3_INTERRUPT
+		char uart3_getc(void); // get character from receiver ring buffer
+		
+		void uart3_gets(char *buffer, uint8_t bufferlimit); // reads whole receiver buffer or bufferlimit-1 characters
+		// newline terminator will not be cut // adds NULL byte at the end of string
+		void uart3_getln(char *buffer, uint8_t bufferlimit); // reads one line from the buffer
+		// waits for newline terminator or reached bufferlimit // adds NULL byte at the end of string
+		void uart3_getlnToFirstWhiteSpace(char *buffer, uint8_t bufferlimit); // read one line to the first whitespace after the string
+		// cuts all whitespaces before string and one after the string
+		
+		inline char uart3_skipWhiteSpaces(void) { char c; do{ c = uart3_getc(); }while(c <= 32); return c; } 
+		// returns first nonspace character found in the buffer
+		
+		int16_t uart3_getint(void);
+		int32_t uart3_getlong(void);
+		float uart3_getfloat(void);
+		
+		int16_t uart3_getData(void); // reads single byte from a buffer // returns negative value if buffer is empty (upper byte is non zero)
+		uint8_t uart3_LoadData(uint8_t *data); // reads single byte from a buffer and loads it into *data byte
+		// in case of empty buffers returned flag is set to BUFFER_EMPTY - NULL
+		
+		extern volatile uint8_t rx3_Head, rx3_Tail;
+		inline uint8_t uart3_AvailableBytes(void) { return (rx3_Head - rx3_Tail) & RX3_BUFFER_MASK; }
+		// returns number of bytes waiting in the receiver buffer
+		
+		uint8_t uart3_peek(void); // returns next byte from buffer // returned byte is invalid if there is nothing to read
+	#endif // NO_RX0_INTERRUPT
+
+#endif // NO_USART_RX
+
+/************************************************************************************
+ *                       soft flow control interrupt handlers                       *
+ ************************************************************************************/
+
+#if defined(USART0_USE_SOFT_CTS)&&!defined(NO_TX0_INTERRUPT)
+	extern volatile uint8_t tx0_Tail, tx0_Head;
+
+	static inline void cts0_isr_handler(void) __attribute__((always_inline));
+	static inline void cts0_isr_handler(void)
+	{
+	#if defined(USART0_IN_IO_ADDRESS_SPACE)
+		if(CTS0_PIN & (1<<CTS0_IONUM))
+		{
+			UCSR0B_REGISTER &= ~(1<<UDRIE0_BIT);
+		}
+		else if (tx0_Tail != tx0_Head)
+		{
+			UCSR0B_REGISTER |= (1<<UDRIE0_BIT);
+		}
+	#else
+		uint8_t tmp = UCSR0B_REGISTER;
+		if(CTS0_PIN & (1<<CTS0_IONUM))
+		{
+			tmp &= ~(1<<UDRIE0_BIT);
+		}
+		else if (tx0_Tail != tx0_Head)
+		{
+			tmp |= (1<<UDRIE0_BIT);
+		}
+		UCSR0B_REGISTER = tmp;
+	#endif
+	}
+	
+	static inline void naked_cts0_isr_handler(void) __attribute__((always_inline));
+	static inline void naked_cts0_isr_handler(void)
+	{
+		asm volatile("\n\t"
+		
+		#if defined(USART0_IN_IO_ADDRESS_SPACE)
+			"cbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"reti \n\t"
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			
+			"lds %B[z_save], (tx0_Tail) \n\t"
+			"lds %A[z_save], (tx0_Head) \n\t"
+			"cpse %B[z_save], %A[z_save] \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			
+		#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
+			
+			"push r25 \n\t"
+			
+			"lds r25, (tx0_Tail) \n\t"
+			"lds %[sreg_save], (tx0_Head) \n\t"
+			"cpse r25, %[sreg_save] \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			
+			"pop r25 \n\t"
+		#else
+			"push r24 \n\t"
+			"push r25 \n\t"
+		
+			"lds r25, (tx0_Tail) \n\t"
+			"lds r24, (tx0_Head) \n\t"
+			"cpse r25, r24 \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+		
+			"pop r25 \n\t"
+			"pop r24 \n\t"
+		#endif
+
+			"reti \n\t"
+			
+		#else // USART not in IO
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"in %[sreg_save], __SREG__ \n\t"
+		#else
+			"push r16 \n\t"
+			"in r16,__SREG__ \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			#ifdef __AVR_HAVE_MOVW__
+				"movw %[z_save], r24 \n\t"
+			#else // in this case only 4 cycles are prematured out
+				"mov %A[z_save], r24 \n\t"
+				"mov %B[z_save], r25 \n\t"
+			#endif
+		#else
+			"push r24 \n\t"
+		#endif
+		
+		#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
+			"in r24, %M[UCSRB_reg_IO] \n\t"
+		#else
+			"lds r24, %M[UCSRB_reg] \n\t"
+		#endif
+			
+			"andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
+			"sbic %M[cts_port], %M[cts_pin]\n\t"
+			"rjmp cts_apply_%= \n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r25 \n\t"
+		#endif
+			"lds r24, (tx0_Head) \n\t"
+			"lds r25, (tx0_Tail) \n\t"
+			"cp r25, r24 \n\t"
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r25 \n\t" // branch after poping
+		#endif
+			"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case - no need to clear it
+		
+		#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
+			"in r24, %M[UCSRB_reg_IO] \n\t"
+		#else
+			"lds r24, %M[UCSRB_reg] \n\t"
+		#endif
+			"ori r24, (1<<%M[UDRIE_bit]) \n\t"
+			
+		"cts_apply_%=:"	
+		#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
+			"out %M[UCSRB_reg_IO], r24 \n\t"
+		#else
+			"sts %M[UCSRB_reg], r24 \n\t"
+		#endif
+		
+		"cts_exit_%=:"
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			#ifdef __AVR_HAVE_MOVW__
+				"movw r24, %[z_save] \n\t"
+			#else // in this case only 4 cycles are prematured out
+				"mov r25, %B[z_save] \n\t"
+				"mov r24, %A[z_save] \n\t"
+			#endif
+		#else
+			"pop r24 \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, %[sreg_save] \n\t"
+		#else
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#endif
+		
+			"reti \n\t"
+		#endif
+			: /* output operands */
+			USART_REG_SAVE_LIST
+			: /* input operands */
+			[UCSRB_reg]      "n" (_SFR_MEM_ADDR(UCSR0B_REGISTER)),
+			[UCSRB_reg_IO]   "M" (_SFR_IO_ADDR(UCSR0B_REGISTER)),
+			[UDRIE_bit]      "M" (UDRIE0_BIT),
+			[cts_port]       "M" (_SFR_IO_ADDR(CTS0_PIN)),
+			[cts_pin]        "M" (CTS0_IONUM)
+			: /* clobbers */
+		);
+	}
+#endif
+
+#if defined(USART1_USE_SOFT_CTS)&&!defined(NO_TX1_INTERRUPT)
+	extern volatile uint8_t tx1_Tail, tx1_Head;
+
+	static inline void cts1_isr_handler(void) __attribute__((always_inline));
+	static inline void cts1_isr_handler(void)
+	{
+	#if defined(USART1_IN_IO_ADDRESS_SPACE)
+		if(CTS1_PIN & (1<<CTS1_IONUM))
+		{
+			UCSR1B_REGISTER &= ~(1<<UDRIE1_BIT);
+		}
+		else if (tx1_Tail != tx1_Head)
+		{
+			UCSR1B_REGISTER |= (1<<UDRIE1_BIT);
+		}
+	#else
+		uint8_t tmp = UCSR1B_REGISTER;
+		if(CTS1_PIN & (1<<CTS1_IONUM))
+		{
+			tmp &= ~(1<<UDRIE1_BIT);
+		}
+		else if (tx1_Tail != tx1_Head)
+		{
+			tmp |= (1<<UDRIE1_BIT);
+		}
+		UCSR1B_REGISTER = tmp;
+	#endif
+	}
+	
+	static inline void naked_cts1_isr_handler(void) __attribute__((always_inline));
+	static inline void naked_cts1_isr_handler(void)
+	{
+		asm volatile("\n\t"
+		
+		#if defined(USART1_IN_IO_ADDRESS_SPACE)
+			"cbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			"sbic %M[cts_port], %M[cts_pin] \n\t"
+			"reti \n\t"
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			
+			"lds %B[z_save], (tx1_Tail) \n\t"
+			"lds %A[z_save], (tx1_Head) \n\t"
+			"cpse %B[z_save], %A[z_save] \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			
+		#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
+			
+			"push r25 \n\t"
+			
+			"lds r25, (tx1_Tail) \n\t"
+			"lds %[sreg_save], (tx1_Head) \n\t"
+			"cpse r25, %[sreg_save] \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+			
+			"pop r25 \n\t"
+		#else
+			"push r24 \n\t"
+			"push r25 \n\t"
+		
+			"lds r25, (tx1_Tail) \n\t"
+			"lds r24, (tx1_Head) \n\t"
+			"cpse r25, r24 \n\t"
+			"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t"
+		
+			"pop r25 \n\t"
+			"pop r24 \n\t"
+		#endif
+		
+			"reti \n\t"
+		
+		#else // USART not in IO
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"in %[sreg_save], __SREG__ \n\t"
+		#else
+			"push r16 \n\t"
+			"in r16,__SREG__ \n\t"
+		#endif
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"movw %[z_save], r24 \n\t"
+		#else
+			"push r24 \n\t"
+		#endif
+			
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
+			"sbic %M[cts_port], %M[cts_pin]\n\t"
+			"rjmp cts_apply_%= \n\t"
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r25 \n\t"
+		#endif
+			"lds r24, (tx1_Head) \n\t"
+			"lds r25, (tx1_Tail) \n\t"
+			"cp r25, r24 \n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r25 \n\t"
+		#endif
+			"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case - no need to clear it
+			
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"ori r24, (1<<%M[UDRIE_bit]) \n\t"
+		"cts_apply_%=:"	
+			"sts %M[UCSRB_reg], r24 \n\t"
+		
+		"cts_exit_%=:"
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE	
+			"movw r24, %[z_save] \n\t"
+		#else
+			"pop r24 \n\t"
+		#endif
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, %[sreg_save] \n\t"
+		#else
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#endif
+
+			"reti \n\t"
+		#endif
+			: /* output operands */
+			USART_REG_SAVE_LIST
+			: /* input operands */
+			[UCSRB_reg]      "n" (_SFR_MEM_ADDR(UCSR1B_REGISTER)),
+			[UCSRB_reg_IO]   "M" (_SFR_IO_ADDR(UCSR1B_REGISTER)),
+			[UDRIE_bit]      "M" (UDRIE1_BIT),
+			[cts_port]       "M" (_SFR_IO_ADDR(CTS1_PIN)),
+			[cts_pin]        "M" (CTS1_IONUM)
+			: /* clobbers */
+		);
+	}
+#endif
+
+#if defined(USART2_USE_SOFT_CTS)&&!defined(NO_TX2_INTERRUPT)
+	extern volatile uint8_t tx2_Tail, tx2_Head;
+
+	static inline void cts2_isr_handler(void) __attribute__((always_inline));
+	static inline void cts2_isr_handler(void)
+	{
+		uint8_t tmp = UCSR2B_REGISTER;
+		if(CTS2_PIN & (1<<CTS2_IONUM))
+		{
+			tmp &= ~(1<<UDRIE2_BIT);
+		}
+		else if (tx2_Tail != tx2_Head)
+		{
+			tmp |= (1<<UDRIE2_BIT);
+		}
+		UCSR2B_REGISTER = tmp;
+	}
+	
+	static inline void naked_cts2_isr_handler(void) __attribute__((always_inline));
+	static inline void naked_cts2_isr_handler(void)
+	{
+		asm volatile("\n\t"
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"in %[sreg_save], __SREG__ \n\t"
+		#else
+			"push r16 \n\t"
+			"in r16,__SREG__ \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"movw %[z_save], r24 \n\t"
+		#else
+			"push r24 \n\t"
+		#endif
+		
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
+			"sbic %M[cts_port], %M[cts_pin]\n\t"
+			"rjmp cts_apply_%= \n\t"
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r25 \n\t"
+		#endif
+			"lds r24, (tx2_Head) \n\t"
+			"lds r25, (tx2_Tail) \n\t"
+			"cp r25, r24 \n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r25 \n\t"
+		#endif
+			"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case - no need to clear it
+			
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"ori r24, (1<<%M[UDRIE_bit]) \n\t"
+		"cts_apply_%=:"	
+			"sts %M[UCSRB_reg], r24 \n\t"
+		
+		"cts_exit_%=:"
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE	
+			"movw r24, %[z_save] \n\t"
+		#else
+			"pop r24 \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, %[sreg_save] \n\t"
+		#else
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#endif
+
+			"reti \n\t"
+			: /* output operands */
+			USART_REG_SAVE_LIST
+			: /* input operands */
+			[UCSRB_reg]      "n" (_SFR_MEM_ADDR(UCSR2B_REGISTER)),
+			[UDRIE_bit]      "M" (UDRIE2_BIT),
+			[cts_port]       "M" (_SFR_IO_ADDR(CTS2_PIN)),
+			[cts_pin]        "M" (CTS2_IONUM)
+			: /* clobbers */
+		);
+	}
+#endif
+
+#if defined(USART3_USE_SOFT_CTS)&&!defined(NO_TX3_INTERRUPT)
+	extern volatile uint8_t tx3_Tail, tx3_Head;
+
+	static inline void cts3_isr_handler(void) __attribute__((always_inline));
+	static inline void cts3_isr_handler(void)
+	{
+		uint8_t tmp = UCSR3B_REGISTER;
+		if(CTS3_PIN & (1<<CTS3_IONUM))
+		{
+			tmp &= ~(1<<UDRIE3_BIT);
+		}
+		else if (tx3_Tail != tx3_Head)
+		{
+			tmp |= (1<<UDRIE3_BIT);
+		}
+		UCSR3B_REGISTER = tmp;
+	}
+	
+	static inline void naked_cts3_isr_handler(void) __attribute__((always_inline));
+	static inline void naked_cts3_isr_handler(void)
+	{
+		asm volatile("\n\t"
+			
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"in %[sreg_save], __SREG__ \n\t"
+		#else
+			"push r16 \n\t"
+			"in r16,__SREG__ \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"movw %[z_save], r24 \n\t"
+		#else
+			"push r24 \n\t"
+		#endif
+		
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
+			"sbic %M[cts_port], %M[cts_pin]\n\t"
+			"rjmp cts_apply_%= \n\t"
+			
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"push r25 \n\t"
+		#endif
+			"lds r24, (tx3_Head) \n\t"
+			"lds r25, (tx3_Tail) \n\t"
+			"cp r25, r24 \n\t"
+		
+		#ifndef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
+			"pop r25 \n\t"
+		#endif
+			"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case - no need to clear it
+			
+			"lds r24, %M[UCSRB_reg] \n\t"
+			"ori r24, (1<<%M[UDRIE_bit]) \n\t"
+		"cts_apply_%=:"	
+			"sts %M[UCSRB_reg], r24 \n\t"
+		
+		"cts_exit_%=:"
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE	
+			"movw r24, %[z_save] \n\t"
+		#else
+			"pop r24 \n\t"
+		#endif
+		
+		#ifdef USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE
+			"out __SREG__, %[sreg_save] \n\t"
+		#else
+			"out __SREG__, r16 \n\t"
+			"pop r16 \n\t"
+		#endif
+
+			"reti \n\t"
+			: /* output operands */
+			USART_REG_SAVE_LIST
+			: /* input operands */
+			[UCSRB_reg]      "n" (_SFR_MEM_ADDR(UCSR3B_REGISTER)),
+			[UDRIE_bit]      "M" (UDRIE3_BIT),
+			[cts_port]       "M" (_SFR_IO_ADDR(CTS3_PIN)),
+			[cts_pin]        "M" (CTS3_IONUM)
+			: /* clobbers */
+		);
+	}
+#endif
+
+/************************************************************************************
+ *                              stdio.h stuff                                       *
+ ************************************************************************************/
+#include <stdio.h> // avoid compilation errors
+
+#if defined(USE_USART1)||defined(USE_USART2)||defined(USE_USART3)
+
+	// wrapper of stdio.h FDEV_SETUP_STREAM to allow setting udata; udata is used to store info about port ID
+	#define FDEV_SETUP_STREAM_U(p, g, f, u) \
+	{ \
+		.put = p, \
+		.get = g, \
+		.flags = f, \
+		.udata = u, \
+	}
+	
+	#ifndef NO_USART_TX
+		int uart_putchar(char data, FILE *stream);
+	#endif
+
+	#ifndef NO_USART_RX
+		int uart_getchar(FILE *stream);
+	#endif
+	
+	#ifdef USE_USART0
+	
+		#if defined(NO_RX0_INTERRUPT)
+			extern FILE uart0_out;
+		
+		#elif defined(NO_TX0_INTERRUPT)
+			extern FILE uart0_in;
+		#else
+			extern FILE uart0_io;
+			extern FILE uart0_in;
+			extern FILE uart0_out;
+		#endif
+		
+	#endif // USE_USART0
+	
+	#ifdef USE_USART1
+	
+		#if defined(NO_RX1_INTERRUPT)
+			extern FILE uart1_out;
+		
+		#elif defined(NO_TX1_INTERRUPT)
+			extern FILE uart1_in;
+		#else
+			extern FILE uart1_io;
+			extern FILE uart1_in;
+			extern FILE uart1_out;
+		#endif
+		
+	#endif // USE_USART1
+	
+	#ifdef USE_USART2
+	
+		#if defined(NO_RX2_INTERRUPT)
+			extern FILE uart2_out;
+		
+		#elif defined(NO_TX2_INTERRUPT)
+			extern FILE uart2_in;
+		#else
+			extern FILE uart2_io;
+			extern FILE uart2_in;
+			extern FILE uart2_out;
+		#endif
+		
+	#endif // USE_USART2
+		
+	#ifdef USE_USART3
+		
+		#if defined(NO_RX3_INTERRUPT)
+			extern FILE uart3_out;
+		
+		#elif defined(NO_TX3_INTERRUPT)
+			extern FILE uart3_in;
+		#else
+			extern FILE uart3_io;
+			extern FILE uart3_in;
+			extern FILE uart3_out;
+		#endif
+		
+	#endif // USE_USART3
+	
+#else // single USART mcu
+
+	#ifndef NO_TX0_INTERRUPT
+		int uart_putchar(char data, FILE *stream);
+	#endif
+
+	#ifndef NO_RX0_INTERRUPT
+		int uart_getchar(FILE *stream);
+	#endif
+	
+	#if defined(NO_RX0_INTERRUPT)
+		extern FILE uart0_out;
+	
+	#elif defined(NO_TX0_INTERRUPT)
+		extern FILE uart0_in;
+	#else
+		extern FILE uart0_io;
+		extern FILE uart0_in;
+		extern FILE uart0_out;
+	#endif
+	
+#endif // single/multi USART
+
+#ifdef __cplusplus
+	}
+#endif
+
+#endif // _USART_H_
diff --git a/vendor/jnk0le-AVR-UART-lib/usart_config.h b/vendor/jnk0le-AVR-UART-lib/usart_config.h
new file mode 100644
index 0000000..dabd328
--- /dev/null
+++ b/vendor/jnk0le-AVR-UART-lib/usart_config.h
@@ -0,0 +1,345 @@
+/*!
+ * \brief
+ *
+ * \author Jan Oleksiewicz <jnk0le@hotmail.com>
+ * \license SPDX-License-Identifier: MIT
+ */
+
+#ifndef USART_CONFIG_H_
+#define USART_CONFIG_H_
+
+// DO NOT DEFINE F_CPU, BUFFERS SIZES OR ANY OTHER SHARED MACROS IN 'main.c' CODE
+// instead of this, define it in makefile (-D flag) or "Project Properties -> AVR C Compiler -> Symbols"
+
+//#define NO_USART_RX // disable all receiver code and dependencies
+//#define NO_USART_TX // disable all transmitter code and dependencies
+
+//#define USART_MPCM_MODE // globally enable MPCM operation mode // 9 bit data frame only // always set frame format to 8 data bits
+
+//#define USE_DOUBLE_SPEED // enables double speed for all available USART interfaces
+
+#define RX_STDIO_GETCHAR_ECHO // echoes back received characters in getchar() function (for reading in scanf())
+//#define RX_GETC_ECHO // echoes back received characters in getc() function
+
+//#define PUTC_CONVERT_LF_TO_CRLF // allow for unix style (\n only) newline terminator in stored strings // not included into putc_noblock
+#define RX_NEWLINE_MODE 2 // 0 - \r,  1 - \n,  2 - \r\n
+// lot of terminals sends only \r character as a newline terminator, instead of \r\n or even unix style \n
+// (BTW PuTTY doesn't allow to change this) but in return requires \r\n terminator to show not broken text
+
+//#define USART_NO_ABI_BREAKING_PREMATURES // do not use prematures that might break compilers ABI (non-gcc calling conventions), compilers that are not forcing constant number of call-used registers might generate even better code
+//#define USART_PUTHEX_IN_UPPERCASE // use uppercase letters in uart_puthex() function
+//#define USART_EXTEND_RX_BUFFER // extend RX buffer by hardware 2/3 byte FIFO // required for hardware and software RTS
+//#define USART_PUTC_FAST_INSERTIONS // skip FIFO procedure and write directly data to the UDR register when possible // probably required for full bus utilization at highest speed (f_cpu/8)
+//#define USART_NO_LOCAL_BUFFERS // do not allocate temporary buffers on stack for integer/float <-> asci conversions and use globally visible u_tmp_buff[] instead // it have to be declared in application part and have to be at least of 6-17 bytes wide (depending on what is being converted)
+//#define USART_UNSAFE_TX_INTERRUPT // max 19 cycles of interrupt latency // 3+PC bytes on stack // will not interrupt itself
+//#define USART_UNSAFE_RX_INTERRUPT // max 23 cycles of interrupt latency // 4+PC bytes on stack // will not interrupt itself
+//#define USART_REMAP_LAST_INTERFACE // remap hardware registers of USART1/2/3 to USART0 if only one interface is used
+//#define USART_SKIP_UBRRH_IF_ZERO // do not generate code for writing to ubrrh if calculated value is zero // prematures out 2 bytes if ubrr is compile time constant
+
+//#define USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE // prematures out 4 cycles from every isr run // requires one globally reserved lower register
+//#define USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE    // prematures out 6 cycles from every isr run // requires pair of globally reserved lower registers
+// usage of globally reserved register for temporary storage in interrupts, should be combined with other interrupts for best results. 
+// special care have to be taken when doing so, since those registers can still be used by other compilation units (fixable in gcc by -ffixed-n flag, where n is a suppressed register),
+// precompiled libraries (vprintf, vscanf, qsort, strtod, strtol, strtoul), or even assembly hardcoded libraries (fft, aes).
+// registers r2-r7 should be used instead of the higher ones, since those are never used by gcc for eg. argument passing.
+
+	#define USART_SREG_SAVE_REG_NAME G_sreg_save // ??? // have to be redeclared under the same name if the same registers are reused in other instances (libs)
+	#define USART_SREG_SAVE_REG_NUM "r4"
+	
+	#define USART_Z_SAVE_REG_NAME G_z_save // ??? // have to be redeclared under the same name if the same registers are reused in other instances (libs)
+	#define USART_Z_SAVE_REG_NUM "r2" // register pair rn and rn+1 (rn+1:rn gives "invalid register name")
+
+//#define RX_BUFFER_SIZE 128 // Size of the ring buffers, must be power of 2 // default 32
+//#define TX_BUFFER_SIZE 64 // Size of the ring buffers, must be power of 2 // default 32
+
+/*****************************config for multiple USART mcu's***********************************/
+
+//#define NO_USART0 // disable usage of uart0
+//#define NO_USART1 // disable usage of uart1
+//#define NO_USART2 // disable usage of uart2
+//#define NO_USART3 // disable usage of uart3
+
+//#define RX0_BUFFER_SIZE 128
+//#define TX0_BUFFER_SIZE 64
+
+//#define RX1_BUFFER_SIZE 128
+//#define TX1_BUFFER_SIZE 64
+
+//#define RX2_BUFFER_SIZE 128
+//#define TX2_BUFFER_SIZE 64
+
+//#define RX3_BUFFER_SIZE 128
+//#define TX3_BUFFER_SIZE 64
+
+//#define NO_RX0_INTERRUPT // removes whole receive code (including ISR) and frees RX0 pin // combining with NO_USART_RX is not necessary
+//#define NO_RX1_INTERRUPT // removes whole receive code (including ISR) and frees RX1 pin
+//#define NO_RX2_INTERRUPT // removes whole receive code (including ISR) and frees RX2 pin
+//#define NO_RX3_INTERRUPT // removes whole receive code (including ISR) and frees RX3 pin
+
+//#define NO_TX0_INTERRUPT // removes whole transmit code (including ISR) and frees TX0 pin // combining with NO_USART_TX is not necessary
+//#define NO_TX1_INTERRUPT // removes whole transmit code (including ISR) and frees TX1 pin
+//#define NO_TX2_INTERRUPT // removes whole transmit code (including ISR) and frees TX2 pin
+//#define NO_TX3_INTERRUPT // removes whole transmit code (including ISR) and frees TX3 pin
+
+//#define USART0_U2X_SPEED // enables double speed for USART0
+//#define USART1_U2X_SPEED // enables double speed for USART1
+//#define USART2_U2X_SPEED // enables double speed for USART2
+//#define USART3_U2X_SPEED // enables double speed for USART3
+
+//#define RX0_GETC_ECHO
+//#define RX1_GETC_ECHO
+//#define RX2_GETC_ECHO
+//#define RX3_GETC_ECHO
+
+//#define PUTC0_CONVERT_LF_TO_CRLF
+//#define PUTC1_CONVERT_LF_TO_CRLF
+//#define PUTC2_CONVERT_LF_TO_CRLF
+//#define PUTC3_CONVERT_LF_TO_CRLF
+
+//#define USART0_EXTEND_RX_BUFFER
+//#define USART1_EXTEND_RX_BUFFER
+//#define USART2_EXTEND_RX_BUFFER
+//#define USART3_EXTEND_RX_BUFFER
+
+//#define USART0_PUTC_FAST_INSERTIONS
+//#define USART1_PUTC_FAST_INSERTIONS
+//#define USART2_PUTC_FAST_INSERTIONS
+//#define USART3_PUTC_FAST_INSERTIONS
+
+//#define USART0_MPCM_MODE
+//#define USART1_MPCM_MODE
+//#define USART2_MPCM_MODE
+//#define USART3_MPCM_MODE
+
+/*****************************soft flow control config***********************************/
+// define IO instance to enable software CTS  
+// CTS handlers also have to be placed into INT/PCINT interrupt in the application code, see example(flow control).c
+
+//#define CTS0_DDR // DDRB
+//#define CTS0_PORT // PORTB
+//#define CTS0_PIN // PINB
+//#define CTS0_IONUM // 0 // pin number
+
+//#define CTS1_DDR
+//#define CTS1_PORT
+//#define CTS1_PIN
+//#define CTS1_IONUM
+
+//#define CTS2_DDR
+//#define CTS2_PORT
+//#define CTS2_PIN
+//#define CTS2_IONUM
+
+//#define CTS3_DDR
+//#define CTS3_PORT
+//#define CTS3_PIN
+//#define CTS3_IONUM
+
+// define IO instance to enable software RTS
+
+//#define RTS0_DDR // DDRB
+//#define RTS0_PORT // PORTB
+//#define RTS0_PIN // PINB
+//#define RTS0_IONUM // 1 // pin number
+
+//#define RTS1_DDR
+//#define RTS1_PORT
+//#define RTS1_PIN
+//#define RTS1_IONUM
+
+//#define RTS2_DDR
+//#define RTS2_PORT
+//#define RTS2_PIN
+//#define RTS2_IONUM
+
+//#define RTS3_DDR
+//#define RTS3_PORT
+//#define RTS3_PIN
+//#define RTS3_IONUM
+
+/*****************************RS 485 config***********************************/
+// define IO instance to enable half duplex rs485 operation mode // used pin should be initially kept in low state before boot
+
+//#define RS485_CONTROL0_DDR // DDRB
+//#define RS485_CONTROL0_PORT // PORTB
+//#define RS485_CONTROL0_PIN // PINB
+//#define RS485_CONTROL0_IONUM // 2 // pin number
+
+//#define RS485_CONTROL1_DDR
+//#define RS485_CONTROL1_PORT
+//#define RS485_CONTROL1_PIN
+//#define RS485_CONTROL1_IONUM
+
+//#define RS485_CONTROL2_DDR
+//#define RS485_CONTROL2_PORT
+//#define RS485_CONTROL2_PIN
+//#define RS485_CONTROL2_IONUM
+
+//#define RS485_CONTROL3_DDR
+//#define RS485_CONTROL3_PORT
+//#define RS485_CONTROL3_PIN
+//#define RS485_CONTROL3_IONUM
+
+/*****************************MPCM config***********************************/
+
+#define MPCM0_ADDRESS 0x01
+#define MPCM1_ADDRESS 0x02
+#define MPCM2_ADDRESS 0x03
+#define MPCM3_ADDRESS 0x04
+
+//#define MPCM0_GCALL_ADDRESS 0x00
+//#define MPCM1_GCALL_ADDRESS 0x00
+//#define MPCM2_GCALL_ADDRESS 0x00
+//#define MPCM3_GCALL_ADDRESS 0x00
+
+//#define MPCM0_MASTER_ONLY // do not include slave code into RX ISR
+//#define MPCM1_MASTER_ONLY // do not include slave code into RX ISR
+//#define MPCM2_MASTER_ONLY // do not include slave code into RX ISR
+//#define MPCM3_MASTER_ONLY // do not include slave code into RX ISR
+
+// Optional macros for placing user-defined code that will be executed inside of USART interrupt handlers.
+// Only inline asm and its input operand lists are allowed to be put here.
+// Too large code may generate weird cryptic linker errors, what is caused by exceeded range of branch instructions.
+// http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
+
+// example:
+//#define STH_EVENT "nop \n\t"\                              //
+//                  "ldi r31, %M[A_MASK] \n\t"\              //
+//                  "out %M[TIMADDR], r31 \n\t"
+//#define OPERAND_LIST [A_MASK] "M" (0x55),\                 //
+//                     [TIMADDR]  "M" (_SFR_IO_ADDR(TCCR0A)),
+
+// code executed on every ISR call, before feeding UDR (for this racing implementation only), can be placed here // r30 and r31 are free to use
+#define TX0_EVERYCAL_EVENT "\n\t"
+
+// code executed on every byte transmission, can be placed here // r30 and r31 are free to use // r30 contains currently transmitted data byte
+#define TX0_TRANSMIT_EVENT "\n\t"
+
+#define TX0_INPUT_OPERAND_LIST 
+
+#if !defined(USART0_EXTEND_RX_BUFFER) // DO NOT CHANGE
+	// code executed before reading UDR register can be placed here // r25 is free to use // executed before enabling interrupts in unsafe mode
+	#define RX0_FRAMING_EVENT "\n\t"
+	
+	//#define USART0_PUSH_BEFORE_RX // frees r30 an r31 for FRAMING_EVENT
+#else
+	// code executed before reading UDR register can be placed here // r25 and r31 are free to use
+	#define RX0_FRAMING_EVENT "\n\t"
+#endif
+
+// code executed on every ISR call, can be placed here // r30 and r31 are free to use // r25 contains received data byte if 'extended buffer' mode is not used, free to use otherwise
+#define RX0_EVERYCALL_EVENT "\n\t"
+
+// code executed only when databyte was received, before buffer store, can be placed here // r31 is free to use // r25 contains received data byte, r30 rxn_last_byte buffer index // MPCM ??
+#define RX0_EARLY_RECEIVE_EVENT "\n\t"
+
+// code executed only when databyte was received, can be placed here // r25,r30,r31 are free to use // r25 contains received data byte
+#define RX0_LATE_RECEIVE_EVENT "\n\t"
+
+#define RX0_INPUT_OPERAND_LIST
+
+//************************************************
+
+#define TX1_EVERYCAL_EVENT "\n\t"
+#define TX1_TRANSMIT_EVENT "\n\t"
+
+#define TX1_INPUT_OPERAND_LIST
+
+#if !defined(USART1_EXTEND_RX_BUFFER) // DO NOT CHANGE
+	#define RX1_FRAMING_EVENT "\n\t"
+	//#define USART1_PUSH_BEFORE_RX
+#else
+	#define RX1_FRAMING_EVENT "\n\t"
+#endif
+
+#define RX1_EVERYCALL_EVENT "\n\t"
+#define RX1_EARLY_RECEIVE_EVENT "\n\t"
+#define RX1_LATE_RECEIVE_EVENT "\n\t"
+
+#define RX1_INPUT_OPERAND_LIST
+
+//************************************************
+
+#define TX2_EVERYCAL_EVENT "\n\t"
+#define TX2_TRANSMIT_EVENT "\n\t"
+
+#define TX2_INPUT_OPERAND_LIST
+
+#if !defined(USART2_EXTEND_RX_BUFFER) // DO NOT CHANGE
+	#define RX2_FRAMING_EVENT "\n\t"
+	//#define USART2_PUSH_BEFORE_RX
+#else
+	#define RX2_FRAMING_EVENT "\n\t"
+#endif
+
+#define RX2_EVERYCALL_EVENT "\n\t"
+#define RX2_EARLY_RECEIVE_EVENT "\n\t"
+#define RX2_LATE_RECEIVE_EVENT "\n\t"
+
+#define RX2_INPUT_OPERAND_LIST
+
+//************************************************
+
+#define TX3_EVERYCAL_EVENT "\n\t"
+#define TX3_TRANSMIT_EVENT "\n\t"
+
+#define TX3_INPUT_OPERAND_LIST
+
+#if !defined(USART3_EXTEND_RX_BUFFER) // DO NOT CHANGE
+	#define RX3_FRAMING_EVENT "\n\t"
+	//#define USART3_PUSH_BEFORE_RX
+#else
+	#define RX3_FRAMING_EVENT "\n\t"
+#endif
+
+#define RX3_EVERYCALL_EVENT "\n\t"
+#define RX3_EARLY_RECEIVE_EVENT "\n\t"
+#define RX3_LATE_RECEIVE_EVENT "\n\t"
+
+#define RX3_INPUT_OPERAND_LIST
+
+// events executed inside transmit complete interrupts (last byte has been transmitted, UDR buffer is empty)
+// if USATRn_NO_NAKED_TXC_INTERRUPT is not defined then inline asm is required here // any modified regs have to be pushed first
+//inline void TXCn_interrupt_event(void)
+//{
+//	asm volatile("\n\t"
+//		"nop \n\t"
+//		"lpm \n\t"
+//		"st Z+, r0 \n\t"
+//	:: );
+//}
+// mpcm ??
+
+//#define USATR0_NO_NAKED_TXC_INTERRUPT
+//#define USART0_USE_TXC_INTERRUPT // if rs485 is not used
+
+inline void TXC0_interrupt_event(void) __attribute__((always_inline));
+inline void TXC0_interrupt_event(void)
+{
+}
+
+//#define USATR1_NO_NAKED_TXC_INTERRUPT 
+//#define USART1_USE_TXC_INTERRUPT
+
+inline void TXC1_interrupt_event(void) __attribute__((always_inline));
+inline void TXC1_interrupt_event(void)
+{
+}
+
+//#define USATR2_NO_NAKED_TXC_INTERRUPT 
+//#define USART2_USE_TXC_INTERRUPT
+
+inline void TXC2_interrupt_event(void) __attribute__((always_inline));
+inline void TXC2_interrupt_event(void)
+{
+}
+
+//#define USATR3_NO_NAKED_TXC_INTERRUPT 
+//#define USART3_USE_TXC_INTERRUPT
+
+inline void TXC3_interrupt_event(void) __attribute__((always_inline));
+inline void TXC3_interrupt_event(void)
+{
+}
+
+#endif /* USART_CONFIG_H_ */
\ No newline at end of file