mirror of
https://github.com/halleysfifthinc/AVCLAN-Mockingboard.git
synced 2026-09-25 13:22:06 +00:00
PIO proof-of-concept
This commit is contained in:
Allen Hill
+1
-1
@@ -61,7 +61,7 @@
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},
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"environment": {
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"PICO_PLATFORM": "rp2350-arm-s",
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"PICO_BOARD": "pimoroni_pico_plus2w_rp2350"
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"PICO_BOARD": "pimoroni_pico_plus2_w_rp2350"
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}
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},
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{
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@@ -1,4 +1,3 @@
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list(APPEND PICO_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/pimoroni_pico_plus2w_rp2350.h)
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pico_sdk_init()
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target_sources(avclan PRIVATE
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@@ -8,11 +7,15 @@ target_sources(avclan PRIVATE
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board.cc
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stdio.cc
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)
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pico_generate_pio_header(avclan ${CMAKE_CURRENT_LIST_DIR}/iebus.pio)
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target_link_libraries(avclan PUBLIC
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pico_stdlib pico_stdio_usb
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pico_stdlib pico_stdio_usb hardware_pio hardware_dma pico_multicore
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)
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pico_enable_stdio_usb(avclan 1)
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# Needs separate/new executable target because `pico_add_extra_outputs` only
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# works on locally (to this file/directory) defined targets
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add_executable(mockingboard_pico
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${avclan-mockingboard_SOURCE_DIR}/src/sniffer.cc
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)
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@@ -30,3 +33,11 @@ unset(_tinyusb_sources)
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pico_add_extra_outputs(mockingboard_pico)
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pico_set_float_implementation(mockingboard_pico none)
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pico_set_double_implementation(mockingboard_pico none)
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pico_set_program_name(mockingboard_pico mockingboard)
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pico_set_program_description(mockingboard_pico
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"Emulate an external CD Changer on an AVCLAN bus to add Bluetooth and aux-input audio to older Toyota's"
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)
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pico_set_program_version(mockingboard_pico
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"${avclan-mockingboard_VERSION}")
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pico_set_program_url(mockingboard_pico "https://github.com/halleysfifthinc/AVCLAN-Mockingboard")
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@@ -0,0 +1,186 @@
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.define public parity_irq 7 ; (polled) Signal BAD_PARITY
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.define public should_ack_irq 6 ; (system)
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; This is used to set the clkdiv.
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; The delay cycle counts in read_bit (AVCLAN_READBIT_THRESHOLD) and iebus_ack
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; (AVCLAN_BIT0_LOGIC_0) must be updated in sync with this variable
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.define public CYCLES_PER_READBIT_PERIOD 64
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.pio_version 1
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.program iebus_rx
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; Initial TX Encoding
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; | 19:4 | 3:0 |
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; | Instr | # bit/instr |
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;
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; Proper behavior for reads is dependent on encoding and executing a `in null, (15 - x)`
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; instruction to initialize the bit count correctly.
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; An even number of instructions must be executed to maintain the correct shift-count/autopull
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; when returning to normal reads after exec'ing. Pad instructions with `nop` as needed.
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;
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; RX encoding: one read per word (RX FIFO can hold max 4 reads)
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; | 31:16 | 15:0 |
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; | zeros | slot |
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;
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; where each slot is encoded as
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; | MSB .................... LSB |
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; | 15-N zeros | N bits | parity |
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.in 1 left
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.out 0 right auto 20
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.mov_status irq set should_ack_irq
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bad_parity:
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irq set parity_irq ; Flag *before* the push: the app samples the flag right
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; after taking the word, so setting it after would race
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push ; Push the failing slot; blocks, so the app must keep
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; draining while it waits for the stall below
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public parity_stall:
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wait 0 irq parity_irq ; Stall until the app clears it. Public so the app can
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; poll for the SM parking here before draining the FIFO
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; -- the push above lands ~2 cycles after the flag.
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wait_read:
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.wrap_target
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set y 0 ; Reset the parity accumulator
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out x, 4 ; Load bit count; the loop will have x + 1 iterations
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out exec, 16 ; Pad or jmp to do_exec
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read_bit:
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;;; Resynchronize at each recessive => dominant edge
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wait 1 pin 0
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; Worst-case (slowest) path to return here is for non-ACK flow.
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wait 0 pin 0 [31] ; Delay for mid-data period (~AVCLAN_READBIT_THRESHOLD) after
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nop [31] ; bus goes dominant
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in pins, 1 ; Read bus state
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jmp pin count_one ; count only if bus is recessive (logical 1)
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; EXECCTRL_JMP_PIN == RX pin
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jmp count_bit
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count_one:
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mov y, ~y ; Toggle on each 1 bit: zero is even, all-ones is odd.
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count_bit:
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jmp x-- read_bit ; Last use of x as bit count
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;;; check parity
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jmp y-- bad_parity ; Even parity over data+parity means an even count of 1
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; bits, so a nonzero y is an error. (clobbers y)
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push ; Parity good
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;;; check if we should ack
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mov x, status ; Load should_ack_irq into x (clobbers x)
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jmp !x wait_read ; Fall through if should_ack_irq is set
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;;; ack
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set x 3
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wait 1 pin 0
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wait 0 pin 0 ; Synchronize with sender
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set pins, 0 [13] ; Drive bus (dominant) for ~AVCLAN_BIT0_LOGIC_0
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loop: ; Total loop length (1+15)*3 cycles
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jmp x-- loop [15]
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set pins, 1 ; Release bus
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.wrap
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; Executes one streamed instruction every 3 cycles
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public do_exec:
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out exec, 16 ; Cycle 1: Load the streamed instruction
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; Cycle 2: Execute the streamed instruction
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jmp x-- do_exec ; Cycle 3: Restart loop (if x != 0)
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jmp wait_read
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.program iebus_tx
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.fifo tx
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; TX Encoding (8 deep TX FIFO):
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; | MSB ............................................ LSB |
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; | 4 bits | N bits | 1 bit | 1 bit | 26 - N bits |
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; | Length (N) | Data+P | ACK slot | NAK | padding |
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;
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; Parity is generated by the driver and appended as the last (least significant)
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; bit of the data field
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.in 1 left
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.out 1 left
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.define public nak_irq 7
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.define public lost_arb_irq 6
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handle_nak:
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out x, 1
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jmp x-- reset ; Reset if NAK was expected
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irq wait nak_irq
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reset:
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.wrap_target
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pull
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out x, 4
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send_bit:
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set pins, 0 [31]
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out y, 1 [15] ; OUT pin remains low/dominant for 48 cycles (~AVCLAN_BIT1_LOGIC_0)
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mov pins, y [15]
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jmp pin bit_one ; Sampled at ~AVCLAN_READBIT_THRESHOLD (64 cycles from bit start)
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; JMP_PIN must be the IEBUS_RX pin (TX activity will
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; mirror back to the RX pin)
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bit_zero:
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jmp !y bit_end [15] ; Delay 16 more cycles before releasing bus at ~AVCLAN_BIT0_LOGIC_0
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; Fall through means we lost arbitration
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irq wait lost_arb_irq
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jmp reset
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bit_one:
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; Bus already released by `mov pins, y`, which caused/allowed the jmp
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nop [12]
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bit_end: ; 15 cycles (~AVCLAN_BIT0_LOGIC_1) of recessive before the next leading
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; edge, on all three exits: the loop (via next_bit), reset, and the ack
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; slot below. Each spends a different number of instructions getting
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; there, so the delay is split between here and the padding they carry.
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set pins, 1 [11]
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jmp x-- send_bit ; Fall through once x (the bit count) is exhausted
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out x, 1
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jmp !x reset ; Jump to reset if x (fill ack slot) is zero
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;;; read ack
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nop [1] ; Match the 2 cycles the reset path spends in
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; pull/out before its first `set pins, 0`, so the last
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; bit gets a full period on both exits
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set pins, 0 [31]
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nop [15]
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set pins, 1 [15]
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jmp pin handle_nak [29] ; Sampled at 64 cycles (~AVCLAN_READBIT_THRESHOLD),
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; then held out to a full 96-cycle logic-0 period: an
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; ACKing peripheral drives dominant until cycle 81
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; (~AVCLAN_BIT0_LOGIC_0), so starting the next bit any
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; sooner swallows its leading edge
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.wrap
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; Copy one input pin to one output pin, forever, at the SM clock. Used to drive
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; the activity LEDs from the bus pins without hanging any DC load on them: the
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; LED current comes out of the mirror pin's pad, and the bus pin only ever sees
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; a (already-enabled) input.
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;
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; `mov pins, pins` reads the IN mapping (bit 0 == in base) and writes the OUT
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; mapping (out base, 1 pin), so one program instance serves any src->dst pair;
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; give each pair its own SM with its own pin mapping.
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.program pin_mirror
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.wrap_target
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mov pins, ~pins
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.wrap
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; === IDIOMS ===
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;;; Isolate first bit (for left shifting)
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; mov osr, ::isr ; Reverse ISR so its LSB becomes the MSB in osr
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; out x, 1 ; Set LSB of x from MSB of osr
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;;; Incrementing (counting up)
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; set x 0
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; set x ~x ; x == 0xffffffff
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; jmp x-- label ; "Increment"
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; set x ~x ; Re-inversing gives the actual count
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; SHIFTCTRL_IN_COUNT = 0x01 (mask for number of pins/LSBs to read/set by `mov x, pins`)
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@@ -1,11 +1,90 @@
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#include "hal/phy.h"
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#include "avclan.h"
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#include "hardware/gpio.h"
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#include "hardware/pio.h"
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#include "iebus.pio.h"
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#include <hardware/clocks.h>
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#define TICK_US 1000000
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#include "timing.h"
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using namespace avclan;
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using enum detail::Error::Read;
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using enum detail::Error::Send;
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extern "C" void phy_init() {}
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namespace {
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constexpr int IEBUS_TX = 16;
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constexpr int IEBUS_RX = 17;
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// Activity indicators: each follows its bus pin exactly, so an LED wired
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// supply -> resistor -> pin is lit while that line is dominant (low). The bus
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// pins themselves stay unloaded.
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constexpr int LED_RX = 8;
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constexpr int LED_TX = 26;
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PIO pio;
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uint sm;
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uint offset;
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inline void iebus_rx_program_init(PIO pio, uint sm, uint offset, uint pin_rx,
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uint pin_tx) {
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pio_sm_set_consecutive_pindirs(pio, sm, pin_rx, 1, false);
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pio_sm_set_consecutive_pindirs(pio, sm, pin_tx, 1, true);
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pio_sm_set_pins_with_mask(pio, sm, (1U << pin_tx), (1U << pin_tx));
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pio_gpio_init(pio, pin_rx);
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pio_gpio_init(pio, pin_tx);
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pio_sm_config cfg = iebus_rx_program_get_default_config(offset);
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sm_config_set_in_pins(&cfg, pin_rx);
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sm_config_set_jmp_pin(&cfg, pin_rx);
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sm_config_set_set_pins(&cfg, pin_tx, 1);
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// CYCLES_PER_READBIT_PERIOD PIO cycles should take
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// ~AVCLAN_READBIT_THRESHOLD μs
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float div = clock_get_hz(clk_sys) /
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(CYCLES_PER_READBIT_PERIOD / (float)AVCLAN_READBIT_THRESHOLD);
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sm_config_set_clkdiv(&cfg, div);
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pio_sm_init(pio, sm, offset, &cfg);
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pio_sm_set_enabled(pio, sm, true);
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}
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// Point one mirror SM at one src -> dst pair. Only the destination gets
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// `pio_gpio_init`: taking the function select of a source pin would hand it to
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// this PIO block and cut whoever actually drives it (IEBUS_TX) loose. Reading
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// needs nothing but the pad's input buffer, which is on for both bus pins
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// already -- asserted here so the mirror cannot go dark if that changes.
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void pin_mirror_sm_init(PIO mpio, uint msm, uint moffset, uint src, uint dst) {
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gpio_set_input_enabled(src, true);
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pio_gpio_init(mpio, dst);
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pio_sm_set_consecutive_pindirs(mpio, msm, dst, 1, true);
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pio_sm_config cfg = pin_mirror_program_get_default_config(moffset);
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sm_config_set_in_pins(&cfg, src);
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sm_config_set_out_pins(&cfg, dst, 1);
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// Default clkdiv: one copy per system clock, so the LED tracks the line far
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// faster than a bit period.
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pio_sm_init(mpio, msm, moffset, &cfg);
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pio_sm_set_enabled(mpio, msm, true);
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}
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} // namespace
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extern "C" void phy_init() {
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gpio_init(IEBUS_TX);
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gpio_init(IEBUS_RX);
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gpio_set_dir(IEBUS_TX, true); // CAN/AVCLAN TX
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gpio_set_dir(IEBUS_RX, false); // CAN/AVCLAN RX
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bool success =
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pio_claim_free_sm_and_add_program(&iebus_rx_program, &pio, &sm, &offset);
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hard_assert(success);
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iebus_rx_program_init(pio, sm, offset, IEBUS_RX, IEBUS_TX);
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pio_sm_exec(pio, sm, pio_encode_irq_set(false, should_ack_irq));
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}
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extern "C" void phy_mute(bool mute) {}
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@@ -1,162 +0,0 @@
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/*
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
||||
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// -----------------------------------------------------
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// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO
|
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// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
|
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// -----------------------------------------------------
|
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|
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// This header may be included by other board headers as "boards/pimoroni_pico_plus2w_rp2350.h"
|
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|
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// pico_cmake_set PICO_PLATFORM=rp2350
|
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|
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#ifndef _BOARDS_PIMORONI_PICO_PLUS2W_RP2350_H
|
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#define _BOARDS_PIMORONI_PICO_PLUS2W_RP2350_H
|
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|
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// For board detection
|
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#define PIMORONI_PICO_PLUS2_RP2350
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#define PIMORONI_PICO_PLUS2W_RP2350
|
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|
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// --- BOARD SPECIFIC ---
|
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#define SPICE_SPI 0
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#define SPICE_TX_MISO_PIN 32
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#define SPICE_RX_CS_PIN 33
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#define SPICE_NETLIGHT_SCK_PIN 34
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#define SPICE_RESET_MOSI_PIN 35
|
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#define SPICE_PWRKEY_BL_PIN 36
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||||
|
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#define PIMORONI_PICO_PLUS2_USER_SW_PIN 45
|
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#define PIMORONI_PICO_PLUS2_PSRAM_CS_PIN 47
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|
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// --- UART ---
|
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#ifndef PICO_DEFAULT_UART
|
||||
#define PICO_DEFAULT_UART 0
|
||||
#endif
|
||||
#ifndef PICO_DEFAULT_UART_TX_PIN
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||||
#define PICO_DEFAULT_UART_TX_PIN 0
|
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#endif
|
||||
#ifndef PICO_DEFAULT_UART_RX_PIN
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||||
#define PICO_DEFAULT_UART_RX_PIN 1
|
||||
#endif
|
||||
|
||||
// --- LED ---
|
||||
#ifndef PICO_DEFAULT_LED_PIN
|
||||
#define PICO_DEFAULT_LED_PIN 25
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||||
#endif
|
||||
// no PICO_DEFAULT_WS2812_PIN
|
||||
|
||||
// --- I2C ---
|
||||
#ifndef PICO_DEFAULT_I2C
|
||||
#define PICO_DEFAULT_I2C 0
|
||||
#endif
|
||||
#ifndef PICO_DEFAULT_I2C_SDA_PIN
|
||||
#define PICO_DEFAULT_I2C_SDA_PIN 4
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||||
#endif
|
||||
#ifndef PICO_DEFAULT_I2C_SCL_PIN
|
||||
#define PICO_DEFAULT_I2C_SCL_PIN 5
|
||||
#endif
|
||||
|
||||
// --- SPI ---
|
||||
#ifndef PICO_DEFAULT_SPI
|
||||
#define PICO_DEFAULT_SPI 0
|
||||
#endif
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||||
#ifndef PICO_DEFAULT_SPI_SCK_PIN
|
||||
#define PICO_DEFAULT_SPI_SCK_PIN SPICE_NETLIGHT_SCK_PIN
|
||||
#endif
|
||||
#ifndef PICO_DEFAULT_SPI_TX_PIN
|
||||
#define PICO_DEFAULT_SPI_TX_PIN SPICE_RESET_MOSI_PIN
|
||||
#endif
|
||||
#ifndef PICO_DEFAULT_SPI_RX_PIN
|
||||
#define PICO_DEFAULT_SPI_RX_PIN SPICE_TX_MISO_PIN
|
||||
#endif
|
||||
#ifndef PICO_DEFAULT_SPI_CSN_PIN
|
||||
#define PICO_DEFAULT_SPI_CSN_PIN SPICE_RX_CS_PIN
|
||||
#endif
|
||||
|
||||
// --- FLASH ---
|
||||
|
||||
#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
|
||||
|
||||
#ifndef PICO_FLASH_SPI_CLKDIV
|
||||
#define PICO_FLASH_SPI_CLKDIV 2
|
||||
#endif
|
||||
|
||||
// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (16 * 1024 * 1024)
|
||||
#ifndef PICO_FLASH_SIZE_BYTES
|
||||
#define PICO_FLASH_SIZE_BYTES (16 * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
#ifndef CYW43_WL_GPIO_COUNT
|
||||
#define CYW43_WL_GPIO_COUNT 3
|
||||
#endif
|
||||
|
||||
#ifndef CYW43_WL_GPIO_LED_PIN
|
||||
#define CYW43_WL_GPIO_LED_PIN 0
|
||||
#endif
|
||||
|
||||
// If CYW43_WL_GPIO_VBUS_PIN is defined then a CYW43 GPIO has to be used to read VBUS.
|
||||
// This can be passed to cyw43_arch_gpio_get to determine if the device is battery powered.
|
||||
// PICO_VBUS_PIN and CYW43_WL_GPIO_VBUS_PIN should not both be defined.
|
||||
|
||||
// no CYW43_WL_GPIO_VBUS_PIN
|
||||
|
||||
// If CYW43_USES_VSYS_PIN is defined then CYW43 uses the VSYS GPIO (defined by PICO_VSYS_PIN) for other purposes.
|
||||
// If this is the case, to use the VSYS GPIO it's necessary to ensure CYW43 is not using it.
|
||||
// This can be achieved by wrapping the use of the VSYS GPIO in cyw43_thread_enter / cyw43_thread_exit.
|
||||
|
||||
// no CYW43_USES_VSYS_PIN
|
||||
|
||||
// The GPIO Pin used to read VBUS to determine if the device is battery powered.
|
||||
#ifndef PICO_VBUS_PIN
|
||||
#define PICO_VBUS_PIN 24
|
||||
#endif
|
||||
|
||||
// The GPIO Pin used to monitor VSYS. Typically you would use this with ADC.
|
||||
// There is an example in adc/read_vsys in pico-examples.
|
||||
#ifndef PICO_VSYS_PIN
|
||||
#define PICO_VSYS_PIN 43
|
||||
#endif
|
||||
|
||||
#ifndef PICO_RP2350_A2_SUPPORTED
|
||||
#define PICO_RP2350_A2_SUPPORTED 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_PIN_WL_DYNAMIC, flag to indicate if cyw43 SPI pins can be changed at runtime, type=bool, default=false, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_PIN_WL_DYNAMIC
|
||||
#define CYW43_PIN_WL_DYNAMIC 1
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_REG_ON, gpio pin to power up the cyw43 chip, type=int, default=23, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_REG_ON
|
||||
#define CYW43_DEFAULT_PIN_WL_REG_ON 23u
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_OUT, gpio pin for spi data out to the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_DATA_OUT
|
||||
#define CYW43_DEFAULT_PIN_WL_DATA_OUT 24u
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_IN, gpio pin for spi data in from the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_DATA_IN
|
||||
#define CYW43_DEFAULT_PIN_WL_DATA_IN 24u
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_HOST_WAKE, gpio (irq) pin for the irq line from the cyw43 chip, type=int, default=24, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_HOST_WAKE
|
||||
#define CYW43_DEFAULT_PIN_WL_HOST_WAKE 24u
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CLOCK, gpio pin for the spi clock line to the cyw43 chip, type=int, default=29, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_CLOCK
|
||||
#define CYW43_DEFAULT_PIN_WL_CLOCK 29u
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CS, gpio pin for the spi chip select to the cyw43 chip, type=int, default=25, advanced=true, group=pico_cyw43_driver
|
||||
#ifndef CYW43_DEFAULT_PIN_WL_CS
|
||||
#define CYW43_DEFAULT_PIN_WL_CS 25u
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user