mirror of
https://github.com/halleysfifthinc/Toyota-AVC-LAN
synced 2025-06-06 15:36:47 +00:00
Setup timing better (fuses, clock speed, TCB clock speed)
This commit is contained in:
Allen Hill
parent
09bcd75811
commit
7245695bc7
@ -1,11 +1,50 @@
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cmake_minimum_required(VERSION 3.24)
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include(CMakeDependentOption)
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set(WITH_MCU OFF)
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set(AVR_MCU "attiny3216")
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set(CMAKE_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/cmake/avr-gcc-toolchain.cmake")
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project(avr-avc-lan VERSION 1 LANGUAGES C CXX ASM)
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project(avclan-mockingboard VERSION 1 LANGUAGES C CXX ASM)
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set(FREQSEL 16MHz CACHE STRING "Select the operating frequency")
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set_property(CACHE FREQSEL PROPERTY STRINGS "20MHz" "16MHz")
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if(FREQSEL MATCHES "20MHz")
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set(F_CPU 20000000L)
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set(AVR_UPLOADTOOL_BASE_OPTIONS ${AVR_UPLOADTOOL_BASE_OPTIONS} -U osccfg:w:0x2:m)
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else()
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set(F_CPU 16000000L)
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set(AVR_UPLOADTOOL_BASE_OPTIONS ${AVR_UPLOADTOOL_BASE_OPTIONS} -U osccfg:w:0x1:m)
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endif()
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option(CLK_PRESCALE "Enable the main clock prescaler")
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cmake_dependent_option(CLK_PRESCALE_DIV "Prescaler divisor" CLKCTRL_PDIV_2X_gc STRING "CLK_PRESCALE")
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if(DEFINED CACHE{CLK_PRESCALE_DIV})
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set_property(CACHE CLK_PRESCALE_DIV PROPERTY STRINGS
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CLKCTRL_PDIV_2X_gc
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CLKCTRL_PDIV_4X_gc
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CLKCTRL_PDIV_8X_gc
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CLKCTRL_PDIV_16X_gc
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CLKCTRL_PDIV_32X_gc
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CLKCTRL_PDIV_64X_gc
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CLKCTRL_PDIV_6X_gc
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CLKCTRL_PDIV_10X_gc
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CLKCTRL_PDIV_12X_gc
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CLKCTRL_PDIV_24X_gc
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CLKCTRL_PDIV_48X_gc
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)
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else()
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set(CLK_PRESCALE_DIV CLKCTRL_PDIV_2X_gc)
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endif()
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set(TCB_CLKSEL "TCB_CLKSEL_CLKDIV2_gc" CACHE STRING "Choose the clock for TCB")
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set_property(CACHE TCB_CLKSEL PROPERTY STRINGS
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TCB_CLKSEL_CLKDIV1_gc
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TCB_CLKSEL_CLKDIV2_gc
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TCB_CLKSEL_CLKTCA_gc
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)
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if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
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if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS "8.3")
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@ -61,18 +100,24 @@ if(CMAKE_BUILD_TYPE MATCHES Debug)
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set(CMAKE_C_FLAGS_DEBUG "-O0 -save-temps -g -gdwarf-3 -gstrict-dwarf")
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endif(CMAKE_BUILD_TYPE MATCHES Debug)
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add_avr_executable(sniffer
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# Set startup time to 8 ms (0x4)
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set(AVR_UPLOADTOOL_BASE_OPTIONS ${AVR_UPLOADTOOL_BASE_OPTIONS} -U syscfg1:w:0x4:m)
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add_avr_executable(mockingboard
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src/sniffer.c
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src/com232.c
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src/avclandrv.c)
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target_link_options(sniffer PUBLIC
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target_link_options(mockingboard PUBLIC
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-B "${attiny_atpack_SOURCE_DIR}/gcc/dev/${AVR_MCU}"
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)
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target_compile_definitions(sniffer PRIVATE
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F_CPU=16000000L
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target_compile_definitions(mockingboard PRIVATE
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F_CPU=${F_CPU}
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CLK_PRESCALE=$<IF:$<BOOL:${CLK_PRESCALE}>,0x01,0x00>
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CLK_PRESCALE_DIV=${CLK_PRESCALE_DIV}
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TCB_CLKSEL=${TCB_CLKSEL}
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)
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target_compile_options(sniffer PRIVATE
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target_compile_options(mockingboard PRIVATE
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--param=min-pagesize=0
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-ffunction-sections
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-fdata-sections
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@ -92,6 +92,7 @@
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#include "avclandrv.h"
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#include "com232.h"
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#include "timing.h"
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// Enable AVC bus Tx
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#define AVC_OUT_EN() \
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@ -265,12 +266,12 @@ void AVCLAN_init() {
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TCB0.CTRLB = TCB_CNTMODE_PW_gc;
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TCB0.INTCTRL = TCB_CAPT_bm;
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TCB0.EVCTRL = TCB_CAPTEI_bm;
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TCB0.CTRLA = TCB_CLKSEL_CLKDIV2_gc | TCB_ENABLE_bm;
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TCB0.CTRLA = TCB_CLKSEL | TCB_ENABLE_bm;
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// TCB1 for send bit timing
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TCB1.CTRLB = TCB_CNTMODE_INT_gc;
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TCB1.CCMP = 0xFFFF;
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TCB1.CTRLA = TCB_CLKSEL_CLKDIV2_gc | TCB_ENABLE_bm;
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TCB1.CTRLA = TCB_CLKSEL | TCB_ENABLE_bm;
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answerReq = cm_Null;
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@ -293,34 +294,36 @@ void set_AVC_logic_for(uint8_t val, uint16_t period) {
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return;
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}
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uint8_t AVCLAN_sendbit_start() {
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set_AVC_logic_for(1, 1328); // 166 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, 152); // 19 us @ 125 ns tick (for F_CPU = 16MHz)
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return 1;
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void AVCLAN_sendbit_start() {
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set_AVC_logic_for(0, AVCLAN_STARTBIT_LOGIC_0); // 166 us
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set_AVC_logic_for(1, AVCLAN_STARTBIT_LOGIC_1); // 19 us
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}
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void AVCLAN_sendbit_1() {
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set_AVC_logic_for(1, 164); // 20.5 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, 152); // 19 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, AVCLAN_BIT1_LOGIC_0); // 20.5 us
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set_AVC_logic_for(1, AVCLAN_BIT1_LOGIC_1); // 19 us
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}
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void AVCLAN_sendbit_0() {
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set_AVC_logic_for(1, 272); // 34 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, 44); // 5.5 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, AVCLAN_BIT0_LOGIC_0); // 34 us
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set_AVC_logic_for(1, AVCLAN_BIT0_LOGIC_1); // 5.5 us
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}
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void AVCLAN_sendbit_ACK() {
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TCB1.CNT = 0;
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// Wait for controller to begin ACK bit
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while (INPUT_IS_CLEAR) {
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if (TCB1.CNT >= 900)
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return; // max wait time
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// Wait for approx the length of a bit; any longer and something has clearly
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// gone wrong
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if (TCB1.CNT >= AVCLAN_BIT_LENGTH)
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return;
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}
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AVC_OUT_EN();
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set_AVC_logic_for(1, 272); // 34 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, 44); // 5.5 us @ 125 ns tick (for F_CPU = 16MHz)
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set_AVC_logic_for(0, AVCLAN_BIT0_LOGIC_0); // 34 us
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set_AVC_logic_for(1, AVCLAN_BIT0_LOGIC_1); // 5.5 us
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AVC_OUT_DIS();
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}
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@ -395,7 +398,7 @@ uint8_t AVCLAN_sendbyte(const uint8_t *byte) {
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ISR(TCB0_INT_vect) {
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// If input was set for less than 26 us (a generous half period), bit was a 1
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if (TCB0.CCMP < 208) {
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if (TCB0.CCMP < (uint16_t)AVCLAN_READBIT_THRESHOLD) {
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READING_BYTE++;
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READING_PARITY++;
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}
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@ -418,7 +421,15 @@ uint8_t AVCLAN_readbitsi(uint8_t *bits, uint8_t len) {
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READING_NBITS = len;
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sei();
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while (READING_NBITS != 0) {};
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TCB1.CNT = 0;
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while (READING_NBITS != 0) {
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// Duration of `len` bits + 10%
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if (TCB1.CNT > (((uint16_t)AVCLAN_BIT_LENGTH * 11 * len) / 10)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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}
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};
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cli();
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*bits = READING_BYTE;
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@ -448,7 +459,15 @@ uint8_t AVCLAN_readbyte(uint8_t *byte) {
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READING_NBITS = 8;
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sei();
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while (READING_NBITS != 0) {};
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TCB1.CNT = 0;
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while (READING_NBITS != 0) {
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// Duration of byte + 10%
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if (TCB1.CNT > (((uint16_t)AVCLAN_BIT_LENGTH * 11 * 8) / 10)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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}
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};
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cli();
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*byte = READING_BYTE;
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@ -459,20 +478,19 @@ uint8_t AVCLAN_readbyte(uint8_t *byte) {
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}
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uint8_t AVCLAN_readbit_ACK() {
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set_AVC_logic_for(1, 152); // 34 us @ 125 ns tick (for F_CPU = 16MHz)
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AVC_SET_LOGICAL_0(); // Replace with AVC_ReleaseLine?
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AVC_OUT_DIS(); // switch to read mode
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TCB1.CNT = 0;
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set_AVC_logic_for(0, AVCLAN_BIT1_LOGIC_0); // 20.5 us
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AVC_SET_LOGICAL_1();
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AVC_OUT_DIS();
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while (1) {
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if (INPUT_IS_SET && (TCB1.CNT > 208))
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break; // Make sure INPUT is not still set from us
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// Line of experimentation: Try changing TCNT0 comparison value or remove
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// check entirely
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if (TCB1.CNT > 300)
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return 1; // Not sure if this fix is intent correct
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if (INPUT_IS_SET && (TCB1.CNT > AVCLAN_READBIT_THRESHOLD))
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break; // ACK
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if (TCB1.CNT > AVCLAN_BIT_LENGTH)
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return 1; // NAK
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}
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// Check/wait in case we get here before peripheral finishes ACK bit
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while (INPUT_IS_SET) {}
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AVC_OUT_EN(); // back to write mode
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return 0;
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@ -669,7 +687,8 @@ uint8_t AVCLAN_sendframe(const AVCLAN_frame_t *frame) {
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TCB1.CNT = 0;
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do {
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while (INPUT_IS_CLEAR) {
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if (TCB1.CNT >= 900)
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// Wait for 120% of a bit length
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if (TCB1.CNT >= (uint16_t)(AVCLAN_BIT_LENGTH * 12 / 10))
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break;
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}
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if (TCB1.CNT > 864)
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@ -23,6 +23,7 @@
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/sfr_defs.h>
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#include <avr/xmega.h>
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#include <stdint.h>
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#include "avclandrv.h"
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@ -217,6 +218,8 @@ void Setup() {
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printAllFrames = 1;
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echoCharacters = 1;
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_PROTECTED_WRITE(CLKCTRL.MCLKCTRLB, (CLK_PRESCALE | CLK_PRESCALE_DIV));
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general_GPIO_init();
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// Setup RTC as 1 sec periodic timer
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51
src/timing.h
Normal file
51
src/timing.h
Normal file
@ -0,0 +1,51 @@
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#ifndef _TIMING_HPP_
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#define _TIMING_HPP_
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#if CLK_PRESCALE == 0x01
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#error "Not implemented"
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#else
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#if F_CPU == 20000000L
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#define CPU_CYCLE 50
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#elif F_CPU == 16000000L
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#define CPU_CYCLE 62.5
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#else
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#error "Not implemented"
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#endif
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#ifndef TCB_CLKSEL_CLKDIV1_gc
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#define TCB_CLKSEL_CLKDIV1_gc (0x00 << 1)
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#endif
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#ifndef TCB_CLKSEL_CLKDIV2_gc
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#define TCB_CLKSEL_CLKDIV2_gc (0x01 << 1)
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#endif
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#ifndef TCB_CLKSEL_CLKTCA_gc
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#define TCB_CLKSEL_CLKTCA_gc (0x02 << 1)
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#endif
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#if TCB_CLKSEL == TCB_CLKSEL_CLKDIV1_gc
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#define TCB_TICK (CPU_CYCLE)
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#elif TCB_CLKSEL == TCB_CLKSEL_CLKDIV2_gc
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#define TCB_TICK (CPU_CYCLE * 2)
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#elif TCB_CLKSEL == TCB_CLKSEL_CLKTCA_gc
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#error "Not implemented"
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#endif
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#define AVCLAN_STARTBIT_LOGIC_0 (166e3 / TCB_TICK)
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#define AVCLAN_STARTBIT_LOGIC_1 (19e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_0 (20.5e3 / TCB_TICK)
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#define AVCLAN_BIT1_LOGIC_1 (19e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_0 (34e3 / TCB_TICK)
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#define AVCLAN_BIT0_LOGIC_1 (5.5e3 / TCB_TICK)
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#define AVCLAN_READBIT_THRESHOLD (26e3 / TCB_TICK)
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#define AVCLAN_BIT_LENGTH (39.5e3 / TCB_TICK)
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#endif
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#endif
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