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Initial adaptations for avrxmega3

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This commit is contained in:
Allen Hill 2023-09-17 18:08:38 -04:00
parent 80e971b978
commit 5ce848f7dd
2 changed files with 693 additions and 201 deletions
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426
vendor/jnk0le-AVR-UART-lib/usart.c vendored
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@ -108,25 +108,41 @@ void uart0_reinit(uint16_t ubrr_value) {
#endif #endif
UCSR0B_REGISTER = 0; // flush all hardware buffers UCSR0B_REGISTER = 0; // flush all hardware buffers
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER = 0;
#endif
//(writing TXENn to zero) will not become effective until ongoing and pending //(writing TXENn to zero) will not become effective until ongoing and pending
//transmissions are completed // transmissions are completed
UBRR0L_REGISTER = (uint8_t)ubrr_value; UBRR0L_REGISTER = (uint8_t)ubrr_value;
UBRR0H_REGISTER = (ubrr_value >> 8); UBRR0H_REGISTER = (ubrr_value >> 8);
#ifdef USART0_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART0_MPCM_MODE #if (!defined(NO_RX0_INTERRUPT) && !defined(NO_TX0_INTERRUPT))
UCSR0A_REGISTER = (1 << U2X0_BIT) | (1 << MPCM0_BIT); #ifdef USART0_RS485_MODE
#else UCSR0A_REGISTER = (1 << RXCIE0_BIT) | (1 << TXCIE0_BIT) | (1 << RS485_BIT);
UCSR0A_REGISTER = (1 << U2X0_BIT); // enable double speed #else
UCSR0A_REGISTER = (1 << RXCIE0_BIT);
#endif
#endif
#else
#ifdef USART0_U2X_SPEED
#ifdef USART0_MPCM_MODE
UCSR0A_REGISTER = (1 << U2X0_BIT) | (1 << MPCM0_BIT);
#else
UCSR0A_REGISTER = (1 << U2X0_BIT); // enable double speed
#endif
#elif defined(USART0_MPCM_MODE)
UCSR0A_REGISTER |= (1 << MPCM0_BIT);
#endif #endif
#elif defined(USART0_MPCM_MODE)
UCSR0A_REGISTER = (1 << MPCM0_BIT);
#endif #endif
UCSR0B_REGISTER = USART0_CONFIG_B; UCSR0B_REGISTER = USART0_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART0_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR0C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
RTS0_DDR |= (1 << RTS0_IONUM); RTS0_DDR |= (1 << RTS0_IONUM);
@ -147,25 +163,41 @@ void uart1_reinit(uint16_t ubrr_value) {
#endif #endif
UCSR1B_REGISTER = 0; // flush all hardware buffers UCSR1B_REGISTER = 0; // flush all hardware buffers
#if __AVR_ARCH__ == 103
UCSR1A_REGISTER = 0;
#endif
//(writing TXENn to zero) will not become effective until ongoing and pending //(writing TXENn to zero) will not become effective until ongoing and pending
//transmissions are completed // transmissions are completed
UBRR1L_REGISTER = (uint8_t)ubrr_value; UBRR1L_REGISTER = (uint8_t)ubrr_value;
UBRR1H_REGISTER = (ubrr_value >> 8); UBRR1H_REGISTER = (ubrr_value >> 8);
#ifdef USART1_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART1_MPCM_MODE #if (!defined(NO_RX1_INTERRUPT) && !defined(NO_TX1_INTERRUPT))
UCSR1A_REGISTER = (1 << U2X1_BIT) | (1 << MPCM1_BIT); #ifdef USART1_RS485_MODE
#else UCSR1A_REGISTER = (1 << RXCIE1_BIT) | (1 << TXCIE1_BIT) | (1 << RS485_BIT);
UCSR1A_REGISTER = (1 << U2X1_BIT); // enable double speed #else
UCSR1A_REGISTER = (1 << RXCIE1_BIT);
#endif
#endif
#else
#ifdef USART1_U2X_SPEED
#ifdef USART1_MPCM_MODE
UCSR1A_REGISTER = (1 << U2X1_BIT) | (1 << MPCM1_BIT);
#else
UCSR1A_REGISTER = (1 << U2X1_BIT); // enable double speed
#endif
#elif defined(USART1_MPCM_MODE)
UCSR1A_REGISTER |= (1 << MPCM1_BIT);
#endif #endif
#elif defined(USART1_MPCM_MODE)
UCSR1A_REGISTER = (1 << MPCM1_BIT);
#endif #endif
UCSR1B_REGISTER = USART1_CONFIG_B; UCSR1B_REGISTER = USART1_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART1_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR1C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART1_USE_SOFT_RTS #ifdef USART1_USE_SOFT_RTS
RTS1_DDR |= (1 << RTS1_IONUM); RTS1_DDR |= (1 << RTS1_IONUM);
@ -186,25 +218,41 @@ void uart2_reinit(uint16_t ubrr_value) {
#endif #endif
UCSR2B_REGISTER = 0; // flush all hardware buffers UCSR2B_REGISTER = 0; // flush all hardware buffers
#if __AVR_ARCH__ == 103
UCSR2A_REGISTER = 0;
#endif
//(writing TXENn to zero) will not become effective until ongoing and pending //(writing TXENn to zero) will not become effective until ongoing and pending
//transmissions are completed // transmissions are completed
UBRR2L_REGISTER = (uint8_t)ubrr_value; UBRR2L_REGISTER = (uint8_t)ubrr_value;
UBRR2H_REGISTER = (ubrr_value >> 8); UBRR2H_REGISTER = (ubrr_value >> 8);
#ifdef USART2_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART2_MPCM_MODE #if (!defined(NO_RX2_INTERRUPT) && !defined(NO_TX2_INTERRUPT))
UCSR2A_REGISTER = (1 << U2X2_BIT) | (1 << MPCM2_BIT); #ifdef USART2_RS485_MODE
#else UCSR2A_REGISTER = (1 << RXCIE2_BIT) | (1 << TXCIE2_BIT) | (1 << RS485_BIT);
UCSR2A_REGISTER = (1 << U2X2_BIT); // enable double speed #else
UCSR2A_REGISTER = (1 << RXCIE2_BIT);
#endif
#endif
#else
#ifdef USART2_U2X_SPEED
#ifdef USART2_MPCM_MODE
UCSR2A_REGISTER = (1 << U2X2_BIT) | (1 << MPCM2_BIT);
#else
UCSR2A_REGISTER = (1 << U2X2_BIT); // enable double speed
#endif
#elif defined(USART2_MPCM_MODE)
UCSR2A_REGISTER |= (1 << MPCM2_BIT);
#endif #endif
#elif defined(USART2_MPCM_MODE)
UCSR2A_REGISTER = (1 << MPCM2_BIT);
#endif #endif
UCSR2B_REGISTER = USART2_CONFIG_B; UCSR2B_REGISTER = USART2_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART2_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR2C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART2_USE_SOFT_RTS #ifdef USART2_USE_SOFT_RTS
RTS2_DDR |= (1 << RTS2_IONUM); RTS2_DDR |= (1 << RTS2_IONUM);
@ -225,22 +273,38 @@ void uart3_reinit(uint16_t ubrr_value) {
#endif #endif
UCSR3B_REGISTER = 0; // flush all hardware buffers UCSR3B_REGISTER = 0; // flush all hardware buffers
#if __AVR_ARCH__ == 103
UCSR3A_REGISTER = 0;
#endif
UBRR3L_REGISTER = (uint8_t)ubrr_value; UBRR3L_REGISTER = (uint8_t)ubrr_value;
UBRR3H_REGISTER = (ubrr_value >> 8); UBRR3H_REGISTER = (ubrr_value >> 8);
#ifdef USART3_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART3_MPCM_MODE #if (!defined(NO_RX3_INTERRUPT) && !defined(NO_TX3_INTERRUPT))
UCSR3A_REGISTER = (1 << U2X3_BIT) | (1 << MPCM3_BIT); #ifdef USART3_RS485_MODE
#else UCSR3A_REGISTER = (1 << RXCIE3_BIT) | (1 << TXCIE3_BIT) | (1 << RS485_BIT);
UCSR3A_REGISTER = (1 << U2X3_BIT); // enable double speed #else
UCSR3A_REGISTER = (1 << RXCIE3_BIT);
#endif
#endif
#else
#ifdef USART3_U2X_SPEED
#ifdef USART3_MPCM_MODE
UCSR3A_REGISTER = (1 << U2X3_BIT) | (1 << MPCM3_BIT);
#else
UCSR3A_REGISTER = (1 << U2X3_BIT); // enable double speed
#endif
#elif defined(USART3_MPCM_MODE)
UCSR3A_REGISTER |= (1 << MPCM3_BIT);
#endif #endif
#elif defined(USART3_MPCM_MODE)
UCSR3A_REGISTER = (1 << MPCM3_BIT);
#endif #endif
UCSR3B_REGISTER = USART3_CONFIG_B; UCSR3B_REGISTER = USART3_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART3_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR3C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART3_USE_SOFT_RTS #ifdef USART3_USE_SOFT_RTS
RTS3_DDR |= (1 << RTS3_IONUM); RTS3_DDR |= (1 << RTS3_IONUM);
@ -271,7 +335,13 @@ void uart0_putc(char data) {
#ifdef USART0_USE_SOFT_CTS #ifdef USART0_USE_SOFT_CTS
if (!(CTS0_PIN & (1 << CTS0_IONUM))) if (!(CTS0_PIN & (1 << CTS0_IONUM)))
#endif #endif
if (tmp_tx_Tail == tmp_tx_Head && (UCSR0A_REGISTER & UDRE0_BIT)) { if (tmp_tx_Tail == tmp_tx_Head &&
#if __AVR_ARCH__ == 103
(USR0_REGISTER & UDRE0_BIT)
#else
(UCSR0A_REGISTER & UDRE0_BIT)
#endif
) {
UDR0_REGISTER = data; UDR0_REGISTER = data;
return; return;
} }
@ -280,16 +350,14 @@ void uart0_putc(char data) {
while (tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer while (tmp_tx_Tail == tmp_tx_Head) // wait for free space in buffer
{ {
tmp_tx_Tail = // for faster pass through, results in a little bigger code
tx0_Tail; // for faster pass through, results in a little bigger code tmp_tx_Tail = tx0_Tail;
} }
#else #else // !USART0_PUTC_FAST_INSERTIONS
register uint8_t tmp_tx_Head = // calculate new position of TX head in buffer
(tx0_Head + 1) & register uint8_t tmp_tx_Head = (tx0_Head + 1) & TX0_BUFFER_MASK;
TX0_BUFFER_MASK; // calculate new position of TX head in buffer
while (tx0_Tail == tmp_tx_Head) while (tx0_Tail == tmp_tx_Head) {} // wait for free space in buffer
; // wait for free space in buffer
#endif #endif
tx0_buffer[tmp_tx_Head] = data; tx0_buffer[tmp_tx_Head] = data;
@ -305,7 +373,7 @@ void uart0_putc(char data) {
if (!(CTS0_PIN & (1 << CTS0_IONUM))) if (!(CTS0_PIN & (1 << CTS0_IONUM)))
#endif #endif
{ {
UCSR0B_REGISTER |= (1 << UDRIE0_BIT); // enable UDRE interrupt uart0_enable_UDREI(); // enable UDRE interrupt
} }
} }
} }
@ -346,12 +414,12 @@ void uart0_putc(char data) {
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
#ifdef USART0_IN_IO_ADDRESS_SPACE #ifdef USART0_IN_IO_ADDRESS_SPACE
"sbis %M[UCSRA_reg_IO], %M[udre_bit] \n\t" "sbis %M[UDRE_reg_IO], %M[udre_bit] \n\t"
#elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE) #elif defined(USART0_IN_UPPER_IO_ADDRESS_SPACE)
"in r26, %M[UCSRA_reg_IO] \n\t" "in r26, %M[UDRE_reg_IO] \n\t"
"sbrs r26, %M[udre_bit] \n\t" "sbrs r26, %M[udre_bit] \n\t"
#else #else
"lds r26, %M[UCSRA_reg] \n\t" "lds r26, %M[UDRE_reg] \n\t"
"sbrs r26, %M[udre_bit] \n\t" "sbrs r26, %M[udre_bit] \n\t"
#endif #endif
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
@ -384,8 +452,13 @@ void uart0_putc(char data) {
[cts_port] "M"(_SFR_IO_ADDR(CTS0_PORT)), [cts_pin] "M"(CTS0_IONUM), [cts_port] "M"(_SFR_IO_ADDR(CTS0_PORT)), [cts_pin] "M"(CTS0_IONUM),
#endif #endif
[mask] "M"(TX0_BUFFER_MASK), [mask] "M"(TX0_BUFFER_MASK),
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)), [UDRE_reg] "n"(_SFR_MEM_ADDR(USR0_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(USR0_REGISTER)),
#else
[UDRE_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)),
#endif
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)),
[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)), [UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)),
[udre_bit] "M"(UDRE0_BIT) [udre_bit] "M"(UDRE0_BIT)
@ -464,7 +537,11 @@ void uart0_putc(char data) {
#endif #endif
: // outputs : // outputs
: // inputs : // inputs
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE0_BIT) [udrie_bit] "M"(UDRIE0_BIT)
: // clobbers : // clobbers
"r25"); "r25");
@ -478,9 +555,9 @@ void uart0_putc(char data) {
// register, make sure it is not affected by the compiler // register, make sure it is not affected by the compiler
} }
char uart0_putc_(char data) __attribute__(( // alias for uart_putc that returns passed argument unaffected by omitting any
alias("uart0_putc"))); // alias for uart_putc that returns passed argument // existent rule
// unaffected by omitting any existent rule char uart0_putc_(char data) __attribute__((alias("uart0_putc")));
#endif // USART_NO_ABI_BREAKING_PREMATURES #endif // USART_NO_ABI_BREAKING_PREMATURES
//****************************************************************** //******************************************************************
@ -676,22 +753,23 @@ void uart0_putstrl(char *string, uint8_t BytesToWrite) {
} }
#endif // USART_NO_ABI_BREAKING_PREMATURES #endif // USART_NO_ABI_BREAKING_PREMATURES
//****************************************************************** //******************************************************************
// Function : Send string from flash memory. // Function : Send string from flash memory.
// Arguments : Pointer to string placed in flash memory. // Arguments : Pointer to string placed in flash memory.
// Return : none // Return : none
//****************************************************************** //******************************************************************
#ifdef USART_NO_ABI_BREAKING_PREMATURES #if __AVR_ARCH__ != 103
#ifdef USART_NO_ABI_BREAKING_PREMATURES
void uart0_puts_p(const __flash char *string) { void uart0_puts_p(const __flash char *string) {
#ifndef USART0_NOT_ACCESIBLE_FROM_CBI // tiny 102/104 #ifndef USART0_NOT_ACCESIBLE_FROM_CBI // tiny 102/104
register char c; register char c;
while ((c = *string++)) while ((c = *string++))
uart0_putc(c); uart0_putc(c);
#endif #endif
} }
#else // !USART_NO_ABI_BREAKING_PREMATURES #else // !USART_NO_ABI_BREAKING_PREMATURES
void uart0_puts_p(const __flash char *string) { void uart0_puts_p(const __flash char *string) {
#if !defined(__AVR_ATtiny102__) || !defined(__AVR_ATtiny104__) #if !defined(__AVR_ATtiny102__) || !defined(__AVR_ATtiny104__)
asm volatile( asm volatile(
"\n\t" "\n\t"
@ -709,9 +787,10 @@ void uart0_puts_p(const __flash char *string) {
: // clobbers : // clobbers
"r24", "r25", "r26", "r27" // uart_putc() "r24", "r25", "r26", "r27" // uart_putc()
); );
#endif #endif
} }
#endif // USART_NO_ABI_BREAKING_PREMATURES #endif // USART_NO_ABI_BREAKING_PREMATURES
#endif
//****************************************************************** //******************************************************************
// Function : Send integer formated into ASCI string (base 10). // Function : Send integer formated into ASCI string (base 10).
@ -922,13 +1001,19 @@ void uart0_flush(void) {
//****************************************************************** //******************************************************************
#ifdef USART0_MPCM_MODE #ifdef USART0_MPCM_MODE
void uart0_mpcm_transmit_addres_Frame(uint8_t dat) { void uart0_mpcm_transmit_addres_Frame(uint8_t dat) {
while (tx0_Tail != tx0_Head) while (tx0_Tail != tx0_Head) {}
; #if __AVR_ARCH__ == 103
UDR0H_REGISTER |= (1 << TXB80_BIT);
#else
UCSR0B_REGISTER |= (1 << TXB80_BIT); UCSR0B_REGISTER |= (1 << TXB80_BIT);
#endif
uart_putc(dat); uart_putc(dat);
while (tx0_Tail != tx0_Head) while (tx0_Tail != tx0_Head) {}
; #if __AVR_ARCH__ == 103
UDR0H_REGISTER &= ~(1 << TXB80_BIT); // not sure if necessary
#else
UCSR0B_REGISTER &= ~(1 << TXB80_BIT); // not sure if necessary UCSR0B_REGISTER &= ~(1 << TXB80_BIT); // not sure if necessary
#endif
} }
#endif #endif
#endif // NO_TX0_INTERRUPT #endif // NO_TX0_INTERRUPT
@ -1024,9 +1109,9 @@ void uart1_putc(char data) {
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
#ifdef USART1_IN_IO_ADDRESS_SPACE #ifdef USART1_IN_IO_ADDRESS_SPACE
"sbis %M[UCSRA_reg_IO], %M[udre_bit] \n\t" "sbis %M[UDRE_reg_IO], %M[udre_bit] \n\t"
#else #else
"lds r26, %M[UCSRA_reg] \n\t" "lds r26, %M[UDRE_reg] \n\t"
"sbrs r26, %M[udre_bit] \n\t" "sbrs r26, %M[udre_bit] \n\t"
#endif #endif
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
@ -1058,8 +1143,13 @@ void uart1_putc(char data) {
[cts_port] "M"(_SFR_IO_ADDR(CTS1_PORT)), [cts_pin] "M"(CTS1_IONUM), [cts_port] "M"(_SFR_IO_ADDR(CTS1_PORT)), [cts_pin] "M"(CTS1_IONUM),
#endif #endif
[mask] "M"(TX1_BUFFER_MASK), [mask] "M"(TX1_BUFFER_MASK),
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)), [UDRE_reg] "n"(_SFR_MEM_ADDR(USR1_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(USR1_REGISTER)),
#else
[UDRE_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)),
#endif
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)),
[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)), [UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)),
[udre_bit] "M"(UDRE1_BIT) [udre_bit] "M"(UDRE1_BIT)
@ -1122,7 +1212,11 @@ void uart1_putc(char data) {
"sts %M[control_reg], r25 \n\t" "sts %M[control_reg], r25 \n\t"
: // outputs : // outputs
: // inputs : // inputs
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE1_BIT) [udrie_bit] "M"(UDRIE1_BIT)
: // clobbers : // clobbers
"r25"); "r25");
@ -1562,7 +1656,7 @@ void uart2_putc(char data) {
"cpse r27, %[head] \n\t" "cpse r27, %[head] \n\t"
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
"lds r26, %M[UCSRA_reg] \n\t" "lds r26, %M[UDRE_reg] \n\t"
"sbrs r26, %M[udre_bit] \n\t" "sbrs r26, %M[udre_bit] \n\t"
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
@ -1589,8 +1683,13 @@ void uart2_putc(char data) {
[cts_port] "M"(_SFR_IO_ADDR(CTS2_PORT)), [cts_pin] "M"(CTS2_IONUM), [cts_port] "M"(_SFR_IO_ADDR(CTS2_PORT)), [cts_pin] "M"(CTS2_IONUM),
#endif #endif
[mask] "M"(TX2_BUFFER_MASK), [mask] "M"(TX2_BUFFER_MASK),
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR2A_REGISTER)), [UDRE_reg] "n"(_SFR_MEM_ADDR(USR2_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(USR2_REGISTER)),
#else
[UDRE_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(UCSR2A_REGISTER)),
#endif
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)),
[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR2_REGISTER)), [UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR2_REGISTER)),
[udre_bit] "M"(UDRE2_BIT) [udre_bit] "M"(UDRE2_BIT)
@ -1650,7 +1749,11 @@ void uart2_putc(char data) {
"sts %M[control_reg], r25 \n\t" "sts %M[control_reg], r25 \n\t"
: // outputs : // outputs
: // inputs : // inputs
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE2_BIT) [udrie_bit] "M"(UDRIE2_BIT)
: // clobbers : // clobbers
"r25"); "r25");
@ -2088,7 +2191,7 @@ void uart3_putc(char data) {
"cpse r27, %[head] \n\t" "cpse r27, %[head] \n\t"
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
"lds r26, %M[UCSRA_reg] \n\t" "lds r26, %M[UDRE_reg] \n\t"
"sbrs r26, %M[udre_bit] \n\t" "sbrs r26, %M[udre_bit] \n\t"
"rjmp normal_insert_%= \n\t" "rjmp normal_insert_%= \n\t"
@ -2115,8 +2218,13 @@ void uart3_putc(char data) {
[cts_port] "M"(_SFR_IO_ADDR(CTS3_PORT)), [cts_pin] "M"(CTS3_IONUM), [cts_port] "M"(_SFR_IO_ADDR(CTS3_PORT)), [cts_pin] "M"(CTS3_IONUM),
#endif #endif
[mask] "M"(TX2_BUFFER_MASK), [mask] "M"(TX2_BUFFER_MASK),
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR3A_REGISTER)), [UDRE_reg] "n"(_SFR_MEM_ADDR(USR3_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(USR3_REGISTER)),
#else
[UDRE_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
[UDRE_reg_IO] "M"(_SFR_IO_ADDR(UCSR3A_REGISTER)),
#endif
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)),
[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR3_REGISTER)), [UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR3_REGISTER)),
[udre_bit] "M"(UDRE3_BIT) [udre_bit] "M"(UDRE3_BIT)
@ -2176,7 +2284,11 @@ void uart3_putc(char data) {
"sts %M[control_reg], r25 \n\t" "sts %M[control_reg], r25 \n\t"
: // outputs : // outputs
: // inputs : // inputs
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE3_BIT) [udrie_bit] "M"(UDRIE3_BIT)
: // clobbers : // clobbers
"r25"); "r25");
@ -2549,15 +2661,22 @@ char uart0_getc(void) {
rx0_Tail = tmp_rx_Tail; rx0_Tail = tmp_rx_Tail;
#ifdef USART0_EXTEND_RX_BUFFER #ifdef USART0_EXTEND_RX_BUFFER
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << RXCIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << RXCIE0_BIT); UCSR0B_REGISTER |= (1 << RXCIE0_BIT);
#endif
#endif #endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
if (RTS0_PORT & (1 << RTS0_IONUM)) if (RTS0_PORT & (1 << RTS0_IONUM))
if (!(UCSR0A_REGISTER & #if __AVR_ARCH__ == 103
(1 << RXC0_BIT))) // isr has fired so check if there is no unread data if (!(USR0_REGISTER & (1 << RXC0_BIT)))
// in UDR (if missed then next read will release RTS #else
// line) // isr has fired so check if there is no unread data in UDR (if missed
// then next read will release RTS line)
if (!(UCSR0A_REGISTER & (1 << RXC0_BIT)))
#endif
RTS0_PORT &= ~(1 << RTS0_IONUM); RTS0_PORT &= ~(1 << RTS0_IONUM);
#endif #endif
@ -2617,15 +2736,22 @@ char uart0_getc(void) {
rx0_Tail = tmp_rx_Tail; rx0_Tail = tmp_rx_Tail;
#ifdef USART0_EXTEND_RX_BUFFER #ifdef USART0_EXTEND_RX_BUFFER
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << RXCIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << RXCIE0_BIT); UCSR0B_REGISTER |= (1 << RXCIE0_BIT);
#endif
#endif #endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
if (RTS0_PORT & (1 << RTS0_IONUM)) if (RTS0_PORT & (1 << RTS0_IONUM))
if (!(UCSR0A_REGISTER & #if __AVR_ARCH__ == 103
(1 << RXC0_BIT))) // isr has fired so check if there is no unread data if (!(USR0_REGISTER & (1 << RXC0_BIT)))
// in UDR (if missed then next read will release RTS #else
// line) // isr has fired so check if there is no unread data in UDR (if missed
// then next read will release RTS line)
if (!(UCSR0A_REGISTER & (1 << RXC0_BIT)))
#endif
RTS0_PORT &= ~(1 << RTS0_IONUM); RTS0_PORT &= ~(1 << RTS0_IONUM);
#endif #endif
@ -2974,12 +3100,22 @@ int16_t uart0_getData(void) {
rx0_Tail = tmp_rx_Tail; rx0_Tail = tmp_rx_Tail;
#ifdef USART0_EXTEND_RX_BUFFER #ifdef USART0_EXTEND_RX_BUFFER
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << RXCIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << RXCIE0_BIT); UCSR0B_REGISTER |= (1 << RXCIE0_BIT);
#endif
#endif #endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
if (RTS0_PORT & (1 << RTS0_IONUM)) if (RTS0_PORT & (1 << RTS0_IONUM))
#if __AVR_ARCH__ == 103
if (!(USR0_REGISTER & (1 << RXC0_BIT)))
#else
// isr has fired so check if there is no unread data in UDR (if missed
// then next read will release RTS line)
if (!(UCSR0A_REGISTER & (1 << RXC0_BIT))) if (!(UCSR0A_REGISTER & (1 << RXC0_BIT)))
#endif
RTS0_PORT &= ~(1 << RTS0_IONUM); RTS0_PORT &= ~(1 << RTS0_IONUM);
#endif #endif
@ -3023,12 +3159,22 @@ int16_t uart0_getData(void) {
rx0_Tail = tmp_rx_Tail; rx0_Tail = tmp_rx_Tail;
#ifdef USART0_EXTEND_RX_BUFFER #ifdef USART0_EXTEND_RX_BUFFER
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << RXCIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << RXCIE0_BIT); UCSR0B_REGISTER |= (1 << RXCIE0_BIT);
#endif
#endif #endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
if (RTS0_PORT & (1 << RTS0_IONUM)) if (RTS0_PORT & (1 << RTS0_IONUM))
#if __AVR_ARCH__ == 103
if (!(USR0_REGISTER & (1 << RXC0_BIT)))
#else
// isr has fired so check if there is no unread data in UDR (if missed
// then next read will release RTS line)
if (!(UCSR0A_REGISTER & (1 << RXC0_BIT))) if (!(UCSR0A_REGISTER & (1 << RXC0_BIT)))
#endif
RTS0_PORT &= ~(1 << RTS0_IONUM); RTS0_PORT &= ~(1 << RTS0_IONUM);
#endif #endif
@ -3056,12 +3202,22 @@ uint8_t uart0_LoadData(uint8_t *data) {
rx0_Tail = tmp_rx_Tail; rx0_Tail = tmp_rx_Tail;
#ifdef USART0_EXTEND_RX_BUFFER #ifdef USART0_EXTEND_RX_BUFFER
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << RXCIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << RXCIE0_BIT); UCSR0B_REGISTER |= (1 << RXCIE0_BIT);
#endif
#endif #endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
if (RTS0_PORT & (1 << RTS0_IONUM)) if (RTS0_PORT & (1 << RTS0_IONUM))
#if __AVR_ARCH__ == 103
if (!(USR0_REGISTER & (1 << RXC0_BIT)))
#else
// isr has fired so check if there is no unread data in UDR (if missed
// then next read will release RTS line)
if (!(UCSR0A_REGISTER & (1 << RXC0_BIT))) if (!(UCSR0A_REGISTER & (1 << RXC0_BIT)))
#endif
RTS0_PORT &= ~(1 << RTS0_IONUM); RTS0_PORT &= ~(1 << RTS0_IONUM);
#endif #endif
@ -4792,8 +4948,13 @@ ISR(UDRE0_INTERRUPT, ISR_NAKED) {
: // input operands : // input operands
TX0_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)), TX0_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)),
#if __AVR_ARCH__ == 103
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
#else
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)), [control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE0_BIT), [mask] "M"(TX0_BUFFER_MASK) [udrie_bit] "M"(UDRIE0_BIT), [mask] "M"(TX0_BUFFER_MASK)
// no clobbers // no clobbers
@ -4930,9 +5091,9 @@ ISR(RX0_INTERRUPT, ISR_NAKED) {
#if defined(USART0_MPCM_MODE) && !defined(MPCM0_MASTER_ONLY) #if defined(USART0_MPCM_MODE) && !defined(MPCM0_MASTER_ONLY)
#ifdef USART0_IN_IO_ADDRESS_SPACE #ifdef USART0_IN_IO_ADDRESS_SPACE
"in r31, %M[UCSRA_reg_IO] \n\t" "in r31, %M[MPCM_reg_IO] \n\t"
#else #else
"lds r31, %M[UCSRA_reg] \n\t" "lds r31, %M[MPCM_reg] \n\t"
#endif #endif
"sbrs r31, %M[mpcm_bit] \n\t" "sbrs r31, %M[mpcm_bit] \n\t"
@ -4947,9 +5108,9 @@ ISR(RX0_INTERRUPT, ISR_NAKED) {
"andi r31, ~(1<<%M[mpcm_bit]) \n\t" "andi r31, ~(1<<%M[mpcm_bit]) \n\t"
#ifdef USART0_IN_IO_ADDRESS_SPACE #ifdef USART0_IN_IO_ADDRESS_SPACE
"out %M[UCSRA_reg_IO], r31 \n\t" "out %M[MPCM_reg_IO], r31 \n\t"
#else #else
"sts %M[UCSRA_reg], r31 \n\t" "sts %M[MPCM_reg], r31 \n\t"
#endif #endif
"USART0_RX_CONTINUE: " "USART0_RX_CONTINUE: "
@ -5044,9 +5205,14 @@ ISR(RX0_INTERRUPT, ISR_NAKED) {
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: // input operands : // input operands
#if __AVR_ARCH__ == 103
RX0_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(RX0_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(RX0_REGISTER)),
#else
RX0_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)), RX0_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR0_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)), [mask] "M"(RX0_BUFFER_MASK), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR0_REGISTER)),
[mpcm_address] "M"(MPCM0_ADDRESS), #endif
[mask] "M"(RX0_BUFFER_MASK), [mpcm_address] "M"(MPCM0_ADDRESS),
#ifdef MPCM0_GCALL_ADDRESS #ifdef MPCM0_GCALL_ADDRESS
[mpcm_gcall_address] "M"(MPCM0_GCALL_ADDRESS), [mpcm_gcall_address] "M"(MPCM0_GCALL_ADDRESS),
#endif #endif
@ -5054,10 +5220,17 @@ ISR(RX0_INTERRUPT, ISR_NAKED) {
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
[rts_port] "M"(_SFR_IO_ADDR(RTS0_PORT)), [rts_pin] "M"(RTS0_IONUM), [rts_port] "M"(_SFR_IO_ADDR(RTS0_PORT)), [rts_pin] "M"(RTS0_IONUM),
#endif #endif
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)), [MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)),
[MPCM_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)),
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
#else
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
[MPCM_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)),
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)), [control_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)),
#endif
[rxcie_bit] "M"(RXCIE0_BIT) [rxcie_bit] "M"(RXCIE0_BIT)
// no clobbers // no clobbers
@ -5178,8 +5351,13 @@ ISR(UDRE1_INTERRUPT, ISR_NAKED) {
: // input operands : // input operands
TX1_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)), TX1_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)),
#if __AVR_ARCH__ == 103
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
#else
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)), [control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE1_BIT), [mask] "M"(TX1_BUFFER_MASK) [udrie_bit] "M"(UDRIE1_BIT), [mask] "M"(TX1_BUFFER_MASK)
// no clobbers // no clobbers
@ -5302,9 +5480,9 @@ ISR(RX1_INTERRUPT, ISR_NAKED) {
#if defined(USART1_MPCM_MODE) && !defined(MPCM1_MASTER_ONLY) #if defined(USART1_MPCM_MODE) && !defined(MPCM1_MASTER_ONLY)
#ifdef USART1_IN_IO_ADDRESS_SPACE #ifdef USART1_IN_IO_ADDRESS_SPACE
"in r31, %M[UCSRA_reg_IO] \n\t" "in r31, %M[MPCM_reg_IO] \n\t"
#else #else
"lds r31, %M[UCSRA_reg] \n\t" "lds r31, %M[MPCM_reg] \n\t"
#endif #endif
"sbrs r31, %M[mpcm_bit] \n\t" "sbrs r31, %M[mpcm_bit] \n\t"
@ -5319,9 +5497,9 @@ ISR(RX1_INTERRUPT, ISR_NAKED) {
"andi r31, ~(1<<%M[mpcm_bit]) \n\t" "andi r31, ~(1<<%M[mpcm_bit]) \n\t"
#ifdef USART1_IN_IO_ADDRESS_SPACE #ifdef USART1_IN_IO_ADDRESS_SPACE
"out %M[UCSRA_reg_IO], r31 \n\t" "out %M[MPCM_reg_IO], r31 \n\t"
#else #else
"sts %M[UCSRA_reg], r31 \n\t" "sts %M[MPCM_reg], r31 \n\t"
#endif #endif
"USART1_RX_CONTINUE: " "USART1_RX_CONTINUE: "
@ -5397,9 +5575,14 @@ ISR(RX1_INTERRUPT, ISR_NAKED) {
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: // input operands : // input operands
#if __AVR_ARCH__ == 103
RX1_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(RX1_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(RX1_REGISTER)),
#else
RX1_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)), RX1_INPUT_OPERAND_LIST[UDR_reg_IO] "M"(_SFR_IO_ADDR(UDR1_REGISTER)),
[UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)), [mask] "M"(RX1_BUFFER_MASK), [UDR_reg] "n"(_SFR_MEM_ADDR(UDR1_REGISTER)),
[mpcm_address] "M"(MPCM1_ADDRESS), #endif
[mask] "M"(RX1_BUFFER_MASK), [mpcm_address] "M"(MPCM1_ADDRESS),
#ifdef MPCM1_GCALL_ADDRESS #ifdef MPCM1_GCALL_ADDRESS
[mpcm_gcall_address] "M"(MPCM1_GCALL_ADDRESS), [mpcm_gcall_address] "M"(MPCM1_GCALL_ADDRESS),
#endif #endif
@ -5407,10 +5590,17 @@ ISR(RX1_INTERRUPT, ISR_NAKED) {
#ifdef USART1_USE_SOFT_RTS #ifdef USART1_USE_SOFT_RTS
[rts_port] "M"(_SFR_IO_ADDR(RTS1_PORT)), [rts_pin] "M"(RTS1_IONUM), [rts_port] "M"(_SFR_IO_ADDR(RTS1_PORT)), [rts_pin] "M"(RTS1_IONUM),
#endif #endif
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRA_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)), [MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)),
[MPCM_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)),
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
#else
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
[MPCM_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)),
[control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)), [control_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)),
#endif
[rxcie_bit] "M"(RXCIE1_BIT) [rxcie_bit] "M"(RXCIE1_BIT)
// no clobbers // no clobbers
@ -5515,7 +5705,11 @@ ISR(UDRE2_INTERRUPT, ISR_NAKED) {
: // input operands : // input operands
TX2_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)), TX2_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)),
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE2_BIT), [mask] "M"(TX2_BUFFER_MASK) [udrie_bit] "M"(UDRIE2_BIT), [mask] "M"(TX2_BUFFER_MASK)
// no clobbers // no clobbers
@ -5620,7 +5814,7 @@ ISR(RX2_INTERRUPT, ISR_NAKED) {
RX2_EARLY_RECEIVE_EVENT RX2_EARLY_RECEIVE_EVENT
#if defined(USART2_MPCM_MODE) && !defined(MPCM2_MASTER_ONLY) #if defined(USART2_MPCM_MODE) && !defined(MPCM2_MASTER_ONLY)
"lds r31, %M[UCSRA_reg] \n\t" "lds r31, %M[MPCM_reg] \n\t"
"sbrs r31, %M[mpcm_bit] \n\t" "sbrs r31, %M[mpcm_bit] \n\t"
"rjmp USART2_RX_CONTINUE \n\t" "rjmp USART2_RX_CONTINUE \n\t"
@ -5633,7 +5827,7 @@ ISR(RX2_INTERRUPT, ISR_NAKED) {
"p_%=: " "p_%=: "
"andi r31, ~(1<<%M[mpcm_bit]) \n\t" "andi r31, ~(1<<%M[mpcm_bit]) \n\t"
"sts %M[UCSRA_reg], r31 \n\t" "sts %M[MPCM_reg], r31 \n\t"
"USART2_RX_CONTINUE: " "USART2_RX_CONTINUE: "
#endif #endif
@ -5700,7 +5894,11 @@ ISR(RX2_INTERRUPT, ISR_NAKED) {
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: // input operands : // input operands
#if __AVR_ARCH__ == 103
RX2_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(RX2_REGISTER)),
#else
RX2_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)), RX2_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR2_REGISTER)),
#endif
[mask] "M"(RX2_BUFFER_MASK), [mpcm_address] "M"(MPCM2_ADDRESS), [mask] "M"(RX2_BUFFER_MASK), [mpcm_address] "M"(MPCM2_ADDRESS),
#ifdef MPCM2_GCALL_ADDRESS #ifdef MPCM2_GCALL_ADDRESS
[mpcm_gcall_address] "M"(MPCM2_GCALL_ADDRESS), [mpcm_gcall_address] "M"(MPCM2_GCALL_ADDRESS),
@ -5709,8 +5907,13 @@ ISR(RX2_INTERRUPT, ISR_NAKED) {
#ifdef USART2_USE_SOFT_RTS #ifdef USART2_USE_SOFT_RTS
[rts_port] "M"(_SFR_IO_ADDR(RTS2_PORT)), [rts_pin] "M"(RTS2_IONUM), [rts_port] "M"(_SFR_IO_ADDR(RTS2_PORT)), [rts_pin] "M"(RTS2_IONUM),
#endif #endif
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)), #if __AVR_ARCH__ == 103
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
#else
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)),
#endif
[rxcie_bit] "M"(RXCIE2_BIT) [rxcie_bit] "M"(RXCIE2_BIT)
// no clobbers // no clobbers
@ -5815,7 +6018,11 @@ ISR(UDRE3_INTERRUPT, ISR_NAKED) {
: // input operands : // input operands
TX3_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)), TX3_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)),
#if __AVR_ARCH__ == 103
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
#else
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)),
#endif
[udrie_bit] "M"(UDRIE3_BIT), [mask] "M"(TX3_BUFFER_MASK) [udrie_bit] "M"(UDRIE3_BIT), [mask] "M"(TX3_BUFFER_MASK)
// no clobbers // no clobbers
@ -5920,7 +6127,7 @@ ISR(RX3_INTERRUPT, ISR_NAKED) {
RX3_EARLY_RECEIVE_EVENT RX3_EARLY_RECEIVE_EVENT
#if defined(USART3_MPCM_MODE) && !defined(MPCM3_MASTER_ONLY) #if defined(USART3_MPCM_MODE) && !defined(MPCM3_MASTER_ONLY)
"lds r31, %M[UCSRA_reg] \n\t" "lds r31, %M[MPCM_reg] \n\t"
"sbrs r31, %M[mpcm_bit] \n\t" "sbrs r31, %M[mpcm_bit] \n\t"
"rjmp USART3_RX_CONTINUE \n\t" "rjmp USART3_RX_CONTINUE \n\t"
@ -5933,7 +6140,7 @@ ISR(RX3_INTERRUPT, ISR_NAKED) {
"p_%=: " "p_%=: "
"andi r31, ~(1<<%M[mpcm_bit]) \n\t" "andi r31, ~(1<<%M[mpcm_bit]) \n\t"
"sts %M[UCSRA_reg], r31 \n\t" "sts %M[MPCM_reg], r31 \n\t"
"USART3_RX_CONTINUE: " "USART3_RX_CONTINUE: "
#endif #endif
@ -6000,7 +6207,11 @@ ISR(RX3_INTERRUPT, ISR_NAKED) {
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: // input operands : // input operands
#if __AVR_ARCH__ == 103
RX3_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(RX3_REGISTER)),
#else
RX3_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)), RX3_INPUT_OPERAND_LIST[UDR_reg] "n"(_SFR_MEM_ADDR(UDR3_REGISTER)),
#endif
[mask] "M"(RX3_BUFFER_MASK), [mpcm_address] "M"(MPCM3_ADDRESS), [mask] "M"(RX3_BUFFER_MASK), [mpcm_address] "M"(MPCM3_ADDRESS),
#ifdef MPCM3_GCALL_ADDRESS #ifdef MPCM3_GCALL_ADDRESS
[mpcm_gcall_address] "M"(MPCM3_GCALL_ADDRESS), [mpcm_gcall_address] "M"(MPCM3_GCALL_ADDRESS),
@ -6009,8 +6220,13 @@ ISR(RX3_INTERRUPT, ISR_NAKED) {
#ifdef USART3_USE_SOFT_RTS #ifdef USART3_USE_SOFT_RTS
[rts_port] "M"(_SFR_IO_ADDR(RTS3_PORT)), [rts_pin] "M"(RTS3_IONUM), [rts_port] "M"(_SFR_IO_ADDR(RTS3_PORT)), [rts_pin] "M"(RTS3_IONUM),
#endif #endif
[UCSRA_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)), #if __AVR_ARCH__ == 103
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
#else
[MPCM_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
[control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)), [control_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)),
#endif
[rxcie_bit] "M"(RXCIE3_BIT) [rxcie_bit] "M"(RXCIE3_BIT)
// no clobbers // no clobbers

468
vendor/jnk0le-AVR-UART-lib/usart.h vendored
View File

@ -15,15 +15,21 @@
#warning F_CPU is undefined, USART may not work correctly without this #warning F_CPU is undefined, USART may not work correctly without this
#endif #endif
#define BAUD_CALC(x) \ #if __AVR_ARCH__ == 103
((F_CPU + (x) * 8UL) / (16UL * (x)) - \ (uint16_t)(((F_CPU / BAUD_RATE) * 4UL) + 0.5)
1UL) // macro calculating precise UBRR value // macro calculating precise UBRR value
#define BAUD_CALC_FAST(x) \ #define BAUD_CALC(x) (uint16_t)(((F_CPU / BAUD_RATE) * 4UL) + 0.5)
((F_CPU) / ((x) * 16UL) - \ #define BAUD_CALC_FAST(x) BAUD_CALC(x)
1) // for faster real time calculations ? // not recommended // macro calculating UBRR value for double speed
#define DOUBLE_BAUD_CALC(x) \ #define DOUBLE_BAUD_CALC(x) (uint16_t)(((F_CPU / BAUD_RATE) * 8UL) + 0.5)
((F_CPU + (x) * 4UL) / (8UL * (x)) - \ #else
1UL) // macro calculating UBRR value for double speed // macro calculating precise UBRR value
#define BAUD_CALC(x) ((F_CPU + (x) * 8UL) / (16UL * (x)) - 1UL)
// for faster real time calculations ? // not recommended
#define BAUD_CALC_FAST(x) ((F_CPU) / ((x) * 16UL) - 1)
// macro calculating UBRR value for double speed
#define DOUBLE_BAUD_CALC(x) ((F_CPU + (x) * 4UL) / (8UL * (x)) - 1UL)
#endif
#if !defined(__OPTIMIZE__) && !defined(USART_NO_ABI_BREAKING_PREMATURES) #if !defined(__OPTIMIZE__) && !defined(USART_NO_ABI_BREAKING_PREMATURES)
#warning Compiler optimizations disabled; functions from usart.h might not work as designed #warning Compiler optimizations disabled; functions from usart.h might not work as designed
@ -82,7 +88,11 @@
#define TX3_BUFFER_MASK (TX3_BUFFER_SIZE - 1) #define TX3_BUFFER_MASK (TX3_BUFFER_SIZE - 1)
#define RX3_BUFFER_MASK (RX3_BUFFER_SIZE - 1) #define RX3_BUFFER_MASK (RX3_BUFFER_SIZE - 1)
enum { COMPLETED = 1, BUFFER_EMPTY = 0, BUFFER_FULL = 0 }; enum {
COMPLETED = 1,
BUFFER_EMPTY = 0,
BUFFER_FULL = 0
};
#if defined(URSEL) || defined(URSEL0) || defined(URSEL1) || defined(URSEL2) || \ #if defined(URSEL) || defined(URSEL0) || defined(URSEL1) || defined(URSEL2) || \
defined(URSEL3) defined(URSEL3)
@ -104,6 +114,25 @@ enum { COMPLETED = 1, BUFFER_EMPTY = 0, BUFFER_FULL = 0 };
#define USART_ASYNC_MODE 0x80 #define USART_ASYNC_MODE 0x80
#define USART_SYNC_MODE 0xC0 #define USART_SYNC_MODE 0xC0
#elif __AVR_ARCH__ == 103
#define USART_XCK_RISING_EDGE 0x00
#define USART_XCK_FALLING_EDGE 0x01
#define USART_5BIT_DATA USART_CHSIZE_5BIT_gc
#define USART_6BIT_DATA USART_CHSIZE_6BIT_gc
#define USART_7BIT_DATA USART_CHSIZE_7BIT_gc
#define USART_8BIT_DATA USART_CHSIZE_8BIT_gc
#define USART_1STOP_BIT USART_SBMODE_1BIT_gc
#define USART_2STOP_BITS USART_SBMODE_2BIT_gc
#define USART_NO_PARITY USART_PMODE_DISABLED_gc
#define USART_EVEN_PARITY USART_PMODE_EVEN_gc
#define USART_ODD_PARITY USART_PMODE_ODD_gc
#define USART_ASYNC_MODE USART_CMODE_ASYNCHRONOUS_gc
#define USART_SYNC_MODE USART_CMODE_SYNCHRONOUS_gc
#define USART_MSPI_MODE USART_CMODE_MSPI_gc
#else #else
#define USART_XCK_RISING_EDGE 0x00 #define USART_XCK_RISING_EDGE 0x00
#define USART_XCK_FALLING_EDGE 0x01 #define USART_XCK_FALLING_EDGE 0x01
@ -1074,6 +1103,69 @@ register uint16_t USART_Z_SAVE_REG_NAME asm(
#endif // NO_USART1 #endif // NO_USART1
#endif #endif
#if __AVR_ARCH__ == 103
#ifndef NO_USART0
#define USE_USART0
#define RX0_INTERRUPT USART0_RXC_vect
#define TXC0_INTERRUPT USART0_TXC_vect
#define UDRE0_INTERRUPT USART0_DRE_vect
#define UDR0_REGISTER USART0_TXDATAL
#define UDR0H_REGISTER USART0_TXDATAH
#define RX0_REGISTER USART0_RXDATAL
#define RX0H_REGISTER USART0_RXDATAH
#define UBRR0L_REGISTER USART0_BAUDL
#define UBRR0H_REGISTER USART0_BAUDH
#define USR0_REGISTER USART0_STATUS
#define UCSR0A_REGISTER USART0_CTRLA
#define UCSR0B_REGISTER USART0_CTRLB
#define UCSR0C_REGISTER USART0_CTRLC
#define TXCIE0_BIT USART_TXCIE_bp // CTRLA
#define UDRIE0_BIT USART_DREIE_bp // CTRLA
#define RXCIE0_BIT USART_RXSIE_bp // CTRLA
#define TXEN0_BIT USART_TXEN_bp // CTRLB
#define RXEN0_BIT USART_RXEN_bp // CTRLB
#define UDRE0_BIT USART_DREIF_bp // STATUS
#define RXC0_BIT USART_RXCIF_bp // STATUS
#define U2X0_BIT USART_RXMODE_gp // CTRLB
#define MPCM0_BIT USART_MPCM_bp // CTRLB
// #define UCSZ02_BIT UCSZ02
#define TXB80_BIT USART_DATA8_bp
#endif // NO_USART0
#if !defined(NO_USART1) && defined(USART1)
#define USE_USART1
#define RX1_INTERRUPT USART1_RXC_vect
#define TXC1_INTERRUPT USART1_TXC_vect
#define UDRE1_INTERRUPT USART1_DRE_vect
#define UDR1_REGISTER USART1_TXDATAL
#define UDR1H_REGISTER USART1_TXDATAH
#define RX1_REGISTER USART1_RXDATAL
#define RX1H_REGISTER USART1_RXDATAH
#define UBRR1L_REGISTER USART1_BAUDL
#define UBRR1H_REGISTER USART1_BAUDH
#define USR1_REGISTER USART1_STATUS
#define UCSR1A_REGISTER USART1_CTRLA
#define UCSR1B_REGISTER USART1_CTRLB
#define UCSR1C_REGISTER USART1_CTRLC
#define TXCIE1_BIT USART_TXCIE_bp // CTRLA
#define UDRIE1_BIT USART_DREIE_bp // CTRLA
#define RXCIE1_BIT USART_RXSIE_bp // CTRLA
#define TXEN1_BIT USART_TXEN_bp // CTRLB
#define RXEN1_BIT USART_RXEN_bp // CTRLB
#define UDRE1_BIT USART_DREIF_bp // STATUS
#define RXC1_BIT USART_RXCIF_bp // RXDATAH
#define U2X1_BIT (USART_RXMODE_gp - USART_RXMODE_0_bp) // CTRLB
#define MPCM1_BIT USART_MPCM_bp // CTRLB
// #define UCSZ12_BIT UCSZ12
#define TXB81_BIT USART_DATA8_bp
#endif // NO_USART1
#endif
#if defined(USART_REMAP_LAST_INTERFACE) && !defined(USE_USART0) && \ #if defined(USART_REMAP_LAST_INTERFACE) && !defined(USE_USART0) && \
defined(USE_USART1) && !defined(USE_USART2) && !defined(USE_USART3) defined(USE_USART1) && !defined(USE_USART2) && !defined(USE_USART3)
#undef USE_USART1 #undef USE_USART1
@ -1217,38 +1309,65 @@ register uint16_t USART_Z_SAVE_REG_NAME asm(
#ifndef USART0_CONFIG_B // set config bytes for UCSR0B_REGISTER #ifndef USART0_CONFIG_B // set config bytes for UCSR0B_REGISTER
#ifdef USART0_MPCM_MODE #if __AVR_ARCH__ == 103
#ifdef USART0_U2X_SPEED
#define USART0_CONFIG_B_SPEED | (1 << U2X0_BIT)
#else
#define USART0_CONFIG_B_SPEED | (0 << U2X0_BIT)
#endif
#ifdef USART0_MPCM_MODE
#define USART0_CONFIG_B_MPCM | (1 << MPCM0_BIT)
#else
#define USART0_CONFIG_B_MPCM | (0 << MPCM0_BIT)
#endif
#if defined(NO_RX0_INTERRUPT) #if defined(NO_RX0_INTERRUPT)
#define USART0_CONFIG_B (1 << TXEN0_BIT) | (1 << UCSZ02_BIT) #define USART0_CONFIG_B \
(1 << TXEN0_BIT) USART0_CONFIG_B_MPCM USART0_CONFIG_B_SPEED
#elif defined(NO_TX0_INTERRUPT) #elif defined(NO_TX0_INTERRUPT)
#define USART0_CONFIG_B \ #define USART0_CONFIG_B \
(1 << RXEN0_BIT) | (1 << RXCIE0_BIT) | (1 << UCSZ02_BIT) (1 << RXEN0_BIT) USART0_CONFIG_B_MPCM USART0_CONFIG_B_SPEED
#else #else
#ifdef USART0_RS485_MODE #define USART0_CONFIG_B \
#define USART0_CONFIG_B \ (1 << TXEN0_BIT) | (1 << RXEN0_BIT) \
(1 << TXEN0_BIT) | (1 << TXCIE0_BIT) | (1 << RXEN0_BIT) | \ USART0_CONFIG_B_MPCM USART0_CONFIG_B_SPEED
(1 << RXCIE0_BIT) | (1 << UCSZ02_BIT)
#else
#define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << RXEN0_BIT) | (1 << RXCIE0_BIT) | \
(1 << UCSZ02_BIT)
#endif
#endif #endif
#else #else
#if defined(NO_RX0_INTERRUPT) #ifdef USART0_MPCM_MODE
#define USART0_CONFIG_B (1 << TXEN0_BIT) #if defined(NO_RX0_INTERRUPT)
#define USART0_CONFIG_B (1 << TXEN0_BIT) | (1 << UCSZ02_BIT)
#elif defined(NO_TX0_INTERRUPT) #elif defined(NO_TX0_INTERRUPT)
#define USART0_CONFIG_B (1 << RXEN0_BIT) | (1 << RXCIE0_BIT)
#else
#ifdef USART0_RS485_MODE
#define USART0_CONFIG_B \ #define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << TXCIE0_BIT) | (1 << RXEN0_BIT) | \ (1 << RXEN0_BIT) | (1 << RXCIE0_BIT) | (1 << UCSZ02_BIT)
(1 << RXCIE0_BIT)
#else #else
#define USART0_CONFIG_B \ #ifdef USART0_RS485_MODE
(1 << TXEN0_BIT) | (1 << RXEN0_BIT) | (1 << RXCIE0_BIT) #define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << TXCIE0_BIT) | (1 << RXEN0_BIT) | \
(1 << RXCIE0_BIT) | (1 << UCSZ02_BIT)
#else
#define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << RXEN0_BIT) | (1 << RXCIE0_BIT) | \
(1 << UCSZ02_BIT)
#endif
#endif
#else
#if defined(NO_RX0_INTERRUPT)
#define USART0_CONFIG_B (1 << TXEN0_BIT)
#elif defined(NO_TX0_INTERRUPT)
#define USART0_CONFIG_B (1 << RXEN0_BIT) | (1 << RXCIE0_BIT)
#else
#ifdef USART0_RS485_MODE
#define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << TXCIE0_BIT) | (1 << RXEN0_BIT) | \
(1 << RXCIE0_BIT)
#else
#define USART0_CONFIG_B \
(1 << TXEN0_BIT) | (1 << RXEN0_BIT) | (1 << RXCIE0_BIT)
#endif
#endif #endif
#endif #endif
#endif #endif
@ -1399,23 +1518,36 @@ static inline void uart0_init(uint16_t ubrr_value) {
#ifdef USART_SKIP_UBRRH_IF_ZERO #ifdef USART_SKIP_UBRRH_IF_ZERO
if (__builtin_constant_p(ubrr_value)) if (__builtin_constant_p(ubrr_value))
if (((ubrr_value >> 8) != // requires -Os flag - do not use in non-inline functions
0)) // requires -Os flag - do not use in non-inline functions if (((ubrr_value >> 8) != 0))
#endif #endif
UBRR0H_REGISTER = (ubrr_value >> 8); UBRR0H_REGISTER = (ubrr_value >> 8);
#ifdef USART0_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART0_MPCM_MODE #if (!defined(NO_RX0_INTERRUPT) && !defined(NO_TX0_INTERRUPT))
UCSR0A_REGISTER = (1 << U2X0_BIT) | (1 << MPCM0_BIT); #ifdef USART0_RS485_MODE
#else UCSR0A_REGISTER = (1 << RXCIE0_BIT) | (1 << TXCIE0_BIT) | (1 << RS485_BIT);
UCSR0A_REGISTER = (1 << U2X0_BIT); // enable double speed #else
UCSR0A_REGISTER = (1 << RXCIE0_BIT);
#endif
#endif #endif
#elif defined(USART0_MPCM_MODE) #else
#ifdef USART0_U2X_SPEED
#ifdef USART0_MPCM_MODE
UCSR0A_REGISTER = (1 << U2X0_BIT) | (1 << MPCM0_BIT);
#else
UCSR0A_REGISTER = (1 << U2X0_BIT); // enable double speed
#endif
#elif defined(USART0_MPCM_MODE)
UCSR0A_REGISTER |= (1 << MPCM0_BIT); UCSR0A_REGISTER |= (1 << MPCM0_BIT);
#endif
#endif #endif
UCSR0B_REGISTER = USART0_CONFIG_B; UCSR0B_REGISTER = USART0_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART0_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR0C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART0_USE_SOFT_RTS #ifdef USART0_USE_SOFT_RTS
RTS0_DDR |= (1 << RTS0_IONUM); RTS0_DDR |= (1 << RTS0_IONUM);
@ -1432,7 +1564,21 @@ static inline void uart0_set_FrameFormat(uint8_t UCSRC_reg) {
// use instead of USE_DOUBLE_SPEED // use instead of USE_DOUBLE_SPEED
static inline void uart0_set_U2X(void) __attribute__((always_inline)); static inline void uart0_set_U2X(void) __attribute__((always_inline));
static inline void uart0_set_U2X(void) { static inline void uart0_set_U2X(void) {
#if __AVR_ARCH__ == 103
UCSR0B_REGISTER = (1 << U2X0_BIT);
#else
UCSR0A_REGISTER |= (1 << U2X0_BIT); UCSR0A_REGISTER |= (1 << U2X0_BIT);
#endif
}
// enable UDRE interrupt
static inline void uart0_enable_UDREI(void) __attribute__((always_inline));
static inline void uart0_enable_UDREI(void) {
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER |= (1 << UDRIE0_BIT);
#else
UCSR0B_REGISTER |= (1 << UDRIE0_BIT);
#endif
} }
#ifdef USART0_MPCM_MODE #ifdef USART0_MPCM_MODE
@ -1440,7 +1586,11 @@ static inline void uart0_set_U2X(void) {
static inline void uart0_mpcm_slave_return_idle(void) static inline void uart0_mpcm_slave_return_idle(void)
__attribute__((always_inline)); __attribute__((always_inline));
static inline void uart0_mpcm_slave_return_idle(void) { static inline void uart0_mpcm_slave_return_idle(void) {
#if __AVR_ARCH__ == 103
UCSR0B_REGISTER = (1 << MPCM0_BIT);
#else
UCSR0A_REGISTER |= (1 << MPCM0_BIT); UCSR0A_REGISTER |= (1 << MPCM0_BIT);
#endif
} }
#endif #endif
@ -1484,23 +1634,36 @@ static inline void uart1_init(uint16_t ubrr_value) {
#ifdef USART_SKIP_UBRRH_IF_ZERO #ifdef USART_SKIP_UBRRH_IF_ZERO
if (__builtin_constant_p(ubrr_value)) if (__builtin_constant_p(ubrr_value))
if (((ubrr_value >> 8) != // requires -Os flag - do not use in non-inline functions
0)) // requires -Os flag - do not use in non-inline functions if (((ubrr_value >> 8) != 0))
#endif #endif
UBRR1H_REGISTER = (ubrr_value >> 8); UBRR1H_REGISTER = (ubrr_value >> 8);
#ifdef USART1_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART1_MPCM_MODE #if (!defined(NO_RX1_INTERRUPT) && !defined(NO_TX1_INTERRUPT))
UCSR1A_REGISTER = (1 << U2X1_BIT) | (1 << MPCM1_BIT); #ifdef USART1_RS485_MODE
#else UCSR1A_REGISTER = (1 << RXCIE1_BIT) | (1 << TXCIE1_BIT) | (1 << RS485_BIT);
UCSR1A_REGISTER = (1 << U2X1_BIT); // enable double speed #else
UCSR1A_REGISTER = (1 << RXCIE1_BIT);
#endif
#endif #endif
#elif defined(USART1_MPCM_MODE) #else
#ifdef USART1_U2X_SPEED
#ifdef USART1_MPCM_MODE
UCSR1A_REGISTER = (1 << U2X1_BIT) | (1 << MPCM1_BIT);
#else
UCSR1A_REGISTER = (1 << U2X1_BIT); // enable double speed
#endif
#elif defined(USART1_MPCM_MODE)
UCSR1A_REGISTER |= (1 << MPCM1_BIT); UCSR1A_REGISTER |= (1 << MPCM1_BIT);
#endif
#endif #endif
UCSR1B_REGISTER = USART1_CONFIG_B; UCSR1B_REGISTER = USART1_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART1_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR1C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART1_USE_SOFT_RTS #ifdef USART1_USE_SOFT_RTS
RTS1_DDR |= (1 << RTS1_IONUM); RTS1_DDR |= (1 << RTS1_IONUM);
@ -1516,14 +1679,34 @@ static inline void uart1_set_FrameFormat(uint8_t UCSRC_reg) {
// use instead of USE_DOUBLE_SPEED // use instead of USE_DOUBLE_SPEED
static inline void uart1_set_U2X(void) __attribute__((always_inline)); static inline void uart1_set_U2X(void) __attribute__((always_inline));
static inline void uart1_set_U2X(void) { UCSR1A_REGISTER |= (1 << U2X1_BIT); } static inline void uart1_set_U2X(void) {
#if __AVR_ARCH__ == 103
UCSR1B_REGISTER = (1 << U2X1_BIT);
#else
UCSR1A_REGISTER |= (1 << U2X1_BIT);
#endif
}
// enable UDRE interrupt
static inline void uart1_enable_UDREI(void) __attribute__((always_inline));
static inline void uart1_enable_UDREI(void) {
#if __AVR_ARCH__ == 103
UCSR1A_REGISTER |= (1 << UDRIE1_BIT);
#else
UCSR1B_REGISTER |= (1 << UDRIE1_BIT);
#endif
}
#ifdef USART1_MPCM_MODE #ifdef USART1_MPCM_MODE
// return slave to mpcm idle mode (wait for own addres frame) // return slave to mpcm idle mode (wait for own addres frame)
static inline void uart1_mpcm_slave_return_idle(void) static inline void uart1_mpcm_slave_return_idle(void)
__attribute__((always_inline)); __attribute__((always_inline));
static inline void uart1_mpcm_slave_return_idle(void) { static inline void uart1_mpcm_slave_return_idle(void) {
#if __AVR_ARCH__ == 103
UCSR1B_REGISTER = (1 << MPCM1_BIT);
#else
UCSR1A_REGISTER |= (1 << MPCM1_BIT); UCSR1A_REGISTER |= (1 << MPCM1_BIT);
#endif
} }
#endif #endif
@ -1562,23 +1745,36 @@ static inline void uart2_init(uint16_t ubrr_value) {
#ifdef USART_SKIP_UBRRH_IF_ZERO #ifdef USART_SKIP_UBRRH_IF_ZERO
if (__builtin_constant_p(ubrr_value)) if (__builtin_constant_p(ubrr_value))
if (((ubrr_value >> 8) != // requires -Os flag - do not use in non-inline functions
0)) // requires -Os flag - do not use in non-inline functions if (((ubrr_value >> 8) != 0))
#endif #endif
UBRR2H_REGISTER = (ubrr_value >> 8); UBRR2H_REGISTER = (ubrr_value >> 8);
#ifdef USART2_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART2_MPCM_MODE #if (!defined(NO_RX2_INTERRUPT) && !defined(NO_TX2_INTERRUPT))
UCSR2A_REGISTER = (1 << U2X2_BIT) | (1 << MPCM2_BIT); #ifdef USART2_RS485_MODE
#else UCSR2A_REGISTER = (1 << RXCIE2_BIT) | (1 << TXCIE2_BIT) | (1 << RS485_BIT);
UCSR2A_REGISTER = (1 << U2X2_BIT); // enable double speed #else
UCSR2A_REGISTER = (1 << RXCIE2_BIT);
#endif
#endif #endif
#elif defined(USART2_MPCM_MODE) #else
#ifdef USART2_U2X_SPEED
#ifdef USART2_MPCM_MODE
UCSR2A_REGISTER = (1 << U2X2_BIT) | (1 << MPCM2_BIT);
#else
UCSR2A_REGISTER = (1 << U2X2_BIT); // enable double speed
#endif
#elif defined(USART2_MPCM_MODE)
UCSR2A_REGISTER |= (1 << MPCM2_BIT); UCSR2A_REGISTER |= (1 << MPCM2_BIT);
#endif
#endif #endif
UCSR2B_REGISTER = USART2_CONFIG_B; UCSR2B_REGISTER = USART2_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART2_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR2C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART2_USE_SOFT_RTS #ifdef USART2_USE_SOFT_RTS
RTS2_DDR |= (1 << RTS2_IONUM); RTS2_DDR |= (1 << RTS2_IONUM);
@ -1594,14 +1790,34 @@ static inline void uart2_set_FrameFormat(uint8_t UCSRC_reg) {
// use instead of USE_DOUBLE_SPEED // use instead of USE_DOUBLE_SPEED
static inline void uart2_set_U2X(void) __attribute__((always_inline)); static inline void uart2_set_U2X(void) __attribute__((always_inline));
static inline void uart2_set_U2X(void) { UCSR2A_REGISTER |= (1 << U2X2_BIT); } static inline void uart2_set_U2X(void) {
#if __AVR_ARCH__ == 103
UCSR2B_REGISTER = (1 << U2X2_BIT);
#else
UCSR2A_REGISTER |= (1 << U2X2_BIT);
#endif
}
// enable UDRE interrupt
static inline void uart2_enable_UDREI(void) __attribute__((always_inline));
static inline void uart2_enable_UDREI(void) {
#if __AVR_ARCH__ == 103
UCSR2A_REGISTER |= (1 << UDRIE2_BIT);
#else
UCSR2B_REGISTER |= (1 << UDRIE2_BIT);
#endif
}
#ifdef USART2_MPCM_MODE #ifdef USART2_MPCM_MODE
// return slave to mpcm idle mode (wait for own addres frame) // return slave to mpcm idle mode (wait for own addres frame)
static inline void uart2_mpcm_slave_return_idle(void) static inline void uart2_mpcm_slave_return_idle(void)
__attribute__((always_inline)); __attribute__((always_inline));
static inline void uart2_mpcm_slave_return_idle(void) { static inline void uart2_mpcm_slave_return_idle(void) {
#if __AVR_ARCH__ == 103
UCSR2B_REGISTER = (1 << MPCM2_BIT);
#else
UCSR2A_REGISTER |= (1 << MPCM2_BIT); UCSR2A_REGISTER |= (1 << MPCM2_BIT);
#endif
} }
#endif #endif
#endif // USE_USART2 #endif // USE_USART2
@ -1627,18 +1843,31 @@ static inline void uart3_init(uint16_t ubrr_value) {
#endif #endif
UBRR3H_REGISTER = (ubrr_value >> 8); UBRR3H_REGISTER = (ubrr_value >> 8);
#ifdef USART3_U2X_SPEED #if __AVR_ARCH__ == 103
#ifdef USART3_MPCM_MODE #if (!defined(NO_RX3_INTERRUPT) && !defined(NO_TX3_INTERRUPT))
UCSR3A_REGISTER = (1 << U2X3_BIT) | (1 << MPCM3_BIT); #ifdef USART3_RS485_MODE
#else UCSR3A_REGISTER = (1 << RXCIE3_BIT) | (1 << TXCIE3_BIT) | (1 << RS485_BIT);
UCSR3A_REGISTER = (1 << U2X3_BIT); // enable double speed #else
UCSR3A_REGISTER = (1 << RXCIE3_BIT);
#endif
#endif #endif
#elif defined(USART3_MPCM_MODE) #else
#ifdef USART3_U2X_SPEED
#ifdef USART3_MPCM_MODE
UCSR3A_REGISTER = (1 << U2X3_BIT) | (1 << MPCM3_BIT);
#else
UCSR3A_REGISTER = (1 << U2X3_BIT); // enable double speed
#endif
#elif defined(USART3_MPCM_MODE)
UCSR3A_REGISTER |= (1 << MPCM3_BIT); UCSR3A_REGISTER |= (1 << MPCM3_BIT);
#endif
#endif #endif
UCSR3B_REGISTER = USART3_CONFIG_B; UCSR3B_REGISTER = USART3_CONFIG_B;
// 8n1 is set by default, setting UCSRC is not needed // 8n1 is set by default, setting UCSRC is not needed
#if defined(USART3_MPCM_MODE) && __AVR_ARCH__ == 103
UCSR3C_REGISTER = USART_CHSIZE_9BITH_gc;
#endif
#ifdef USART3_USE_SOFT_RTS #ifdef USART3_USE_SOFT_RTS
RTS3_DDR |= (1 << RTS3_IONUM); RTS3_DDR |= (1 << RTS3_IONUM);
@ -1654,14 +1883,34 @@ static inline void uart3_set_FrameFormat(uint8_t UCSRC_reg) {
// use instead of USE_DOUBLE_SPEED // use instead of USE_DOUBLE_SPEED
static inline void uart3_set_U2X(void) __attribute__((always_inline)); static inline void uart3_set_U2X(void) __attribute__((always_inline));
static inline void uart3_set_U2X(void) { UCSR3A_REGISTER |= (1 << U2X3_BIT); } static inline void uart3_set_U2X(void) {
#if __AVR_ARCH__ == 103
UCSR3B_REGISTER = (1 << U2X3_BIT);
#else
UCSR3A_REGISTER |= (1 << U2X3_BIT);
#endif
}
// enable UDRE interrupt
static inline void uart3_enable_UDREI(void) __attribute__((always_inline));
static inline void uart3_enable_UDREI(void) {
#if __AVR_ARCH__ == 103
UCSR3A_REGISTER |= (1 << UDRIE3_BIT);
#else
UCSR3B_REGISTER |= (1 << UDRIE3_BIT);
#endif
}
#ifdef USART3_MPCM_MODE #ifdef USART3_MPCM_MODE
// return slave to mpcm idle mode (wait for own addres frame) // return slave to mpcm idle mode (wait for own addres frame)
static inline void uart3_mpcm_slave_return_idle(void) static inline void uart3_mpcm_slave_return_idle(void)
__attribute__((always_inline)); __attribute__((always_inline));
static inline void uart3_mpcm_slave_return_idle(void) { static inline void uart3_mpcm_slave_return_idle(void) {
#if __AVR_ARCH__ == 103
UCSR3B_REGISTER = (1 << MPCM3_BIT);
#else
UCSR3A_REGISTER |= (1 << MPCM3_BIT); UCSR3A_REGISTER |= (1 << MPCM3_BIT);
#endif
} }
#endif #endif
#endif // USE_USART3 #endif // USE_USART3
@ -2258,13 +2507,22 @@ static inline void cts0_isr_handler(void) {
UCSR0B_REGISTER |= (1 << UDRIE0_BIT); UCSR0B_REGISTER |= (1 << UDRIE0_BIT);
} }
#else #else
#if __AVR_ARCH__ == 103
uint8_t tmp = UCSR0A_REGISTER;
#else
uint8_t tmp = UCSR0B_REGISTER; uint8_t tmp = UCSR0B_REGISTER;
#endif
if (CTS0_PIN & (1 << CTS0_IONUM)) { if (CTS0_PIN & (1 << CTS0_IONUM)) {
tmp &= ~(1 << UDRIE0_BIT); tmp &= ~(1 << UDRIE0_BIT);
} else if (tx0_Tail != tx0_Head) { } else if (tx0_Tail != tx0_Head) {
tmp |= (1 << UDRIE0_BIT); tmp |= (1 << UDRIE0_BIT);
} }
#if __AVR_ARCH__ == 103
UCSR0A_REGISTER = tmp;
#else
UCSR0B_REGISTER = tmp; UCSR0B_REGISTER = tmp;
#endif
#endif #endif
} }
@ -2273,7 +2531,7 @@ static inline void naked_cts0_isr_handler(void) {
asm volatile("\n\t" asm volatile("\n\t"
#if defined(USART0_IN_IO_ADDRESS_SPACE) #if defined(USART0_IN_IO_ADDRESS_SPACE)
"cbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "cbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"sbic %M[cts_port], %M[cts_pin] \n\t" "sbic %M[cts_port], %M[cts_pin] \n\t"
"reti \n\t" "reti \n\t"
@ -2281,14 +2539,14 @@ static inline void naked_cts0_isr_handler(void) {
"lds %B[z_save], (tx0_Tail) \n\t" "lds %B[z_save], (tx0_Tail) \n\t"
"lds %A[z_save], (tx0_Head) \n\t" "lds %A[z_save], (tx0_Head) \n\t"
"cpse %B[z_save], %A[z_save] \n\t" "cpse %B[z_save], %A[z_save] \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE) #elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
"push r25 \n\t" "push r25 \n\t"
"lds r25, (tx0_Tail) \n\t" "lds r25, (tx0_Tail) \n\t"
"lds %[sreg_save], (tx0_Head) \n\t" "lds %[sreg_save], (tx0_Head) \n\t"
"cpse r25, %[sreg_save] \n\t" "cpse r25, %[sreg_save] \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"pop r25 \n\t" "pop r25 \n\t"
#else #else
@ -2298,7 +2556,7 @@ static inline void naked_cts0_isr_handler(void) {
"lds r25, (tx0_Tail) \n\t" "lds r25, (tx0_Tail) \n\t"
"lds r24, (tx0_Head) \n\t" "lds r24, (tx0_Head) \n\t"
"cpse r25, r24 \n\t" "cpse r25, r24 \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"pop r25 \n\t" "pop r25 \n\t"
"pop r24 \n\t" "pop r24 \n\t"
@ -2327,9 +2585,9 @@ static inline void naked_cts0_isr_handler(void) {
#endif #endif
#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE #ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
"in r24, %M[UCSRB_reg_IO] \n\t" "in r24, %M[UDRIE_reg_IO] \n\t"
#else #else
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
#endif #endif
"andi r24, ~(1<<%M[UDRIE_bit]) \n\t" "andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
@ -2350,17 +2608,17 @@ static inline void naked_cts0_isr_handler(void) {
// - no need to clear it // - no need to clear it
#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE #ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
"in r24, %M[UCSRB_reg_IO] \n\t" "in r24, %M[UDRIE_reg_IO] \n\t"
#else #else
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
#endif #endif
"ori r24, (1<<%M[UDRIE_bit]) \n\t" "ori r24, (1<<%M[UDRIE_bit]) \n\t"
"cts_apply_%=:" "cts_apply_%=:"
#ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE #ifdef USART0_IN_UPPER_IO_ADDRESS_SPACE
"out %M[UCSRB_reg_IO], r24 \n\t" "out %M[UDRIE_reg_IO], r24 \n\t"
#else #else
"sts %M[UCSRB_reg], r24 \n\t" "sts %M[UDRIE_reg], r24 \n\t"
#endif #endif
"cts_exit_%=:" "cts_exit_%=:"
@ -2387,8 +2645,13 @@ static inline void naked_cts0_isr_handler(void) {
: /* output operands */ : /* output operands */
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: /* input operands */ : /* input operands */
[UCSRB_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRB_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)), [UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR0A_REGISTER)),
[UDRIE_reg_IO] "M"(_SFR_IO_ADDR(UCSR0A_REGISTER)),
#else
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR0B_REGISTER)),
[UDRIE_reg_IO] "M"(_SFR_IO_ADDR(UCSR0B_REGISTER)),
#endif
[UDRIE_bit] "M"(UDRIE0_BIT), [UDRIE_bit] "M"(UDRIE0_BIT),
[cts_port] "M"(_SFR_IO_ADDR(CTS0_PIN)), [cts_pin] "M"(CTS0_IONUM) [cts_port] "M"(_SFR_IO_ADDR(CTS0_PIN)), [cts_pin] "M"(CTS0_IONUM)
: /* clobbers */ : /* clobbers */
@ -2423,7 +2686,7 @@ static inline void naked_cts1_isr_handler(void) {
asm volatile("\n\t" asm volatile("\n\t"
#if defined(USART1_IN_IO_ADDRESS_SPACE) #if defined(USART1_IN_IO_ADDRESS_SPACE)
"cbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "cbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"sbic %M[cts_port], %M[cts_pin] \n\t" "sbic %M[cts_port], %M[cts_pin] \n\t"
"reti \n\t" "reti \n\t"
@ -2431,7 +2694,7 @@ static inline void naked_cts1_isr_handler(void) {
"lds %B[z_save], (tx1_Tail) \n\t" "lds %B[z_save], (tx1_Tail) \n\t"
"lds %A[z_save], (tx1_Head) \n\t" "lds %A[z_save], (tx1_Head) \n\t"
"cpse %B[z_save], %A[z_save] \n\t" "cpse %B[z_save], %A[z_save] \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
#elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE) #elif defined(USART_USE_GLOBALLY_RESERVED_ISR_SREG_SAVE)
"push r25 \n\t" "push r25 \n\t"
@ -2439,7 +2702,7 @@ static inline void naked_cts1_isr_handler(void) {
"lds r25, (tx1_Tail) \n\t" "lds r25, (tx1_Tail) \n\t"
"lds %[sreg_save], (tx1_Head) \n\t" "lds %[sreg_save], (tx1_Head) \n\t"
"cpse r25, %[sreg_save] \n\t" "cpse r25, %[sreg_save] \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"pop r25 \n\t" "pop r25 \n\t"
#else #else
@ -2449,7 +2712,7 @@ static inline void naked_cts1_isr_handler(void) {
"lds r25, (tx1_Tail) \n\t" "lds r25, (tx1_Tail) \n\t"
"lds r24, (tx1_Head) \n\t" "lds r24, (tx1_Head) \n\t"
"cpse r25, r24 \n\t" "cpse r25, r24 \n\t"
"sbi %M[UCSRB_reg_IO], %M[UDRIE_bit] \n\t" "sbi %M[UDRIE_reg_IO], %M[UDRIE_bit] \n\t"
"pop r25 \n\t" "pop r25 \n\t"
"pop r24 \n\t" "pop r24 \n\t"
@ -2471,7 +2734,7 @@ static inline void naked_cts1_isr_handler(void) {
"push r24 \n\t" "push r24 \n\t"
#endif #endif
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"andi r24, ~(1<<%M[UDRIE_bit]) \n\t" "andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
"sbic %M[cts_port], %M[cts_pin]\n\t" "sbic %M[cts_port], %M[cts_pin]\n\t"
"rjmp cts_apply_%= \n\t" "rjmp cts_apply_%= \n\t"
@ -2489,10 +2752,10 @@ static inline void naked_cts1_isr_handler(void) {
"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case "breq cts_exit_%= \n\t" // UDRIE should be disabled in this case
// - no need to clear it // - no need to clear it
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"ori r24, (1<<%M[UDRIE_bit]) \n\t" "ori r24, (1<<%M[UDRIE_bit]) \n\t"
"cts_apply_%=:" "cts_apply_%=:"
"sts %M[UCSRB_reg], r24 \n\t" "sts %M[UDRIE_reg], r24 \n\t"
"cts_exit_%=:" "cts_exit_%=:"
#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE #ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
@ -2513,8 +2776,13 @@ static inline void naked_cts1_isr_handler(void) {
: /* output operands */ : /* output operands */
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: /* input operands */ : /* input operands */
[UCSRB_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)), #if __AVR_ARCH__ == 103
[UCSRB_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)), [UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR1A_REGISTER)),
[UDRIE_reg_IO] "M"(_SFR_IO_ADDR(UCSR1A_REGISTER)),
#else
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR1B_REGISTER)),
[UDRIE_reg_IO] "M"(_SFR_IO_ADDR(UCSR1B_REGISTER)),
#endif
[UDRIE_bit] "M"(UDRIE1_BIT), [UDRIE_bit] "M"(UDRIE1_BIT),
[cts_port] "M"(_SFR_IO_ADDR(CTS1_PIN)), [cts_pin] "M"(CTS1_IONUM) [cts_port] "M"(_SFR_IO_ADDR(CTS1_PIN)), [cts_pin] "M"(CTS1_IONUM)
: /* clobbers */ : /* clobbers */
@ -2553,7 +2821,7 @@ static inline void naked_cts2_isr_handler(void) {
"push r24 \n\t" "push r24 \n\t"
#endif #endif
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"andi r24, ~(1<<%M[UDRIE_bit]) \n\t" "andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
"sbic %M[cts_port], %M[cts_pin]\n\t" "sbic %M[cts_port], %M[cts_pin]\n\t"
"rjmp cts_apply_%= \n\t" "rjmp cts_apply_%= \n\t"
@ -2571,10 +2839,10 @@ static inline void naked_cts2_isr_handler(void) {
"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case "breq cts_exit_%= \n\t" // UDRIE should be disabled in this case
// - no need to clear it // - no need to clear it
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"ori r24, (1<<%M[UDRIE_bit]) \n\t" "ori r24, (1<<%M[UDRIE_bit]) \n\t"
"cts_apply_%=:" "cts_apply_%=:"
"sts %M[UCSRB_reg], r24 \n\t" "sts %M[UDRIE_reg], r24 \n\t"
"cts_exit_%=:" "cts_exit_%=:"
#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE #ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
@ -2594,7 +2862,11 @@ static inline void naked_cts2_isr_handler(void) {
: /* output operands */ : /* output operands */
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: /* input operands */ : /* input operands */
[UCSRB_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)), #if __AVR_ARCH__ == 103
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR2A_REGISTER)),
#else
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR2B_REGISTER)),
#endif
[UDRIE_bit] "M"(UDRIE2_BIT), [UDRIE_bit] "M"(UDRIE2_BIT),
[cts_port] "M"(_SFR_IO_ADDR(CTS2_PIN)), [cts_pin] "M"(CTS2_IONUM) [cts_port] "M"(_SFR_IO_ADDR(CTS2_PIN)), [cts_pin] "M"(CTS2_IONUM)
: /* clobbers */ : /* clobbers */
@ -2633,7 +2905,7 @@ static inline void naked_cts3_isr_handler(void) {
"push r24 \n\t" "push r24 \n\t"
#endif #endif
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"andi r24, ~(1<<%M[UDRIE_bit]) \n\t" "andi r24, ~(1<<%M[UDRIE_bit]) \n\t"
"sbic %M[cts_port], %M[cts_pin]\n\t" "sbic %M[cts_port], %M[cts_pin]\n\t"
"rjmp cts_apply_%= \n\t" "rjmp cts_apply_%= \n\t"
@ -2651,10 +2923,10 @@ static inline void naked_cts3_isr_handler(void) {
"breq cts_exit_%= \n\t" // UDRIE should be disabled in this case "breq cts_exit_%= \n\t" // UDRIE should be disabled in this case
// - no need to clear it // - no need to clear it
"lds r24, %M[UCSRB_reg] \n\t" "lds r24, %M[UDRIE_reg] \n\t"
"ori r24, (1<<%M[UDRIE_bit]) \n\t" "ori r24, (1<<%M[UDRIE_bit]) \n\t"
"cts_apply_%=:" "cts_apply_%=:"
"sts %M[UCSRB_reg], r24 \n\t" "sts %M[UDRIE_reg], r24 \n\t"
"cts_exit_%=:" "cts_exit_%=:"
#ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE #ifdef USART_USE_GLOBALLY_RESERVED_ISR_Z_SAVE
@ -2674,7 +2946,11 @@ static inline void naked_cts3_isr_handler(void) {
: /* output operands */ : /* output operands */
USART_REG_SAVE_LIST USART_REG_SAVE_LIST
: /* input operands */ : /* input operands */
[UCSRB_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)), #if __AVR_ARCH__ == 103
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR3A_REGISTER)),
#else
[UDRIE_reg] "n"(_SFR_MEM_ADDR(UCSR3B_REGISTER)),
#endif
[UDRIE_bit] "M"(UDRIE3_BIT), [UDRIE_bit] "M"(UDRIE3_BIT),
[cts_port] "M"(_SFR_IO_ADDR(CTS3_PIN)), [cts_pin] "M"(CTS3_IONUM) [cts_port] "M"(_SFR_IO_ADDR(CTS3_PIN)), [cts_pin] "M"(CTS3_IONUM)
: /* clobbers */ : /* clobbers */