mirror of
https://github.com/halleysfifthinc/AVCLAN-Mockingboard.git
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Decouple hardware specific code from generic, agnostic code
This commit is contained in:
Allen Hill
@@ -0,0 +1,525 @@
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/*
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AVCLAN-Mockingboard
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Copyright (C) 2015 Allen Hill <allenofthehills@gmail.com>
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Portions of the following source code are based on code that is
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copyright (C) 2006 Marcin Slonicki <marcin@softservice.com.pl>
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copyright (C) 2007 Louis Frigon
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <https://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------------
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AVC LAN Theory
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The AVC LAN bus is an implementation of the IEBus (mode 1) which is a
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differential signal; IEBus is electrically (but not logically) compatible with
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CAN bus.
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- Logical `1`: Potential difference between bus lines (BUS+ pin and BUS– pin)
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is 20 mV or lower (floating).
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- Logical `0`: Potential difference between bus lines (BUS+ pin and BUS– pin)
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is 120 mV or higher (driving).
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A nominal bit length is 39 us, composed of 3 periods: preparation,
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synchronization, data.
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Figure 1. AVCLAN Bus bit format
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│ Prep │<─ Sync ─>│<─ Data ─>│ ...
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Driving (logical `0`) ╭──────────╮──────────╮
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│ │ │
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Floating (logical `1`) ─────────╯ ╰──────────╰─────────
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│ 6 μs │── 19 μs ─│─ 13 μs ──│
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The logical value during the data period signifies the bit value, e.g. a bit
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`0` continues the logical `0` (high potential difference between bus lines) of
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the sync period thru the data period, and a bit `1` has a logical `1`
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(low/floating potential between bus lines) during the data period. Using the
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TCB pulse-width and frequency measure mode, the total bit length differs for
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bit `1` and `0`; detailed bit timing can be found in "timing.h". The bus
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idles at low potential (floating).
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A start bit is nominally 169 us high followed by 20 us low.
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A bit `0` is dominant on the bus, which is a design choice that affects
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bit/interpretation:
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- Low addresses have priority upon transmission conflicts
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- The broadcast bit is `1` (floating, no effort) for normal communication
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- For acknowledge bits, the receiver extends the logical '0' of the sync
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period to the length of a normal bit `0`. Hence, a NAK (bit `1`) is
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literally the absence of an ACK.
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--------------------------------------------------------------------------------------
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*/
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/sfr_defs.h>
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#include <stdint.h>
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#include <util/atomic.h>
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#include "avclan_phy.h"
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#include "cdchanger.h" // AVCLAN_isPlaying (startEvent)
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#include "com232.h" // RS232_setRxInterrupt (guard); RS232_Print (Measure)
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#include "media_avr.h" // mediacontrol_syncDuringMask (guard)
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#include "statustimer.h" // statustimer_enable/disable (guard)
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// F_CPU + TICK_US (timing.h) defined here; F_CPU potentially needed by
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// avr-libc.
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#include "timing_avr.h"
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// Name difference between avr-libc and Microchip pack
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#if defined(EVSYS_ASYNCCH00_bm)
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#define EVSYS_ASYNCCH0_0_bm EVSYS_ASYNCCH00_bm
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#endif
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// AVC LAN bus on AC2 (PA6/7): PA6 AINP0 (+), PA7 AINN1 (-)
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#define BUS_IS_IDLE (bit_is_clear(AC2_STATUS, AC_STATE_bp))
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#define READING_BYTE GPIOR1
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#define READING_NBITS GPIOR2
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#define READING_PARITY GPIOR3
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#define TCB_CNTMODE TCB_CNTMODE_PW_gc
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static volatile uint16_t pulsewidth;
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#ifndef NDEBUG
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static volatile uint8_t pulse_count = 0;
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static volatile uint16_t period = 0;
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#endif
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// clang-format off
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static inline void AVCLAN_setBusIdle() {
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__asm__ __volatile__(
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"cbi %[vporta_out], 4; \n\t"
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"sbi %[vportc_out], 0; \n\t"
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::[vporta_out] "I"(_SFR_IO_ADDR(VPORTA_OUT)),
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[vportc_out] "I"(_SFR_IO_ADDR(VPORTC_OUT)));
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}
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static inline void AVCLAN_setBusDriven() {
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__asm__ __volatile__(
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"sbi %[vporta_out], 4; \n\t"
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"cbi %[vportc_out], 0; \n\t"
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::[vporta_out] "I"(_SFR_IO_ADDR(VPORTA_OUT)),
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[vportc_out] "I"(_SFR_IO_ADDR(VPORTC_OUT)));
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}
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// clang-format on
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// Returns true if device TX is muted on the AVCLAN bus (both drive pins are
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// configured as inputs).
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bool AVCLAN_ismuted() {
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return (((VPORTA_DIR & PIN4_bm) | (VPORTA_DIR & PIN0_bm)) == 0);
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}
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// True when the bus is being driven (i.e. not idle/floating).
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bool AVCLAN_busActive() { return !BUS_IS_IDLE; }
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// Mute device TX on AVCLAN bus
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void AVCLAN_muteDevice(bool mute) {
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if (mute) {
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// clang-format off
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__asm__ __volatile__("cbi %[vporta_dir], 4; \n\t" // set as INPUT (output values ignored)
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"cbi %[vportc_dir], 0; \n\t" // set as INPUT (output values ignored)
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::
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[vporta_dir] "I"(_SFR_IO_ADDR(VPORTA_DIR)),
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[vportc_dir] "I"(_SFR_IO_ADDR(VPORTC_DIR)));
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// clang-format on
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} else {
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// clang-format off
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__asm__ __volatile__("sbi %[vporta_dir], 4; \n\t"
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"sbi %[vportc_dir], 0; \n\t"
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::
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[vporta_dir] "I"(_SFR_IO_ADDR(VPORTA_DIR)),
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[vportc_dir] "I"(_SFR_IO_ADDR(VPORTC_DIR)));
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// clang-format on
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}
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}
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// Set AVC bus to `val` (logical 1 or 0) for `period` ticks of TCB1
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static void set_AVC_logic_for(uint8_t val, uint16_t period) {
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TCB1.CNT = 0;
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if (val) {
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AVCLAN_setBusIdle(); // idle bus is logical 1
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} else {
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AVCLAN_setBusDriven();
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}
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while (TCB1.CNT <= period) {};
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return;
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}
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void AVCLAN_sendbit(avclan_bit_t bit) {
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uint16_t zero_length, one_length;
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switch (bit) {
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case bit_zero:
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zero_length = AVCLAN_BIT0_LOGIC_0;
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one_length = AVCLAN_BIT0_LOGIC_1;
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break;
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case bit_one:
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zero_length = AVCLAN_BIT1_LOGIC_0;
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one_length = AVCLAN_BIT1_LOGIC_1;
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break;
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case bit_start:
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zero_length = AVCLAN_STARTBIT_LOGIC_0;
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one_length = AVCLAN_STARTBIT_LOGIC_1;
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break;
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default: __builtin_unreachable();
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}
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set_AVC_logic_for(0, zero_length);
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set_AVC_logic_for(1, one_length);
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}
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void AVCLAN_sendbit_ACK() {
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TCB1.CNT = 0;
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// Wait for controller to begin ACK bit
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while (BUS_IS_IDLE) {
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// Wait for approx the length of a bit; any longer and something has clearly
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// gone wrong
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if (TCB1.CNT >= AVCLAN_BIT_LENGTH_MAX)
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return;
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}
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AVCLAN_sendbit(bit_zero);
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}
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/* Returns true if the peripheral sent an ACK bit.
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An ACK bit is a cooperative bit, where the sender starts (drives the bus) a
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sync period, and allows the receiver to drive the bus (or not) to finish a "1"
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bit.
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*/
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uint8_t AVCLAN_readbit_ACK() {
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TCB1.CNT = 0; // Double reset of TCB1.CNT: here
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set_AVC_logic_for(0, AVCLAN_BIT1_LOGIC_0); // And here (within)
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AVCLAN_setBusIdle(); // Stop driving bus
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while (true) {
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if (!BUS_IS_IDLE && (TCB1.CNT > AVCLAN_READBIT_THRESHOLD))
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break; // ACK
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if (TCB1.CNT > AVCLAN_BIT_LENGTH_MAX)
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return 0; // NAK
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}
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// Check/wait in case we get here before peripheral finishes ACK bit
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while (!BUS_IS_IDLE) {
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if (TCB1.CNT > AVCLAN_BIT_LENGTH_MAX)
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return 0; // NAK
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}
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return 1;
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}
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// Send `len` bits on the AVCLAN bus; returns the even parity
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avclan_bit_t AVCLAN_sendbitsi(const uint8_t *bits, int8_t len) {
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uint8_t b = *bits;
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uint8_t parity = 0;
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int8_t len_mod8 = 8;
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if (len & 0x7) {
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len_mod8 = (int8_t)(len & 0x7);
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b <<= (uint8_t)(8 - len_mod8);
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}
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while (len > 0) {
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len -= len_mod8;
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for (; len_mod8 > 0; len_mod8--) {
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avclan_bit_t bit = (b & 0x80) != 0;
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parity += (uint8_t)bit;
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AVCLAN_sendbit(bit);
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b <<= 1;
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}
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len_mod8 = 8;
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b = *--bits;
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}
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return (parity & 1);
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}
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// Send `len` bits on the AVCLAN bus; returns the even parity
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avclan_bit_t AVCLAN_sendbitsl(const uint16_t *bits, int8_t len) {
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return AVCLAN_sendbitsi((const uint8_t *)bits + 1, len);
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}
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avclan_bit_t AVCLAN_sendbyte(const uint8_t *byte) {
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uint8_t b = *byte;
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uint8_t parity = 0;
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for (uint8_t nbits = 8; nbits > 0; nbits--) {
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avclan_bit_t bit = (b & 0x80) != 0;
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parity += (uint8_t)bit;
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AVCLAN_sendbit(bit);
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b <<= 1;
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}
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return (parity & 1);
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}
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ISR(TCB0_INT_vect) {
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// #ifndef NDEBUG
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// pulse_count++;
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// // PW mode fires on falling edge; measure period as TCB1 delta between
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// // consecutive falling edges (equivalent to FRQPW's rising-to-rising).
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// static uint16_t last_tcb1 = 0;
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// uint16_t cur_tcb1 = TCB1.CNT;
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// period = cur_tcb1 - last_tcb1;
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// last_tcb1 = cur_tcb1;
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// #endif
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READING_BYTE <<= 1;
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// If the logical `0` pulse was less than the sync + data period threshold,
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// bit was a 1
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pulsewidth = TCB0.CCMP;
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if (pulsewidth < (uint16_t)AVCLAN_READBIT_THRESHOLD) {
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READING_BYTE++;
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READING_PARITY++;
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}
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READING_NBITS--;
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}
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// Read `len` bits on the AVCLAN bus; returns the even parity
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uint8_t AVCLAN_readbitsi(uint8_t *bits, uint8_t len) {
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cli();
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READING_BYTE = 0;
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READING_PARITY = 0;
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READING_NBITS = len;
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sei();
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TCB1.CNT = 0;
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while (READING_NBITS) {
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// 200% the duration of `len` bits
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if (TCB1.CNT > ((uint16_t)AVCLAN_BIT_LENGTH_MAX * 2 * len)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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}
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};
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cli();
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*bits = READING_BYTE;
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uint8_t parity = READING_PARITY;
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sei();
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return (parity & 1);
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}
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// Read `len` bits on the AVCLAN bus; returns the even parity
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uint8_t AVCLAN_readbitsl(uint16_t *bits, int8_t len) {
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uint8_t parity = 0;
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if (len > 8) {
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uint8_t over = len - 8;
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parity = AVCLAN_readbitsi((uint8_t *)bits + 1, over);
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len -= over;
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}
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parity += AVCLAN_readbitsi((uint8_t *)bits + 0, len);
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return (parity & 1);
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}
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// Read a byte on the AVCLAN bus
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uint8_t AVCLAN_readbyte(uint8_t *byte) {
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cli();
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READING_BYTE = 0;
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READING_PARITY = 0;
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READING_NBITS = 8;
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sei();
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TCB1.CNT = 0;
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while (READING_NBITS) {
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// 200% the length of a byte
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if (TCB1.CNT > ((uint16_t)AVCLAN_BIT_LENGTH_MAX * 2 * 8)) {
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READING_BYTE = 0;
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READING_PARITY = 0;
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break; // Should have finished by now; something's wrong
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}
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};
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cli();
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*byte = READING_BYTE;
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uint8_t parity = READING_PARITY;
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sei();
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return (parity & 1);
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}
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void AVCLAN_busInit() {
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// Set pin 6 and 7 as input
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PORTA.DIRCLR = (PIN6_bm | PIN7_bm);
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// Disable input buffer; recommended when using AC
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PORTA.PIN6CTRL = PORT_ISC_INPUT_DISABLE_gc;
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// PA7/AINN1(-) additionally gets a pull-up to help prevent the comparator
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// latching high (ie false "driven" bus)
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PORTA.PIN7CTRL = PORT_PULLUPEN_bm | PORT_ISC_INPUT_DISABLE_gc;
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// Analog comparator config
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AC2.CTRLA = AC_OUTEN_bm | AC_HYSMODE_25mV_gc | AC_ENABLE_bm;
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PORTB.DIRSET = PIN2_bm; // Enable AC2 OUT for LED
|
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PORTB.PIN2CTRL = PORT_ISC_INPUT_DISABLE_gc; // Output only
|
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// Set AC2 to generate events on async channel 0
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EVSYS.ASYNCCH0 = EVSYS_ASYNCCH0_AC2_OUT_gc;
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EVSYS.ASYNCUSER0 = EVSYS_ASYNCUSER0_ASYNCCH0_gc; // USER0 is TCB0
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// TCB0 for read bit timing
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TCB0.CTRLB = TCB_CNTMODE;
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TCB0.INTCTRL = TCB_CAPT_bm;
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TCB0.EVCTRL = TCB_CAPTEI_bm;
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||||
TCB0.CTRLA = TCB_CLKSEL | TCB_ENABLE_bm;
|
||||
|
||||
// TCB1 for send bit timing
|
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TCB1.CTRLB = TCB_CNTMODE_INT_gc;
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TCB1.CCMP = 0xFFFF;
|
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TCB1.CTRLA = TCB_CLKSEL | TCB_ENABLE_bm;
|
||||
|
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AVCLAN_setBusIdle();
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AVCLAN_muteDevice(false); // unmute AVCLAN bus TX
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||||
}
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||||
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// Wait for and validate an incoming start bit. On an over-long "driven" bus
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// (AC2 latched high because the bus is actually floating) this kicks PA7 hard
|
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// high to unlatch the comparator. The framing layer maps the result to its own
|
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// error reporting; no printing happens here.
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avclan_readerr_t AVCLAN_readstartbit() {
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uint16_t startbitlen = TCB1.CNT = 0;
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while (!BUS_IS_IDLE) {
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startbitlen = TCB1.CNT;
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if (startbitlen > (uint16_t)AVCLAN_STARTBIT_LOGIC_0 * 1.2) {
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avclan_readerr_t result = rSTARTBIT_TOO_LONG;
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while (!BUS_IS_IDLE) {
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// If bus is "driven" too long, assume the AC2 is latched (e.g.
|
||||
// because the bus is actually floating). Kick it if so.
|
||||
// This should prevent/resolve a flood of "STARTBIT_TOO_LONG" errors
|
||||
if (TCB1.CNT > (uint16_t)(AVCLAN_STARTBIT_LOGIC_0 * 3)) {
|
||||
result = rLATCHED_COMPARATOR;
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||||
PORTA.OUTSET = PIN7_bm; // preset high before enabling the driver
|
||||
PORTA.DIRSET = PIN7_bm; // drive (-) hard high
|
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TCB1.CNT = 0;
|
||||
while (!BUS_IS_IDLE && TCB1.CNT < (uint16_t)AVCLAN_BIT0_LOGIC_1) {
|
||||
// Wait a max of ~6μs until bus is idle
|
||||
}
|
||||
PORTA.DIRCLR = PIN7_bm; // back to high-Z comparator input
|
||||
PORTA.OUTCLR = PIN7_bm;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
}
|
||||
if (startbitlen < (uint16_t)(AVCLAN_STARTBIT_LOGIC_0 * 0.8)) {
|
||||
// We missed the beginning of this message; wait for it to finish (bus
|
||||
// continuously idle for >1 bit length) before returning, so we don't have
|
||||
// multiple false-starts while the in-progress message keeps sending more
|
||||
// bits.
|
||||
TCB1.CNT = 0;
|
||||
while (TCB1.CNT < (uint16_t)(AVCLAN_BIT_LENGTH_MAX * 1.2)) {
|
||||
if (!BUS_IS_IDLE)
|
||||
TCB1.CNT = 0;
|
||||
}
|
||||
return rSTARTBIT_TOO_SHORT;
|
||||
}
|
||||
return rNO_ERROR; // that was a start bit
|
||||
}
|
||||
|
||||
// Acquire the bus and emit a start bit. Returns false if another device is
|
||||
// already driving the bus (we can't yet do proper CSMA/CD).
|
||||
bool AVCLAN_sendstartbit() {
|
||||
// wait for free line
|
||||
TCB1.CNT = 0;
|
||||
while (BUS_IS_IDLE) {
|
||||
// Wait for 120% of a bit length
|
||||
if (TCB1.CNT >= (uint16_t)(AVCLAN_BIT_LENGTH_MAX * 2))
|
||||
break;
|
||||
}
|
||||
|
||||
// End of first loop could be due to bus being driven
|
||||
TCB1.CNT = 0;
|
||||
if (!BUS_IS_IDLE) {
|
||||
// Some other device started sending
|
||||
// Can't yet simultaneously send and receive to do proper CSMA/CD
|
||||
|
||||
// Beginnings of CSMA/CD
|
||||
// do {
|
||||
// if (TCB1.CNT >= (uint16_t)(AVCLAN_STARTBIT_LOGIC_0 * 1.2))
|
||||
// return false; // Something's hinky; nothing is longer than start bit
|
||||
// } while (!BUS_IS_IDLE);
|
||||
// if (TCB1.CNT <= (uint16_t)(AVCLAN_STARTBIT_LOGIC_0 * 0.8))
|
||||
// return false; // Shouldn't be possible
|
||||
// set_AVC_logic_for(1, AVCLAN_STARTBIT_LOGIC_1); // wait for end of start
|
||||
return false;
|
||||
}
|
||||
AVCLAN_sendbit(bit_start);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Disable non-read related interrupts (USART RX, RTC status tick, mic timer)
|
||||
during AVCLAN bus transactions so framing isn't disturbed. TCB0 must remain
|
||||
enabled. */
|
||||
void AVCLAN_stopEvent() {
|
||||
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
|
||||
statustimer_disable();
|
||||
RS232_setRxInterrupt(false);
|
||||
mediacontrol_syncDuringMask();
|
||||
}
|
||||
}
|
||||
|
||||
// Re-enable serial and periodic interrupts after a bus transaction.
|
||||
void AVCLAN_startEvent() {
|
||||
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
|
||||
if (AVCLAN_isPlaying()) // Reenable status interrupt if currently playing
|
||||
statustimer_enable();
|
||||
RS232_setRxInterrupt(true);
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Only used immediately below
|
||||
#define XSTR(x) #x
|
||||
#define STR(x) XSTR(x)
|
||||
|
||||
static uint16_t pulses[100];
|
||||
static uint16_t periods[100];
|
||||
|
||||
void AVCLan_Measure() {
|
||||
AVCLAN_stopEvent();
|
||||
|
||||
uint8_t tmp = 0;
|
||||
|
||||
RS232_Print(
|
||||
"Timing config: F_CPU=" STR(F_CPU) ", TCB_CLKSEL=" STR(TCB_CLKSEL) "\n");
|
||||
RS232_Print("Sampling bit (pulse-width and period) timing...\n");
|
||||
|
||||
for (uint8_t n = 0; n < 100; n++) {
|
||||
while (pulse_count == tmp) {}
|
||||
pulses[n] = pulsewidth;
|
||||
periods[n] = period;
|
||||
tmp = pulse_count;
|
||||
}
|
||||
|
||||
RS232_Print("Pulses:\n");
|
||||
for (uint8_t i = 0; i < 100; i++) {
|
||||
RS232_PrintHex8((uint8_t)(pulses[i] >> 8));
|
||||
RS232_PrintHex8((uint8_t)pulses[i]);
|
||||
RS232_Print("\n");
|
||||
}
|
||||
|
||||
RS232_Print("Periods:\n");
|
||||
for (uint8_t i = 0; i < 100; i++) {
|
||||
RS232_PrintHex8((uint8_t)(periods[i] >> 8));
|
||||
RS232_PrintHex8((uint8_t)periods[i]);
|
||||
RS232_Print("\n");
|
||||
}
|
||||
RS232_Print("\nDone.\n");
|
||||
|
||||
AVCLAN_startEvent();
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user