mirror of
https://github.com/DanielBroad/AVCSniffer
synced 2025-06-07 07:56:29 +00:00
232 lines
4.3 KiB
Plaintext
232 lines
4.3 KiB
Plaintext
** AVCLAN Sniffer PAGE1 **
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*
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* Electronics Workbench
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*
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* This file was created by:
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* Multisim to SPICE netlist routine
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*
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* Generated by: dbroad
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* Friday, November 24 16:37:34, 2006
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*
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*
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VDDVDD VDD 0 dc 5
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VCCVCC VCC 0 dc 12
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cC1 0 VCC 1.000e-005
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cC7 0 VDD 2.200e-005
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xU6 VCC VDD 0 LM2940T_5__VOLTAGE_REGULATOR__1
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.SUBCKT LM2940T_5__VOLTAGE_REGULATOR__1 3 1 2
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* Model Generated by MODPEX *
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*Copyright(c) Symmetry Design Systems*
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* All Rights Reserved *
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* UNPUBLISHED LICENSED SOFTWARE *
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* Contains Proprietary Information *
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* Which is The Property of *
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* SYMMETRY OR ITS LICENSORS *
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*Commercial Use or Resale Restricted *
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* by Symmetry License Agreement *
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* Model generated on Sep 8, 97
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* MODEL FORMAT: SPICE3
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*Rev. Date: Dec. 20, 1994
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*Positive Fixed Regulator
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*External Node Designations
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*node 1: VREG (OUTPUT)
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*node 2: Ground (Common)
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*node 3: Line Voltage
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ECCX 131 2 135 2 1.0
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VXX 133 2 DC 0
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FSET6 2 135 VSENS2 1
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FPP 3 2 VXX 1.0
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R_YY 31 2 1e6
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R_XX 15 2 1e8
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R_ZZ 36 2 1e6
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R_QQ 65 2 1e8
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RXX 1 2 1e8
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VSENS1 10 1 DC 0
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ISET 2 15 DC 1e-3
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DON1 15 16 DMOD1
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VSENS2 16 19 DC 0
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DON2 15 17 DMOD1
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EON2 18 2 3 2 1
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FYY 3 2 VSENS1 1
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DON3 15 27 DMOD1
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VDROP3 28 27 DC 2
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EON3 28 2 3 2 4
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ELINE 13 42 66 2 1
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FSET2 2 36 VSENS2 1
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DSC1 36 35 DMOD1
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RCL1 36 37 10
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DSC2 37 38 DMOD1
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ESCCON 38 39 30 2 1
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VSCCON 39 40 DC 0
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FSC 19 2 VSCCON 1
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FSET3 2 31 VSENS2 1
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DOV1 31 32 DMOD1
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EOV1 32 2 3 1 1
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DOV2 31 33 DMOD1
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ISET4 2 30 DC 1e-3
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ELOAD 41 2 77 2 -1
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ERIPPLE 42 41 72 2 1
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EREF 12 13 19 2 1
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E3 52 2 3 2 1
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CBYPS 54 2 0.001
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VORB 54 60 DC 0
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RB 60 2 1e3
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RBR 72 2 1000
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CBS2 52 71 1
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RSTEP 77 2 1
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FRB 2 65 VORB 1
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DRB2 65 67 DMOD1
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VXRB 67 68 DC -1
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EXRB 68 2 1 2 1
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DRB1 65 66 DMOD1
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RB1 66 2 1000
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.MODEL DMOD1 D
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*-- DMOD1 DEFAULT PARAMETERS
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*IS=1e-14 RS=0 N=1 TT=0 CJO=0
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*VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5
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*KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27
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EXX 132 131 3 131 3.33333e-07
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RST6 135 2 10000
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RIQX 133 132 RQIX 333.333
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.MODEL RQIX R TC1=-0.005
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RSET 19 2 RSET 5000
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.MODEL RSET R TC1=0 TC2=0
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RS1 10 12 0.0368
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VDROPX 18 17 -0.13
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HSENSE1 35 2 VSENS1 5.26316
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RISC 30 2 RISC 10000
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.MODEL RISC R TC1=0
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ROV 34 2 25800
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VOV 33 34 5.2
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EOV2 2 40 34 2 0.183599
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FIQD 3 2 VSENS1 0
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RY 52 54 985222
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RA 72 73 9020.4
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RYR 71 72 3.98007e+06
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CRA 52 73 3.98975e-11
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HSTEP 76 2 VSENS1 0.368
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CSTEP 76 77 5.30516e-06
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.ENDS lm2940t_5
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** AVCLAN Sniffer PAGE2 **
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*
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* Electronics Workbench
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*
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* This file was created by:
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* Multisim to SPICE netlist routine
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*
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* Generated by: dbroad
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* Friday, November 24 16:37:34, 2006
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*
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*
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cC14 0 50 2.2E-11
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cC13 0 51 2.2E-11
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xX1 51 50 CRYSTAL_HC-49/U_15MHZ__CRYSTAL__1
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rR12 VDD 42 1.000e+004
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cC12 9 0 1.0E-7
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rR11 43 0 1.000e+003
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rR10 37 41 1.000e+006
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rR9 VDD 41 3.0k
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rR8 0 37 1.000e+004
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rR7 39 37 180
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rR6 38 40 180
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rR5 38 39 120
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xU10_A 37 40 VDD 0 41 LM139A__COMPARATOR__1
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.SUBCKT CRYSTAL_HC-49/U_15MHZ__CRYSTAL__1 1 2
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* EWB Version 4 - CRYSTAL Model
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* LS= 0.005 CS= 2.2e-014 RS= 10 CO= 5e-012
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LS 1 3 0.005
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CS 3 4 2.2e-014
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RS 4 2 10
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CO 1 2 5e-012
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.ENDS
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* LM139A VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
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* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
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* REV (N/A)
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* CONNECTIONS: NON-INVERTING INPUT
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* | INVERTING INPUT
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* | | POSITIVE POWER SUPPLY
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* | | | NEGATIVE POWER SUPPLY
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* | | | | OPEN COLLECTOR OUTPUT
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* | | | | |
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.SUBCKT LM139A__COMPARATOR__1 1 2 3 4 5
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*
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F1 9 3 V1 1
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IEE 3 7 DC 100.0E-6
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VI1 21 1 DC .75
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VI2 22 2 DC .75
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Q1 9 21 7 QIN
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Q2 8 22 7 QIN
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Q3 9 8 4 QMO
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Q4 8 8 4 QMI
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.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
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.MODEL QMI NPN(IS=800.0E-18 BF=1002)
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.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
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E1 10 4 9 4 1
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V1 10 11 DC 0
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Q5 5 11 4 QOC
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.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
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DP 4 3 DX
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RP 3 4 46.3E3
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.MODEL DX D(IS=800.0E-18)
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.ENDS
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** AVCLAN Sniffer PAGE3 **
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*
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* Electronics Workbench
|
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*
|
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* This file was created by:
|
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* Multisim to SPICE netlist routine
|
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*
|
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* Generated by: dbroad
|
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* Friday, November 24 16:37:34, 2006
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*
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*
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cC5 55 0 1.000e-006
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cC6 VDD 56 1.000e-006
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cC3 53 54 1.000e-006
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cC4 49 52 1.000e-006
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